Design and Implementation of a delay and area efficient 32x32bit Vedic Multiplier using Brent Kung Adder

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1 Design and Implementation of a delay and area efficient 32x32bit Vedic Multiplier using Brent Kung Adder #1 Ayushi Sharma, #2 Er. Ajit Singh #1 M.Tech. Student, #2 Assistant Professor and Faculty Guide, EC Department (VLSI DESIGN), A.P.J. ABDUL KALAM TECHNICAL UNIVERSITY, LUCKNOW, Uttar Pradesh Ideal Institute of Technology, Ghaziabad, Uttar Pradesh, INDIA Abstract: This paper proposed the design of a delay and area efficient 32x32bit Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. BRENT KUNG ADDER, modified Ripple Carry Adder and modified Kogge Stone adders are used to design proposed 32x32bit Vedic Multiplier. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. The work has proved the efficiency of Urdhva Tiryakbhyam Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm with the compatibility to different data types. Urdhva Tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large. Further, the Verilog HDL coding of Urdhva Tiryakbhyam Sutra for 32x32 bits multiplication have been done and it is synthesized using XILINX ISE 14.1 and implemented on Spartan 6 FPGA board. The work has proved that area and delay of proposed Vedic multiplier are less than existing Vedic multipliers. Keywords Multipliers, Urdhva Tiryakbhyam, Brent Kung Adder (BKA), Ripple Carry Adder(RCA), Kogge Stone Adder, Verilog HDL. I. INTRODUCTION Multipliers have an important effect in designing arithmetic, signal and image processors. Many important functions in such processors make use of multipliers. Many current DSP applications are targeted at portable, battery-operated systems, due to which power dissipation becomes one of the primary design constraints. The multiplier is generally the slowest element in the system hence system s performance is generally determined by the performance of the multiplier. At the same time, multipliers are the most area consuming elements in the system. Power dissipation in a multiplier is a very important issue as it shows the total power dissipated by the device. Hence it affects the device s overall performance. As multipliers are the main component of many handheld devices, the power requirements are more stringent for them. Hence there is a requirement of efficient low power and low area multipliers. A multiplier is typically composed of three stages partial product generation stage, partial product addition stage and final addition stage. In the first stage, multiplicand and multiplier are multiplied bit by bit to generate partial products. The second stage is the most important stage as it is the most complicated and determines the speed and power consumption of overall multiplier. The addition of the partial products contributes most to the overall delay, area and power consumption due to which the demand of high speed and low power adders is continuously increasing. II. VEDIC MULTIPLIER The proposed multiplier depends on Urdhva Tiryakbhyam (UT) sutra. Urdhva Tiryakbhyam Urdhva Tiryakbhyam is taken from the Sanskrit. Urdhva signifies Vertically and Tiryakbhyam signifies Crosswise. The UT sutra can be connected to all instances of multiplication, for example- binary, decimal, hexadecimal, octal, etc. 1) 2x2bit Vedic Multiplier It is synthesized using 2bit Kogge Stone Adder (KSA) as shown in Fig.2 and one 1-bit adder, one 1-bit xor and one 2-bit xor. Fig.1 2bit Kogge Stone Adder ISSN: Page 393

2 Fig.2 Vedic Multiplier 2x2bit using 2bit KSA 2) 4x4bit Vedic Multiplier It is synthesized using four 2x2bit Vedic multipliers using four 2x2bit Vedic Multipliers using KSA and one 4bit KSA as shown in Fig.4. It consists of nine 1-bit adders, two 6-bit adders (i.e. total 11 adders/subtractors) and seven 1-bit xor, four 2-bit xor and one 4-bit xor (total 12 xors). Fig.4 Vedic Multiplier 4x4bit 3) 8x8bit Vedic Multiplier It is synthesized using four 4x4bit Vedic Multipliers using KSA and one 8 bit Kogge stone adder as shown in Fig.5. It consists of total 61 adders/subtractors, thirty five 1- bit xors, sixteen 2-bit xors, four 4-bit xors and one 1-bit xor (total 56 xors). Fig.3 4bit KSA Fig.5 Vedic Multiplier 8x8bit 4) 16x16bit Vedic Multiplier It is synthesized using four 8x8 bit Vedic Multipliers using KSA and one 16-bit Kogge stone adder as shown in Fig.6. It consists of total 276 adders/subtractors and 155 one-bit xors, sixty four 2-bit xors, sixteen 4-bit xors and six 8-bit xor (total 241 xors). ISSN: Page 394

3 IV. Brent Kung Adder The Brent Kung adder computes the prefixes for 2 bit groups. These prefixes are used to find the prefixes for the 4 bit groups, which in turn are used to compute the prefixes for 8 bit groups and so on. These prefixes are then used to compute the carry out of the particular bit stage. These carries will be used along with the Group Propagate of the next stage to compute the Sum bit of that stage. Brent Kung Tree will be using 2log 2 N - 1 stages. Since we are designing a 32-bit adder the number of stages will be 9. The fanout for each bit stage is limited to 2. The diagram below shows the fan out being minimized and the loading on the further stages being reduced. But while actually implemented the buffers are generally omitted. Fig.6 Vedic Multiplier 16x16bit III. Proposed 32x32 bit Vedic Multiplier It is synthesized using four 16x16 bit Vedic Multipliers using modified KSA and Brent Kung Adder and one 32-bit kogge stone adder and BKA as shown in Fig.7. It consists of total 918 adders/subtractors and 651 one-bit xors, bit xors, sixty four 4-bit xors and twenty eight 8-bit xors (i.e. total 999 xors). 1) CARRY GENERATION AND CARRY PROPAGATION IN BRENT KUNG ADDER Some generalized Equations of Carry Generate Signals (G) and Carry Propagate Signals (P) are: P[i] =A[i] xor B[i] and G[i] =A[i] and B[i] Sum[i] =P[i] xor C[i-1] C[i] = (P[i] and C[i-1]) +G[i] The working procedure of BKA can be easily explained as follows: Pre-processing: In this step, the generate and propagate signals for each pair of bits are computed. Below equations represent this step: P=Ai xor Bi G=Ai and Bi Ci=Gi Carry Look Ahead Network: This block makes this adder distinct from other adders and is the key block behind its high performance. Int this block intermediate carries are computed and represented by the following equations: Pi:j=Pi:k+1 and Pk:j Gi:j= (Pi:k+1 and Gk:j) or Gi:k+1 Post-Processing: In this final step, the sum bits are computed as given by the following equation: Si=Pi xor Ci-1 Fig.8 shows a 16-bit Brent Kung Adder Fig.7 Vedic Multiplier 32x32bit ISSN: Page 395

4 RESULTS Fig.8 16-bit Brent Kung Adder Simulation results of 16x16 bit Vedic Multiplier in binary and decimal is shown in Fig.9 Fig.9 Simulation Results of 16x16bit Vedic Multiplier in Binary and Decimal ISSN: Page 396

5 Multipliers Table I Comparison of 16x16bit Vedic Multipliers Existing Modified Existing Multiplier using Multiplier using Multiplier RCA Modified RCA using Kogge Modified Multiplier using modified Kogge Stone Adder Vedic Multiplier using Brent Kung Adder Stone Adder Delay(ns) No. of LUTs Simulation results of 32x32 bit Vedic Multiplier in binary and decimal is shown in Fig.10 Multipliers Fig.10 Simulation Results of 32x32bit Vedic Multiplier in binary and decimal Existing Multiplier using RCA Table II Comparison of 32x32bit Vedic Multipliers Modified Existing Modified Multiplier Multiplier Multiplier using Modified using Kogge using modified RCA Stone Adder Kogge Multiplier using Brent Kung Adder Stone Adder Delay(ns) No. of LUTs CONCLUSION In our design, efforts have been made to reduce the area and propagation delay and achieved an improvement in the reduction of maximum combinational path delay with 51% when compared to array multiplier, booth multiplier and conventional Vedic multiplier implementation on XILINX software. It is coded in Verilog HDL and synthesized using XILINX ISE ISSN: Page 397

6 The proposed 32x32bit Vedic multiplier architecture has been designed and synthesized using Spartan 6 XC6SLX4 board. The proposed Vedic Multiplier with Brent Kung Adder is compared with the existing Vedic multiplier using Kogge Stone Adder and ripple carry adder and can be inferred that proposed architecture is faster compared to existing Vedic multiplier. The work has proved that delay of proposed Vedic multiplier is less than the existing 32 bit Vedic Multipliers. In comparison to existing Vedic Multiplier using Kogge Stone Adder, modified 16x16bit Vedic Multiplier using modified Kogge Stone Adder has delay reduction of % and area reduction is of 9.983%.In comparison to existing 32x32bit Vedic multiplier that is synthesized using Kogge Stone Adder, the delay of proposed 32x32bit Vedic Multiplier using Brent Kung Adder, is reduced from 38.63ns to ns i.e % reduction in delay and 5.190% reduction in area. In future the proposed multiplier performance parameters can be improved by high level pipelining operations and applied in signal processing applications like image processing and video processing. Advanced Research In Computer Science and Software Engineering (ijarcsse), Volume 6, issue 6, June Pankaj Prajapati, Nitish Raghuvanshi and Anurag Rishishwar, Analysis Parameter of Area Efficient Vedic Multiplier using Barrel Shifter, International Journal of Advanced Research In Computer Science and Software Engineering (ijarcsse), Volume 6, issue 2, Feb RAJARAPU KRISHNANJANEYULU and Y.KONDAIAH, Area Efficient and High Speed Vedic Multiplier Using Different Compressors, International Journal of Computer Engineering in Research Trends (ijcert), Volume 2, issue 10, Oct Nikita Jain, Jitendra Jain and Krishna Kant Nayak, Area Efficient High Speed Vedic Multiplier using Common Boolean Logic, International Journal of Computer Applications (ijca), Volume No.2, Dec Nidhi Pokhriyal and Neelam Rup Prakash, Area Efficient Low Power Vedic Multiplier Design Using GDI Technique, International Journal of Engineering Trends and Technology (IJETT) Volume 15 Number 4 Sep Nidhi Pokhriyal, Harsimranjit Kaur and Neelam Rup Prakash, Compressor Based Area-Efficient Low-Power 8x8 Vedic Multiplier, Nidhi Pokhriyal et al Int. Journal of Engineering Research and Applications, Vol. 3, Issue 6, Nov-Dec SCOPE FOR FUTURE WORK Brent Kung Adders and Kogge Stone Adders are the fastest adders with more hardware utilization. The delay and area of multipliers can further be reduced if the fastest adders other than Brent Kung and Kogge Stone Adders are designed thereby achieving High Speed Vedic Multipliers. APPLICATIONS 1. The beauty of Vedic Multiplier lies in the fact that they can be used to solve cumbersome mathematical operations orally thereby improving speed. 2. Multipliers being the key components of Arithmetic and logic units, Digital signal processing blocks and Multiplier and accumulate units, determine the performance and throughput of the applications. 3. Vedic Multiplier has become highly popular as a faster method for computation and analysis. They have found immense use in applications of image processing to save time and area. Image processing is the application of certain operations on images such as image sharpening, pattern recognition, edge detection etc., to extract some useful information from them or to enhance a particular feature in it. Hence it is essential in fields of mapping, holography, x-ray imaging, medical image processing and robotics. REFERENCES 1. Mahadevappa Mugalihal and Dr. TC Thanuja, Design and Implementation of a 32bitx32bit Vedic Multiplier using Kogge Stone Adder, International Journal of ISSN: Page 398