HIGHLY EFFICIENT INTEGRATED 2A SYNCHRONOUS BUCK REGULATOR

Transcription

1 SupIRBuck TM Features Wide Input ltage Range.5 t 6 Wide Output ltage Range 0.7 t 0.9*in Cntinuus 2A Lad Capability Integrated Btstrap-dide High Bandwidth E/A fr excellent transient perfrmance Prgrammable Switching Frequency up t.5mhz Prgrammable Over Current Prtectin PGd utput Hiccup Current Limit Precisin Reference ltage (0.7, +/-%) Prgrammable Sft-Start Enable Input with ltage Mnitring Capability Enhanced Pre-Bias Start-up Seq input fr Tracking applicatins -40 C t 25 C perating junctin temperature Thermal Prtectin Multiple current ratings in pin cmpatible ftprint 5mm x 6mm Pwer QFN Package, 0.9 mm height Lead-free, halgen-free and RHS cmpliant Applicatins Server Applicatins Strage Applicatins Embedded Telecm Systems Distributed Pint f Lad Pwer Architectures Descriptin PD HIGHLY EFFICIENT INTEGRATED 2A SYNCHRONOUS BUCK REGULATOR.5 <in<6 The IR84W SupIRBuck TM is an easy-t-use, fully integrated and highly efficient DC/DC synchrnus Buck regulatr. The MOSFETs cpackaged with the n-chip PWM cntrller make IR84W a space-efficient slutin, prviding accurate pwer delivery fr lw utput vltage applicatins. IR84W is a versatile regulatr which ffers prgrammability f start up time, switching frequency and current limit while perating in wide input and utput vltage range. The switching frequency is prgrammable frm 250kHz t.5mhz fr an ptimum slutin. It als features imprtant prtectin functins, such as Pre-Bias startup, hiccup current limit and thermal shutdwn t give required system level security in the event f fault cnditins. Netcm Applicatins Cmputing Peripheral ltage Regulatrs General DC-DC Cnverters 4.5 <cc<5.5 Seq Enable in Bt cc SW PGd PGd OCSet Rt Fb SS/ SD Gnd Cmp PGnd Fig.. Typical applicatin diagram

2 ABSOLUTE MAXIMUM RATINGS (ltages referenced t GND unless therwise specified) in. -0. t 25 cc t 8 (Nte2) Bt t SW t 25(DC), -4 t 25(AC, 00ns) Bt t SW t cc+0. (Nte) OCSet t 0, 0mA Input / utput Pins t cc+0. (Nte) PGND t GND t +0. Strage Temperature Range C T 50 C Junctin Temperature Range C T 50 C (Nte2) ESD Classificatin JEDEC Class C Misture sensitivity level... JEDEC Level 2@260 C (Nte5) Nte: Must nt exceed 8 Nte2: cc must nt exceed 7.5 fr Junctin Temperature between -0 C and -40 C Stresses beynd thse listed under Abslute Maximum Ratings may cause permanent damage t the device. These are stress ratings nly and functinal peratin f the device at these r any ther cnditins beynd thse indicated in the peratinal sectins f the specificatins are nt implied. PACKAGE INFORMATION 5mm x 6mm POWER QFN SW IN 2 0 PGnd θ θ JA J-PCB 5 C / W 2 C / W Bt Enable 4 5 Gnd 9 8 CC PGd ORDERING INFORMATION Seq FB COMP Gnd Rt SS OCSet PACKAGE DESIGNATOR PACKAGE DESCRIPTION PIN COUNT PARTS PER REEL M IR84WMTRPbF M IR84WMTRPbF

3 Blck Diagram Fig. 2. Simplified blck diagram f the IR84W

4 Pin Descriptin Pin Name Descriptin Seq 2 Fb Cmp Sequence pin. Use tw external resistrs t set Simultaneus Pwer up sequencing. If this pin is nt used cnnect t cc. Inverting input t the errr amplifier. This pin is cnnected directly t the utput f the regulatr via resistr divider t set the utput vltage and prvide feedback t the errr amplifier. Output f errr amplifier. An external resistr and capacitr netwrk is typically cnnected frm this pin t Fb pin t prvide lp cmpensatin. 4 Gnd Signal grund fr internal reference and cntrl circuitry. 5 Rt 6 SS/SD 7 OCSet 8 PGd 9 CC 0 PGnd Set the switching frequency. Cnnect an external resistr frm this pin t Gnd t set the switching frequency. Sft start / shutdwn. This pin prvides user prgrammable sft-start functin. Cnnect an external capacitr frm this pin t Gnd t set the start up time f the utput vltage. The cnverter can be shutdwn by pulling this pin belw 0.. Current limit set pint. A resistr frm this pin t SW pin will set the current limit threshld. Pwer Gd status pin. Output is pen drain. Cnnect a pull up resistr frm this pin t cc. If unused, it can be left pen. This pin pwers the internal IC and the drivers. A minimum f uf high frequency capacitr must be cnnected frm this pin t the pwer grund (PGnd). Pwer Grund. This pin serves as a separated grund fr the MOSFET drivers and shuld be cnnected t the system s pwer grund plane. SW Switch nde. This pin is cnnected t the utput inductr. 2 IN Input vltage cnnectin pin. Bt 4 Enable Supply vltage fr high side driver. A 0.uF capacitr must be cnnected frm this pin t SW. Enable pin t turn n and ff the device. Use tw external resistrs t set the turn n threshld (see Enable sectin). Cnnect this pin t cc if it is nt used. 5 Gnd Signal grund fr internal reference and cntrl circuitry. 4

5 Recmmended Operating Cnditins Symbl Definitin Min Max Units in Input ltage.5 6 cc Supply ltage Bt t SW Supply ltage Output ltage *in I Output Current 0 2 A Fs Switching Frequency khz T j Junctin Temperature C Electrical Specificatins Unless therwise specified, these specificatin apply ver 4.5< cc <5.5, in 2, 0 C<T j < 25 C. Typical values are specified at T a 25 C. Pwer Lss Parameter Symbl Test Cnditin Min TYP MAX Units Pwer Lss P lss cc5, in2,.8, I 2A, Fs600kHz, L.uH, Nte W MOSFET R ds(n) Tp Switch R ds(n)_tp Bt -sw 5, ID2A, Tj25 C Bttm Switch R ds(n)_bt cc5, ID2A, Tj25 C mω Reference ltage Feedback ltage FB 0.7 Accuracy Supply Current 0 C<Tj<25 C C<Tj<25 C, Nte % CC Supply Current (Standby) I CC(Standby) SS0, N Switching, Enable lw 500 μa cc Supply Current (Dyn) I CC(Dyn) SS, cc5, Fs500kHz Enable high Under ltage Lckut 0 ma CC-Start-Threshld CC_ULO_Start cc Rising Trip Level CC-Stp-Threshld CC_ULO_Stp cc Falling Trip Level Enable-Start-Threshld Enable_ULO_Start Supply ramping up Enable-Stp-Threshld Enable_ULO_Stp Supply ramping dwn Enable leakage current Ien Enable. 5 μa 5

6 Electrical Specificatins (cntinued) Unless therwise specified, these specificatins apply ver 4.5< cc <5.5, in 2, 0 C<T j < 25 C. Typical values are specified at T a 25 C. Oscillatr Parameter Symbl Test Cnditin Min TYP MAX Units Rt ltage Frequency FS Rt59K Rt28.7K khz Rt9.K, Nte Ramp Amplitude ramp Nte4.8 p-p Ramp Offset Ramp (s) Nte4 0.6 Min Pulse Width Dmin(ctrl) Nte4 00 Fixed Off Time Nte ns Max Duty Cycle Dmax Fs250kHz 92 % Errr Amplifier Input Offset ltage s fb-seq, m seq0.8 Input Bias Current IFb(E/A) - + μa Input Bias Current Ip(E/A) - + Sink Current Isink(E/A) Surce Current Isurce(E/A) 8 0 ma Slew Rate SR Nte /μs Gain-Bandwidth Prduct GBWP Nte MHz DC Gain Gain Nte db Maximum ltage max(e/a) cc Minimum ltage min(e/a) m Cmmn Mde ltage Nte4 0 Sft Start/SD Sft Start Current ISS Surce μa Sft Start Clamp ltage ss(clamp) Shutdwn Output Threshld SD 0. Over Current Prtectin OCSET Current IOCSET Fs250kHz Fs500kHz μa Fs500kHz OC Cmp Offset ltage OFFSET Nte m SS ff time SS_Hiccup 4096 Cycles Btstrap Dide Frward ltage I(Bt)0mA m Deadband Deadband time Nte ns 6

7 Electrical Specificatins (cntinued) Unless therwise specified, these specificatin apply ver 4.5< cc <5.5, in 2, 0 C<T j < 25 C. Typical values are specified at T a 25 C. Parameter SYM Test Cnditin Min TYP MAX Units Thermal Shutdwn Thermal Shutdwn Nte4 40 C Hysteresis Nte4 20 Pwer Gd Pwer Gd upper PG(upper) Fb Rising Threshld Upper Threshld PG(upper)_Dly Fb Rising 256/Fs s Delay Pwer Gd lwer PG(lwer) Fb Falling Threshld Lwer Threshld PG(lwer)_Dly Fb Falling 256/Fs s Delay Delay Cmparatr PG(Delay) Relative t charge vltage, SS rising Threshld Delay Cmparatr Delay(hys) Nte m Hysteresis PGd ltage Lw PG(vltage) I PGd -5mA 0.5 Leakage Current I leakage 0 0 μa Switch Nde SW Bias Current Isw SW0, Enable0 SW0,Enablehigh,SS,seq0, Nte4 6 μa Nte: Cld temperature perfrmance is guaranteed via crrelatin using statistical quality cntrl. Nt tested in prductin. Nte4: Guaranteed by Design but nt tested in prductin. Nte5: Upgrade t industrial/msl2 level applies frm date cdes 227 (marking explained n applicatin nte AN2 page 2). Prducts with prir date cde f 227 are qualified with MSL fr Cnsumer market. 7

8 TYPICAL OPERATING CHARACTERISTICS (-40 C - 25 C) F s 500 khz [ua] [khz] Icc(Standby) Temp[ C] FREQUENCY Temp[ C] [ma] [ua] Ic(Dyn) Temp[ C] IOCSET(500kHz) Temp[ C] 4.46 cc(ulo) Start 4.6 cc(ulo) Stp [] 4.26 [] Temp[ C] Temp[ C] [] Enable(ULO) Start Temp[ C] [] Enable(ULO) Stp Temp[ ο C] 26.0 ISS fb [ua] [m] Temp[ C] Temp[ C] 8

9 Rdsn f MOSFETs Over Temperature at cc5 Nte: Ctrl-FET and Sync-FET are identical Resistance [mω] Temperature [ C] Ctrl-FET/Sync-FET 9

10 Typical Efficiency and Pwer Lss Curves in2, cc5, I0.2A-2A, F s 600kHz, Rm Temperature, N Air Flw The table belw shws the inductrs used fr each f the utput vltages in the efficiency measurement. PD ut () L (uh) P/N DCR (mω) IHLP2525EZ-0 2.2uH 2.2 IHLP2525EZ-0 2.2uH. 2.2 IHLP2525EZ-0 2.2uH IHLP2525EZ-0 2.2uH.5. IHLP2525EZ-0.uH IHLP2525EZ-0.uH IHLP2525EZ-0 4.7uH IHLP2525EZ-0 4.7uH IHLP2525EZ-0 5.6uH 2.7 Efficiency (%) Iut (A) Pwer Lss (W) Iut (A)

11 Typical Efficiency and Pwer Lss Curves in5, cc5, I0.2A-2A, F s 600kHz, Rm Temperature, N Air Flw The table belw shws the inductrs used fr each f the utput vltages in the efficiency measurement. PD ut () L (uh) P/N DCR (mω) PCMB065T-R5MS PCMB065T-R5MS PCMB065T-R5MS IHLP2525EZ-0 2.2uH. 2.2 IHLP2525EZ-0 2.2uH IHLP2525EZ-0 2.2uH IHLP2525EZ-0 2.2uH IHLP2525EZ-0 2.2uH 2.5. IHLP2525EZ-0.uH IHLP2525EZ-0 2.2uH Efficiency (%) Iut (A) Pwer Lss (W) Iut (A)

12 Circuit Descriptin THEORY OF OPERATION Intrductin The IR84W uses a PWM vltage mde cntrl scheme with external cmpensatin t prvide gd nise immunity and maximum flexibility in selecting inductr values and capacitr types. The switching frequency is prgrammable frm 250kHz t.5mhz and prvides the capability f ptimizing the design in terms f size and perfrmance. IR84W prvides precisely regulated utput vltage prgrammed via tw external resistrs frm 0.7 t 0.9*in. The IR84W perates with an external bias supply frm 4.5 t 5.5, allwing an extended perating input vltage range frm.5 t 6. If the input t the Enable pin is derived frm the bus vltage by a suitably prgrammed resistive divider, it can be ensured that the IR84W des nt turn n until the bus vltage reaches the desired level. Only after the bus vltage reaches r exceeds this level will the vltage at Enable pin exceed its threshld, thus enabling the IR84W. Therefre, in additin t being a lgic input pin t enable the IR84W, the Enable feature, with its precise threshld, als allws the user t implement an Under-ltage Lckut fr the bus vltage in. This is desirable particularly fr high utput vltage applicatins, where we might want the IR84W t be disabled at least until in exceeds the desired utput vltage level. The device utilizes the n-resistance f the lw side MOSFET as current sense element, this methd enhances the cnverter s efficiency and reduces cst by eliminating the need fr external current sense resistr. IR84W includes tw lw R ds(n) MOSFETs using IR s HEXFET technlgy. These are specifically designed fr high efficiency applicatins. Under-ltage Lckut and POR The under-vltage lckut circuit mnitrs the input supply cc and the Enable input. It assures that the MOSFET driver utputs remain in the ff state whenever either f these tw signals drp belw the set threshlds. Nrmal peratin resumes nce cc and Enable rise abve their threshlds. The POR (Pwer On Ready) signal is generated when all these signals reach the valid lgic level (see system blck diagram). When the POR is asserted the sft start sequence starts (see sft start sectin). Fig. a. Nrmal Start up, Device turns n when the Bus vltage reaches 0.2 Figure b. shws the recmmended start-up sequence fr the nn-sequenced peratin f IR84W. Enable The Enable features anther level f flexibility fr start up. The Enable has precise threshld which is internally mnitred by Under-ltage Lckut (ULO) circuit. Therefre, the IR84W will turn n nly when the vltage at the Enable pin exceeds this threshld, typically,.2. Fig. b. Recmmended startup sequence, Nn-Sequenced peratin Figure c. shws the recmmended startup sequence fr sequenced peratin f IR84W 2

13 Fig. 5. Pre-Bias startup pulses Fig. c. Recmmended startup sequence, Sequenced peratin Pre-Bias Startup IR84W is able t start up int pre-charged utput, which prevents scillatin and disturbances f the utput vltage. The utput starts in asynchrnus fashin and keeps the synchrnus MOSFET ff until the first gate signal fr cntrl MOSFET is generated. Figure 4 shws a typical Pre-Bias cnditin at start up. The synchrnus MOSFET always starts with a narrw pulse width and gradually increases its duty cycle with a step f 25%, 50%, 75% and 00% until it reaches the steady state value. The number f these startup pulses fr the synchrnus MOSFET is internally prgrammed. Figure 5 shws a series f 2, 6, 8 startup pulses. Sft-Start The IR84W has a prgrammable sft-start t cntrl the utput vltage rise and t limit the current surge at the start-up. T ensure crrect start-up, the sft-start sequence initiates when the Enable and cc rise abve their ULO threshlds and generate the Pwer On Ready (POR) signal. The internal current surce (typically 20uA) charges the external capacitr C ss linearly frm 0 t. Figure 6 shws the wavefrms during the sft start. The start up time can be estimated by: T start (.4-0.7) * C 20μA SS () During the sft start the OCP is enabled t prtect the device fr any shrt circuit and ver current cnditin. Fig. 4. Pre-Bias startup Fig. 6. Theretical peratin wavefrms during sft-start

14 Operating Frequency The switching frequency can be prgrammed between 250kHz 500kHz by cnnecting an external resistr frm R t pin t Gnd. Table tabulates the scillatr frequency versus R t. Table. Switching Frequency and I OCSet vs. External Resistr (R t ) R t (kω) F s (khz) I cset (μa) Shutdwn The IR84W can be shutdwn by pulling the Enable pin belw its threshld. This will tristate bth, the high side driver as well as the lw side driver. Alternatively, the utput can be shutdwn by pulling the sft-start pin belw 0.. Nrmal peratin is resumed by cycling the vltage at the Sft Start pin. Over-Current Prtectin The ver current prtectin is perfrmed by sensing current thrugh the R DS(n) f lw side MOSFET. This methd enhances the cnverter s efficiency and reduces cst by eliminating a current sense resistr. As shwn in figure 7, an external resistr (R OCSet ) is cnnected between OCSet pin and the switch nde (SW) which sets the current limit set pint. An internal current surce surces current (I OCSet ) ut f the OCSet pin. This current is a functin f the switching frequency and hence, f R t. Table. shws I OCSet at different switching frequencies. The internal current surce develps a vltage acrss R OCSet. When the lw side MOSFET is turned n, the inductr current flws thrugh the Q2 and results in a vltage at OCSet which is given by: OCSet ( IOCSet ROCSet ) ( R ) I DS(n L )...() Fig. 7. Cnnectin f ver current sensing resistr An ver current is detected if the OCSet pin ges belw grund. Hence, at the current limit threshld, OCset 0. Then, fr a current limit setting I Limit,R OCSet is calculated as fllws: R I OCSet OCSet 400 (μa)...(2) R (kω) R DS( n) * I t OCSet I Limit......(4) An vercurrent detectin trips the OCP cmparatr, latches OCP signal and cycles the sft start functin in hiccup mde. The hiccup is perfrmed by shrting the sft-start capacitr t grund and cunting the number f switching cycles. The Sft Start pin is held lw until 4096 cycles have been cmpleted. The OCP signal resets and the cnverter recvers. After every sft start cycle, the cnverter stays in this mde until the verlad r shrt circuit is remved. The OCP circuit starts sampling current typically 60 ns after the lw gate drive rises t abut. This delay functins t filter ut switching nise. 4

15 Thermal Shutdwn Temperature sensing is prvided inside IR84W. The trip threshld is typically set t 40 C. When trip threshld is exceeded, thermal shutdwn turns ff bth MOSFETs and discharges the sft start capacitr. Autmatic restart is initiated when the sensed temperature drps within the perating range. There is a 20 C hysteresis in the thermal shutdwn threshld..5 <in<6 4.5 <cc<5.5 PGd Enable cc PGd Seq Rt SS/ SD Gnd in Bt SW OCSet Fb Cmp PGnd RA RB (master) Output ltage Sequencing The IR84W can accmmdate user prgrammable sequencing using Seq, Enable and Pwer Gd pins..5 <in<6 4.5 <cc<5.5 Enable in Bt (master) cc SW (slave) PGd 2 RE RF PGd Seq Rt OCSet Fb RC RD SS/ SD Gnd Cmp PGnd Simultaneus Pwerup Fig. 8a. Simultaneus Pwer-up f the slave with respect t the master. Thrugh these pins, vltage sequencing such as simultaneus and sequential can be implemented. Figure 8. shws simultaneus sequencing cnfiguratins. In simultaneus pwer-up, the vltage at the Seq pin f the slave reaches 0.7 befre the Fb pin f the master. Fr R E /R F R C /R D, therefre, the utput vltage f the slave fllws that f the master until the vltage at the Seq pin f the slave reaches 0.7. After the vltage at the Seq pin f the slave exceeds 0.85, the internal 0.7 reference f the slave dictates its utput vltage. It is recmmended that irrespective f the sequencing cnfiguratin used, the input vltage shuld be allwed t cme up t its nminal value first, fllwed by cc and Enable, befre the sequencing signal is applied. Fr nn-sequenced peratin, the Seq pin shuld be tied t a vltage greater than 0.85, such as. r cc. Again, the input vltage shuld be allwed t cme up befre cc and Enable. Fig. 8b. Applicatin Circuit fr Simultaneus Sequencing Pwer Gd Output The IC cntinually mnitrs the utput vltage via Feedback (Fb pin). The feedback vltage frms an input t a windw cmparatr whse upper and lwer threshlds are and respectively. Hence, the Pwer Gd signal is flagged when the Fb pin vltage is within the PGd windw, i. e., between t 0.805, as shwn in Fig.9 The PGd pin is pen drain and it needs t be externally pulled high. High state indicates that utput is in regulatin. Fig. 9a shws the PGd timing diagram fr nntracking peratin. In this case, during startup, PGd ges high after the SS vltage reaches 2. if the Fb vltage is within the PGd cmparatr windw. Fig. 9a. and Fig 9.b. als shw a 256 cycle delay between the Fb vltage entering within the threshlds defined by the PGd windw and PGd ging high. 5

16 TIMING DIAGRAM OF PGOOD FUNCTION PD Fig.9a IR84W Nn-Tracking Operatin (Seqcc) Fig.9b IR84W Tracking Operatin 6

17 Minimum n time Cnsideratins The minimum ON time is the shrtest amunt f time fr which the Cntrl FET may be reliably turned n, and this depends n the internal timing delays. Fr the IR84W, the typical minimum n-time is specified as 00 ns. Any design r applicatin using the IR84W must ensure peratin with a pulse width that is higher than this minimum n-time and preferably higher than 50 ns. This is necessary fr the circuit t perate withut jitter and pulseskipping, which can cause high inductr current ripple and high utput vltage ripple. In any applicatin that uses the IR84W, the fllwing cnditin must be satisfied: t t n n(min) t n(min) in D F s in F t s n ut F The minimum utput vltage is limited by the reference vltage and hence ut(min) 0.7. Therefre, fr ut(min) 0.7, s ut F in t ut s n(min) Maximum Duty Rati Cnsideratins A fixed ff-time f 200 ns maximum is specified fr the IR84W. This prvides an upper limit n the perating duty rati at any given switching frequency. It is clear that, higher the switching frequency, the lwer is the maximum duty rati at which the IR84W can perate. T allw a margin f 50ns, the maximum perating duty rati in any applicatin using the IR84W shuld still accmmdate abut 250 ns ff-time. Fig 0. shws a plt f the maximum duty rati v/s the switching frequency, with 250 ns ff-time. Max Duty Cycle (%) Max Duty Cycle Switching Frequency (khz) Fig. 0. Maximum duty cycle v/s switching frequency. in F in s F t s ut(min) n(min) ns /s Therefre, at the maximum recmmended input vltage 6 and minimum utput vltage, the cnverter shuld be designed at a switching frequency that des nt exceed 290 khz. Hwever, practical cnsideratins dictate that any applicatin that demands a pulse width smaller than 75ns may nt exhibit jitter free peratin ver the entire lad range. This means that fr 6 input vltage, the peratin frequency shuld be limited t 250 khz. 7

18 Applicatin Infrmatin Design Example: The fllwing example is a typical applicatin fr IR84W. The applicatin circuit is shwn n page 2. Enabling the IR84W As explained earlier, the precise threshld f the Enable lends itself well t implementatin f a ULO fr the Bus ltage. Fr a typical Enable threshld f EN.2 Fr a in (min) 0.2, R 49.9K and R 2 7.5K is a gd chice. Prgramming the frequency Fr F s 600 khz, select R t 2.7 kω, using Table.. Output ltage Prgramming Output vltage is prgrammed by reference vltage and external vltage divider. The Fb pin is the inverting input f the errr amplifier, which is internally referenced t 0.7. The divider is ratied t prvide 0.7 at the Fb pin when the utput is at its desired value. The utput vltage is defined by using the fllwing equatin: I Δ F in s 2 (.2 max).8 2 A 54m 600 khz IR84W Enable R + 8 R ref 9 in R R 2 R2 in (min) * EN.2... (5) R R R R EN in( min ) EN... (6) (7) when an external resistr divider is cnnected t the utput as shwn in figure. Equatin (7) can be rewritten as: R 9 8 ref R ref Fr the calculated values f R8 and R9 see feedback cmpensatin sectin. Fig.. Typical applicatin f the IR84W fr prgramming the utput vltage Sft-Start Prgramming The sft-start timing can be prgrammed by selecting the sft-start capacitance value. Frm (), fr a desired start-up time f the cnverter, the sft start capacitr can be calculated by using: C SS Where T start is the desired start-up time (ms). Fr a start-up time f.5ms, the sft-start capacitr will be 0.099μF. Chse a 0.μF ceramic capacitr. Btstrap Capacitr Selectin (8) T drive the Cntrl FET, it is necessary t supply a gate vltage at least 4 greater than the vltage at the SW pin, which is cnnected the surce f the Cntrl FET. This is achieved by using a btstrap cnfiguratin, which cmprises the internal btstrap dide and an external btstrap capacitr (C6), as shwn in Fig. 2.. The peratin f the circuit is as fllws: When the lwer MOSFET is turned n, the capacitr nde cnnected t SW is pulled dwn t grund. The capacitr charges twards cc thrugh the internal btstrap dide, which has a frward vltage drp D. The vltage c acrss the btstrap capacitr C6 is apprximately given as c IR84W IR624 cc Fb D OUT... (0) When the upper MOSFET turns n in the next cycle, the capacitr nde cnnected t SW rises t the bus vltage in. Hwever, if the value f C6 is apprpriately chsen, R8 R9 ( μf) T ( ms ) (9) start 8

19 the vltage c acrss C6 remains apprximately unchanged and the vltage at the Bt pin becmes Bt A btstrap capacitr f value 0.uF is suitable fr mst applicatins. Input Capacitr Selectin The ripple current generated during the n time f the upper MOSFET shuld be prvided by the input capacitr. The RMS value f this ripple is expressed by: I RMS cc D in I D ( D) (2) in + cc IR84W D... () () Where: D is the Duty Cycle I RMS is the RMS value f the input capacitr current. I is the utput current. Fr I 2A and D 0.5, the I RMS 0.7 A. Ceramic capacitrs are recmmended due t their peak current capabilities. They als feature lw ESR and ESL at higher frequency which enables better efficiency. Fr this applicatin, it is advisable t have x0uf 25 ceramic capacitr C26X5RE06M frm TDK. In additin t these, althugh nt mandatry, a X0uF, 25 SMD capacitr EE-FKEP may als be used as a bulk capacitr and is recmmended if the input pwer supply is nt lcated clse t the cnverter. IN C6 SW PGnd Bt + c - Fig. 2. Btstrap circuit t generate c vltage L Inductr Selectin The inductr is selected based n utput pwer, perating frequency and efficiency requirements. A lw inductr value causes large ripple current, resulting in the smaller size, faster respnse t a lad transient but pr efficiency and high utput nise. Generally, the selectin f the inductr value can be reduced t the desired maximum ripple current in the inductr ( Δi). The ptimum pint is usually fund between 20% and 50% ripple f the utput current. Fr the buck cnverter, the inductr value fr the desired perating ripple current can be determined using the fllwing relatin: in L Where: ( ) Δi L ; Δt D Δt Fs Δi * F in in Maximum input vltage Output ltage Δi Inductr ripple current F Switching frequency s in Δt Turn n time D Duty cycle... (4) If Δi 40%(I ), then the utput inductr is calculated t be.9μh. Select L. μh. The IHLP2525EZ-0.uH frm ishay prvides a cmpact, lw prfile inductr suitable fr this applicatin s. 9

20 Output Capacitr Selectin The vltage ripple and transient requirements determine the utput capacitrs type and values. The criteria is nrmally based n the value f the Effective Series Resistance (ESR). Hwever the actual capacitance value and the Equivalent Series Inductance (ESL) are ther cntributing cmpnents. These cmpnents can be described as Δ Δ Δ Δ ( ESL) Δ ( ESR) ( ESR) ( C) + Δ ΔI in ΔI 8 * C ( ESL) L L * ESR L * ESL * F + Δ s ( C)... (5) The utput LC filter intrduces a duble ple, 40dB/decade gain slpe abve its crner resnant frequency, and a ttal phase lag f 80 (see figure ). The resnant frequency f the LC filter is expressed as fllws: F Gain 0 db LC 2 π L C Figure shws gain and phase f the LC filter. Since we already have 80 phase shift frm the utput filter alne, the system runs the risk f being unstable. -40dB/decade (6) Phase 0 0 Δ Output vltage ripple ΔI L Inductr ripple current Since the utput capacitr has a majr rle in the verall perfrmance f the cnverter and determines the result f transient respnse, selectin f the capacitr is critical. The IR84W can perfrm well with all types f capacitrs. As a rule, the capacitr must have lw enugh ESR t meet utput ripple and lad transient requirements. The gal fr this design is t meet the vltage ripple requirement in the smallest pssible capacitr size. Therefre it is advisable t select ceramic capacitrs due t their lw ESR and ESL and small size. Tw f the Panasnic ECJ- 2FB0J226ML (22uF, 6., mohm) capacitrs is a gd chice. Feedback Cmpensatin The IR84W is a vltage mde cntrller. The cntrl lp is a single vltage feedback path including errr amplifier and errr cmparatr. T achieve fast transient respnse and accurate utput regulatin, a cmpensatin circuit is necessary. The gal f the cmpensatin netwrk is t prvide a clsed-lp transfer functin with the highest 0 db crssing frequency and adequate phase margin (greater than 45 ). F LC Frequency F Frequency LC Fig.. Gain and Phase f LC filter The IR84W uses a vltage-type errr amplifier with high-gain (0dB) and wide-bandwidth. The utput f the amplifier is available fr DC gain cntrl and AC phase cmpensatin. The errr amplifier can be cmpensated either in type II r type III cmpensatin. Lcal feedback with Type II cmpensatin is shwn in Fig. 4. This methd requires that the utput capacitr shuld have enugh ESR t satisfy stability requirements. In general the utput capacitr s ESR generates a zer typically at 5kHz t 50kHz which is essential fr an acceptable phase margin. The ESR zer f the utput capacitr is expressed as fllws: F ESR 2 π*esr*c... (7) 20

21 Z IN OUT R8 R C POLE C4 Z f Where: in Maximum Input ltage sc Oscillatr Ramp ltage F Crssver Frequency F ESR Zer Frequency f the Output Capacitr F LC Resnant Frequency f the Output Filter R 8 Feedback Resistr H(s) db Gain(dB) F Z R9 REF E/A The transfer functin ( e / ) is given by: F POLE The (s) indicates that the transfer functin varies as a functin f frequency. This cnfiguratin intrduces a gain and zer, expressed by: Fb Fig. 4. Type II cmpensatin netwrk and its asympttic gain plt ( ) H s e Zf + sr C H( s) Z sr C R R 8 Fz 2π * R * C...(8) First select the desired zer-crssver frequency (F ): ESR Use the fllwing equatin t calculate R: R IN (9) (20) ( /5~/0) Fs F > F and F * sc * F in * F * F ESR 2 LC * R (2) e Cmp Frequency T cancel ne f the LC filter ples, place the zer befre the LC filter resnant frequency ple: F 75% F z LC Fz 0. 75* 2π L * C (22) Use equatins (20), (2) and (22) t calculate C4. One mre capacitr is smetimes added in parallel with C4 and R. This intrduces ne mre ple which is mainly used t suppress the switching nise. The additinal ple is given by: F P 2π * R C * C 4 4 * C + C POLE POLE (2) The ple sets t ne half f the switching frequency which results in the capacitr C POLE : C POLE π*r *Fs C 4 π*r *F......(24) Fr a general slutin fr uncnditinal stability fr any type f utput capacitrs, and a wide range f ESR values, we shuld implement lcal feedback with a type III cmpensatin netwrk. The typically used cmpensatin netwrk fr vltage-mde cntrller is shwn in figure 5. Again, the transfer functin is given by: e By replacing Z in and Z f accrding t figure 5, the transfer functin can be expressed as: H( s) sr ( C 8 4 Zf H( s) Z ( + sr C 4 IN C + C ) + sr C s [ + sc ( R + R )] ) * C + C 0 ( + sr 0...(25) C ) 7 2

22 ZIN OUT C Cmpensatr Type F ESR vs F Output Capacitr C7 R0 R8 R C4 Zf Type II F LC <F ESR <F <F s /2 Electrlytic Tantalum R9 Fb E/A e Cmp Type III F LC <F <F ESR Tantalum Ceramic Fig.5. Type III Cmpensatin netwrk and its asympttic gain plt The cmpensatin netwrk has three ples and tw zers and they are expressed as fllws: F F F F F H(s) db P P2 P Z Z (26) 2π * R C4 * C 2π * R C4 + C 2π * R * C 2π * C Crss ver frequency is expressed as: Gain(dB) 0 F R * C7 * 7 * C 4 7 * ( R in sc (27) 2π * R (29) 8 + R 0 * 2π * L * C REF FZ FZ2 FP2 FP ) 2π * C * C 7 * R...(28) 8 Frequency...(0) () Based n the frequency f the zer generated by the utput capacitr and its ESR, relative t crssver frequency, the cmpensatin type can be different. The table belw shws the cmpensatin types and lcatin f the crssver frequency. The higher the crssver frequency, the ptentially faster the lad transient respnse. Hwever, the crssver frequency shuld be lw enugh t allw attenuatin f switching nise. Typically, the cntrl lp bandwidth r crssver frequency is selected such that The DC gain shuld be large enugh t prvide high DC-regulatin accuracy. The phase margin shuld be greater than 45 fr verall stability. Fr this design we have: in 2.8 sc.8 ref 0.7 L. uh C 2x22uF, ESRmOhm each It must be nted here that the value f the capacitance used in the cmpensatr design must be the small signal value. Fr instance, the small signal capacitance f the 22uF capacitr used in this design is 2uF at.8 DC bias and 600 khz frequency. It is this value that must be used fr all cmputatins related t the cmpensatin. The small signal value may be btained frm the manufacturer s datasheets, design tls r SPICE mdels. Alternatively, they may als be inferred frm measuring the pwer stage transfer functin f the cnverter and measuring the duble ple frequency F LC and using equatin (6) t cmpute the small signal C. These result t: F LC 7.88 khz F ESR 4.4 MHz F s /200 khz ( /5~/0) Fs F * Select crssver frequency: F 80 khz Since F LC <F <F s /2<F ESR, TypeIII is selected t place the ple and zers. 22

23 Detailed calculatin f cmpensatin TypeIII Desired Phase Margin F Z 2 F P 2 F F Select : F F P 0.5 * F sin Θ 4. + sin Θ khz + sin Θ 45.7 sin Θ khz Z 0. 5* F s Z 2 00 khz Θ khz and Prgramming the Current-Limit The Current-Limit threshld can be set by cnnecting a resistr (R OCSET ) frm the SW pin t the OCSet pin. The resistr can be calculated by using equatin (4). This resistr R OCSET must be placed clse t the IC. The R DS(n) has a psitive temperature cefficient and it shuld be cnsidered fr the wrst case peratin. I SET I L( critical ) R OCSet R I DS( n) OCSet (2) Select : C 2.2 nf Calculate 7 R, C and 2π * F * L * C * R C * 7 in sc C 4 : ;R 2.7 kω R I I R DS( n) SET I 24.5 mω * mΩ 2 A*.5 A (50% ver nminal utput current ) OCSet OCSet ( LIM) 59.07μA (at F.55 kω Select R s 600kHz) 7.54 kω Select : R 2.74 kω C4 ; C nf, Select : C4 8.2 nf 2π * FZ * R C ; C 9.62 pf, Select : C 80 pf 2π * F * R Calculate R 0 P R, R 2π * C * F R8 2π * C * F P 2 Z 2 8 ; and R R 60 - R ; R 5 kω, : Ω, Select : R 0 58 Ω Setting the Pwer Gd Threshld A windw cmparatr internally sets a lwer Pwer Gd threshld at 0.6 and an upper Pwer Gd threshld at 0.8. When the vltage at the FB pin is within the windw set by these threshlds, PGd is asserted. The PGd is an pen drain utput. Hence, it is necessary t use a pull up resistr R PG frm PGd pin t cc. The value f the pull-up resistr must be chsen such as t limit the current flwing int the PGd pin, when the utput vltage is nt in regulatin, t less than 5 ma. A typical value used is 0 kω. Select : R kω ref R9 - ref * R ; R kω Select : R.6 9 kω 2

24 Applicatin Diagram: Fig. 6. Applicatin circuit diagram fr a 2 t.8, 2 A Pint Of Lad Cnverter Suggested Bill f Materials fr the applicatin circuit: Part Reference Quantity alue Descriptin Manufacturer Part Number Cin 0uF SMD Elecrlytic, Fsize, 25, 20% Panasnic EE-FKEP 0uF 206, 25, X5R, 20% TDK C26X5RE06M C cc uf uf, 0, X5R,0805 Panasnic ECJ-2FBC05K L.uH.uH,8A,20%,6.5MMx7MM ishay/dale IHLP2525EZ-0.uH C 2 22uF 0805, 6., X5R, 20% Panasnic ECJ-2FB0J226M R 49.9k 49.9K,060,/0 W,% Rhm MCR0EZPFX4992 R2 7.5k 7.5K,060,/0W,% Rhm MCR0EZPFX750 R t 2.7k Thick Film, 060,/0W,% Rhm MCR0EZPFX272 R OCSet.54K 060,/0 W,% Rhm MCR0EZPFX54 R PG 0K 060,/0 W,% Rhm MCR0EZPFX002 C ss 0.uF 060, 25, X7R, 0% Panasnic - ECG ECJ-BE04K R 2.74k 060,/0W,% Rhm MCR0EZPFX274 C 80pF 50, 060, NP0, 5% Murata GRM885CH8JA0D C4 8200pF 060, 50, X7R, 0% Panasnic - ECG ECJ-BH822K R8 4.99k 060,/0W,% Rhm MCR0EZPFX499 R9.6k 060,/0W,% Rhm MCR0EZPFX6 R ,/0W,% Panasnic ERJ-EKF580 C7 2200pF 060, 50, X7R, 0% Panasnic - ECG ECJ-BH222K U IR84W SupIRBuck PQFN 5x6mm Internatinal Rectifier 24

25 TYPICAL OPERATING WAEFORMS in2.0, cc5,.8, I0-2A, Rm Temperature, N Air Flw PD Fig. 7. Start up at 2A Lad Ch : in, Ch 2 :, Ch : ss, Ch 4 :Enable Fig. 8. Start up at 2A Lad, Ch : in, Ch 2 :, Ch : ss, Ch 4 : PGd Fig. 9. Start up with.62 Pre Bias, 0A Lad, Ch 2 :, Ch : SS Fig. 20. Output ltage Ripple, 2A lad Ch 2 : Fig. 2. Inductr nde at 2A lad Ch 2 :LX Fig. 22. Shrt (Hiccup) Recvery Ch 2 :, Ch : SS 25

26 TYPICAL OPERATING WAEFORMS in2, cc5,.8, IA-2A, Rm Temperature, N Air Flw Fig. 2. Transient Respnse, A t 2A step 2.5A/μs Ch :, Ch 4 :I 26

27 TYPICAL OPERATING WAEFORMS in2, cc5,.8, I2A, Rm Temperature, N Air Flw Fig. 24. Bde Plt at 2A lad shws a bandwidth f 86kHz and phase margin f 56 degrees 27

28 Simultaneus Tracking at Pwer Up and Pwer Dwn in2,.8, I2A, Rm Temperature, N Air Flw. 4.99K R s IR84W IR624 Seq Fb OUT R8 4.99K.6K R s2 R9.6K Fig. 25: Simultaneus Tracking a. input at pwer-up and shut-dwn Ch2: ut Ch:SS Ch4: Seq 28

29 Layut Cnsideratins The layut is very imprtant when designing high frequency switching cnverters. Layut will affect nise pickup and can cause a gd design t perfrm with less than expected results. Make all the cnnectins fr the pwer cmpnents in the tp layer with wide, cpper filled areas r plygns. In general, it is desirable t make prper use f pwer planes and plygns fr pwer distributin and heat dissipatin. The inductr, utput capacitrs and the IR84W shuld be as clse t each ther as pssible. This helps t reduce the EMI radiated by the pwer traces due t the high switching currents thrugh them. Place the input capacitr directly at the in pin f IR84W. The feedback part f the system shuld be kept away frm the inductr and ther nise surces. The critical bypass cmpnents such as capacitrs fr cc shuld be clse t their respective pins. It is imprtant t place the feedback cmpnents including feedback resistrs and cmpensatin cmpnents clse t Fb and Cmp pins. The cnnectin between the OCSet resistr and the Sw pin shuld nt share any trace with the cnnectin between the btstrap capacitr and the Sw pin. Instead, it is recmmended t use a Kelvin in cnnectin f the trace PGnd frm the OCSet resistr and the trace frm the btstrap in capacitr at the Sw pin. PGnd In a multilayer PCB use ne layer as a pwer grund plane and have a cntrl circuit ut grund (analg grund), t which all signals are referenced. The gal is t lcalize the high AGnd current path t a separate lp that des nt interfere AGnd with the mre sensitive ut analg cntrl functin. These tw grunds must be cnnected tgether n the PC bard layut at a single pint. The Pwer QFN is a thermally enhanced package. Based n thermal perfrmance it is recmmended t use at least a 4-layers PCB. T effectively remve heat frm the device the expsed pad shuld be cnnected t the grund plane using vias. Figure 26 illustrates the implementatin f the layut guidelines utlined abve, n the IRDC84W 4 layer dembard. Cmpensatin parts shuld be placed as clse as pssible t the Cmp pin. in in PGnd PGnd Enugh cpper & minimum length grund path between Input and Output All bypass caps shuld be placed as clse as pssible t their cnnecting pins. Resistrs Rt and Rcset shuld be placed as clse as pssible t their pins. AGnd AGnd ut ut Fig. 26a. IRDC84W dembard layut cnsideratins Tp Layer 29

30 Feedback trace shuld be kept away frm nise surces PGnd Fig. 26b. IRDC84W dembard layut cnsideratins Bttm Layer Analg Grund plane Single pint cnnectin between AGND & PGND, shuld be clse t the SupIRBuck, kept away frm nise surces. Pwer in Grund Plane AGnd Fig. 26c. IRDC84W dembard layut cnsideratins Mid Layer Use separate traces fr cnnecting Bt cap and Rcset t the switch nde and with the minimum length traces. Avid big lps. Fig. 26d. IRDC84W dembard layut cnsideratins Mid Layer 2 0

31 PCB Metal and Cmpnents Placement Lead lands (the IC pins) width shuld be equal t nminal part lead width. The minimum lead t lead spacing shuld be 0.2mm t minimize shrting. Lead land length shuld be equal t maximum part lead length + 0. mm utbard extensin. The utbard extensin ensures a large and inspectable te fillet. Pad lands (the 4 big pads ther than the IC pins) length and width shuld be equal t maximum part pad length and width. Hwever, the minimum metal t metal spacing shuld be n less than 0.7mm fr 2 z. Cpper; n less than 0.mm fr z. Cpper and n less than 0.2mm fr z. Cpper.

32 Slder Resist It is recmmended that the lead lands are Nn Slder Mask Defined (NSMD). The slder resist shuld be pulled away frm the metal lead lands by a minimum f 0.025mm t ensure NSMD pads. The land pad shuld be Slder Mask Defined (SMD), with a minimum verlap f the slder resist nt the cpper f 0.05mm t accmmdate slder resist mis-alignment. Ensure that the slder resist in-between the lead lands and the pad land is 0.5mm due t the high aspect rati f the slder resist strip separating the lead lands frm the pad land. 2

33 Stencil Design PD The Stencil apertures fr the lead lands shuld be apprximately 80% f the area f the lead lads. Reducing the amunt f slder depsited will minimize the ccurrences f lead shrts. If t much slder is depsited n the center pad the part will flat and the lead lands will be pen. The maximum length and width f the land pad stencil aperture shuld be equal t the slder resist pening minus an annular 0.2mm pull back t decrease the incidence f shrting the center land t the lead lands when the part is pushed int the slder paste.

34 BOTTOM IEW IR WORLD HEADQUARTERS: 2 Kansas St., El Segund, Califrnia 90245, USA Tel: (0) TAC Fax: (0) This prduct has been designed and qualified fr the Industrial market (Nte5) isit us at fr sales cntact infrmatin Data and specificatins subject t change withut ntice. 08/2 4