10 A/4000 V ISOLATED INTEGRATED DRIVER MODULE

Transcription

1 IXYS Digital Pwer 10 A/4000 V ISOLATED INTEGRATED DRIVER MODULE IXIDM1401_O Datasheet Part Number Optins IXIDM1401_1505_O tw islated gate drivers with 10 A gate current, 15 V psitive and 5 V negative gate vltage, pen frame versin. IXIDM1401_1515_O tw islated gate drivers with 10 A gate current, 15 V psitive and -15 V negative gate vltage, pen frame versin. Abstract The IXIDM1401_O driver mdule cmbines supreme cmpactness with the highest perfrmance and reliability. It cmprises a dual-channel driver cre that targets medium pwer dual-channel IGBTs fr up t 4 kv and applicatins such as inverters, drives & autmatin, UPS, renewable energy, transprtatin, and medical. Its parallel capability allws fr an easy, high pwer system design. It supprts switching up t 250 khz, shrt-circuit prtectin, advanced active clamping, and supply-vltage mnitring. The IXIDM1401_O driver cre is equipped with the IX6610/6611 chipset f applicatin-specific integrated circuits that cvers the main range f functins required t design intelligent gate drivers. IXIDM1401_O is available in a 50x50x25 mm package. Figure 1. Tp and Bttm Views f IXIDM1401_O 2017 IXYS Crp. 1 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

2 Table f Cntents Part Number Optins... 1 Abstract... 1 Features... 3 Applicatins... 3 Descriptin... 3 Typical Applicatin Circuits... 4 Abslute Maximum Ratings... 6 Electrical Operating Characteristics... 7 Pin Cnfiguratin... 9 Pin Assignment... 9 Blck Diagram Basic Operatin Interface Pwer Blck Gate Driver Active Clamping Prtectin Over-Current Prtectin Secndary Side Under-/Over-vltage Prtectin Layut and Use Cnsideratins Typical Perfrmance Characteristics Ordering Infrmatin Package Drawing and Dimensins Marking IXYS Crp. 2 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

3 10 A/4000 V Islated Integrated Driver Mdule Features Tw islated gate drivers fr half bridge switching mdules Internal pwer supply fr islated drivers with up t 2 W utput pwer per channel Nn-verlap peratin f high side and lw side drivers TTL lgic level micrcntrller interface Single 15 V pwer supply peratin +15 V/-5 V islated gate driver utput vltage t drive IGBTs with up t 10 A pulse current Minimum input pulse width 500 ns Input t utput gate driver signal prpagatin delay 100 ns Gate drive pulse width distrtin 20 ns Under- and ver-vltage lckut prtectin Up t 50 ma 3.3 V lad capability utput t drive an external MCU FAULT signals Infrming MCU abut vervltage, under-vltage, and ver-current cnditins at islated gate drivers Latched FAULT signals frm gate drivers t let MCU read fault infrmatin asynchrnusly Operating ambient temperature: 40 0 C~ C Driver and internal pwer supply vertemperature prtectin with C threshld and 25 0 C hysteresis Envirnmentally friendly: EU RHS cmpliant, Pb-free Applicatins AC and DC mtr drives fr EV and industrial Inverters fr slar and wind pwer Cnverters fr medical, lighting, and transprt UPS, SMPD, and industrial battery chargers Paralleled peratin f IGBTs Inductin heating and tractin Designed fr phase-leg IGBT mdules Designed fr phase-leg SiC MOSFET mdules Up t 600 A/600 V Up t 600 A/900 V Up t 600 A/1200 V Up t 450 A/1700 V Descriptin A High Vltage Islated Mdule (IXIDM1401_O) is develped and ptimized fr electrnic mtr cntrl applicatins such as air cnditiners, washing machines, refrigeratrs, and high pwer buck cnverters r inverters. It is a cmpact, high perfrmance device in a single islated package with a very simple design. Based n the IX6610/11 chip set, this device enables a 3.3 V micrcntrller unit (MCU) t perate halfbridge-cnnected IGBTs thrugh a 4 kv islatin barrier prviding PWM pulses as shrt as 500 ns, and n lwer limit n switching frequency. Internal pwer supply prvides up t 2 W per channel f islated pwer t drive upper and lwer IGBTs, effectively islating the MCU frm high pwer circuitry. Operating frm a single plarity 15 V pwer surce, this device prvides +15 V/-5 V t perate IGBT gates and +3.3 V at 50 ma t pwer the MCU frm the same surce. Built-in under-vltage and ver-vltage prtectin prevents the IGBT frm perating at gate vltages utside the ptimal windw and infrms the MCU abut such cnditins irrespective f the surce f the prblem, which may be n either the lw r high side IGBT behind the islatin barrier r n the primary side befre the islatin barrier. Over-current prtectin with 300 mv threshld may utilize either the current sense resistr r IGBT desaturatin event. Over-current prtectin turns the IGBT ff immediately after the cllectr current exceeds the value set by the custmer, infrming the MCU abut every such event t make apprpriate decisins. An active clamping cmparatr with a 3 V threshld with respect t negative IGBTs gate vltage surce disables the driver in case the cllectr vltage exceeds the level set by the custmer, preventing frm excessive pwer dissipatin n IGBTs. Built-in dead time delay circuitry prevents turning n f bth IGBTs simultaneusly with channel A pririty. If channel B is active and channel A is frced int the ON state, channel B becmes disabled immediately and the channel A IGBT turns n with a delay time f ~0.4 µs. After channel A becmes inactive, channel B, if active, turns n with the same delay time. If 2017 IXYS Crp. 3 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

4 channel A is active and channel B is frced int the ON state, this cmmand will be ignred as lng as channel A remains active. If channel A becmes inactive befre the cmmand activating channel B expires, channel B becmes active with a delay time f ~400 ns after channel A becmes inactive. Over-temperature prtectin disables IGBTs if the temperature f any f the internal chips exceeds 150 C and resumes nrmal peratins when the temperature falls belw 125 C. If IGBT assembly is equipped with a temperature sensr, IXIDM1401_O is able t translate its signal t the MCU fr mnitring. The IXIDM1401_O device is available in a 50x50x27 mm package with a 12-pin 1 mm pitch FFC cnnectr t cmmunicate with the MCU, tw 5-pin 2.54 mm pitch headers t prvide signals t/frm IGBTs and ne 2-pin 2.54 mm pitch header t translate the signal frm the IGBT s assembly temperature sensr. Typical Applicatin Circuits Figure 2. Typical Applicatin Circuit with Half-bridge IGBT Mdule and De-saturatin Over-current Prtectin Figure 2 shws a standard cnnectin fr IXIDM1401_O with an MCU and a phase-leg IGBT mdule. 10 primaryside pins (ut f a ttal f 12 pins) are directly cnnected with the MCU. The secndary side has 5 pins fr each IGBT cnnectin IXYS Crp. 4 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

5 Figure 3. Typical Applicatin Circuit with Half-bridge IGBT Mdule and Over-current Prtectin Utilizing Current Sense Resistrs Figure 3 shws a standard cnnectin fr IXIDM1401_O with an MCU and a phase-leg IGBT mdule. 10 primaryside pins (ut f a ttal f 12 pins) are directly cnnected with the MCU. The secndary side has 5 pins fr each IGBT cnnectin. Figure 4. Typical Applicatin Circuit with Push-pull Cnverter and Active Clamping Prtectin 2017 IXYS Crp. 5 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

6 Figure 4 hws a standard cnnectin fr IXIDM1401_O with an MCU and a phase-leg IGBT mdule. 10 primaryside pins (ut f a ttal f 12 pins) are directly cnnected with the MCU. The secndary side has 5 pins fr each IGBT cnnectin. Abslute Maximum Ratings PARAMETER SYMBOL RATINGS UNITS Supply Vltage (+15 V) V SUPM 0.3 ~ +18 V MCU Supply Vltage (+3.3 V utput) V MCUM 0.3 ~ +6 V Lgic Pin Vltages (INA, INB, FLT_RESET, RESTART, MODE, V LG 0.3 ~ +6 V FAULT1, FAULT2) ACL pin Vltage 1) V ACL V EE 0.3 ~ V EE + 6 V ICM Pin Vltage 1) V ICM 0.3 ~+6 ) V GATE Pin Vltage 1) V G V EE 0.3 ~ +28 V Operating Temperature Range T OPR 40 ~ Strage Temperature Range T STG 55 ~ C 0 C Nte: 1) With respect t the COM Pin f the particular driver 2017 IXYS Crp. 6 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

7 Electrical Operating Characteristics Unless therwise specified, Ta = 25 0 C PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Nrmal Operating Pwer Supply Vltage Range V SUP V Under-vltage Lckut Threshld UVLO TR V Under-vltage Lckut Hysteresis UVLO HYS 0.5 V Over-vltage Lckut Threshld OVLO TR 16,5 17,25 18 V Over-vltage Lckut Hysteresis OVLO HYS 0.5 V V Pwer Supply Current I INA=V INB=V MODE = 0 V, V FLT_RST= V RESTART SUP 10 ma =V CLK=V FAULT1=V FAULT2 =V +3.3V=OPEN MCU Supply Vltage (+3.3 V utput) V MCU C OUT = 22 µf V MCU Supply Vltage Lad Regulatin V MCU_LR I MCU = 1 ma t 50 ma 50 mv MCU Supply Shrt Circuit Current 100 ma MCU Supply Bypass Capacitance ESR C OUT_ESR 0.3 Ω Lgic Inputs Leakage Current I INLKG V CLK=V RESTART=V INA=V INB=V MODE =0 V -1 1 µa Lgic Inputs Pull-dwn Resistance CLK, RESTART, INA, INB, MODE 25 kω Lgic Inputs Leakage Current I FLT_RESET V FLT_RESET = 0 r V FLT_RESET= 3.3 V -1 1 µa Lgic Inputs High Level V LGH CLK, RESTART, INA, INB, MODE, FLT_RESET 2.0 V Lgic Inputs Lw Level CLK, RESTART, INA, INB, MODE, FLT_RESET 0.8 V Lgic Inputs INA, INB Frequency F INA, F INB khz Lgic Inputs INA, INB Pulse Width 1) INA, INB 350 ns INA vs. INB Pulse Width Distrtin t DST 20 ns Lgic Inputs INA, INB Dead Time t DEAD 400 ns RESTART Pulse Width t RESET 200 ns FLT_RESET Pulse Width t FLT_RESET 200 ns External Clck F CLK Input Frm MCU khz External Clck Duty Cycle D CLK % External Clck Watchdg Timeut T DOG Infrmatin parameter nly 40 µs V FAULT1, FAULT2 Output High Vltage V FLTH I OUT = 10 ma MCU- V 0.20 FAULT1, FAULT2 Output Lw Vltage V FLTL I OUT = 10 ma 0.20 V ICM Cmparatr Threshld 2) V ICM_TR ICM Cmparatr Blanking Time 3) T ICM_BL µs ICM Cmparatr Respnse Time T ICM_R ns ICM Cmparatr Input Series Resistr R ICM kω ACL Cmparatr Threshld 4) V ACL_TR V ACL Cmparatr Respnse Time T ACL_R ns ACL Cmparatr t Driver Output Tri-state 5) Delay Time TACL_TR ns ACL Cmparatr Input Pull-dwn Resistance R ACL 1 kω IGBT Driver Output Vltage High Level V GH 15 V Lw Level V GL -5 V IGBT Driver Output Peak Sink/Surce Current I G ±10 A IGBT Driver Prpagatin Delay 6) T DPR 200 ns IGBT Driver Prpagatin Delay Time Mismatch 6) T DPR 20 ns Islatin Vltage Between Grund Pin and COM A Pin V IS_GCA 4 kv Islatin Vltage Between Grund Pin and COM B Pin V IS_GCB 4 kv Islatin Vltage Between COM A Pin and COM B Pin V IS_CACB 4 kv 2017 IXYS Crp. 7 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

8 Ntes: 1. INA signal verrides INB and INB is reduced by t INDEAD when INA verlaps INB 2. With respect t the COM pin 3. Time frm IGBT driver turn-n t turn-ff measured with ICM terminal set at 500 mv with respect t the COM pin 4. With respect t the VEE pin f the apprpriate driver 5. Delay time is measured frm the ACL terminal input verdriven abve the threshld t the IGBT driver utput respnse. The driver s utput tied t the COM pin by 50 hm resistr. 6. Measured as delay time between INA and INB activated/deactivated t respective respnse by the IGBT driver IXYS Crp. 8 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

9 Pin Cnfiguratin (Bttm View; Nt t Scale) Pin Assignment CONNECTOR PIN NUMBER PIN NAME FUNCTIONS V Supply vltage. Cnnect psitive terminal f the +15 V supply surce V Output vltage t drive external MCU. It can be disabled by MODE pin set at lgic high level, if MCU is pwered frm ther than mdule surce. In this case, the same external surce shuld be used t drive IXIDM1401_O internal lgic. 3 MODE MODE = 0 V r left pen activates internal +3.3 V vltage surce. MODE pin set abve +2.5 V disables internal surce and an external surce cnnected t +3.3 V pin will be used t perate internal lgic 1). 4 FLT_RESET Psitive lgic pulse at this pin resets flip-flps hlding infrmatin abut FAULT1 and FAULT2 cnditins 5 RESTART Psitive lgic pulse at this input restarts mdule J1 Lgic input t prvide external clck in case synchrnizatin between internal pwer supplies 6 CLK f different mdules required. If n external clck is applied, internal clck will be used 7 FAULT1 FAULT1 signal lgic utput 8 FAULT2 FAULT1 signal lgic utput J2 J3 J4 9 GROUND Grund terminal fr all pwer supplies and lgic signals 10 INB Channel B gate driver lgic input. If INB =1 and INA is active, cmplimentary pulses will be generated at GATE B utput with a dead time ~400 ns. 11 INA Channel A gate driver lgic input 12 TS Terminal t translate therm sensr infrmatin frm IGBT mdule t MCU. It is a direct cnnect t pin #1 f the cnnectr J4 1 GATE A Gate driver A utput. Cnnect t the gate f the IGBT A 2 COM Cmmn terminal f the Gate driver A, Cnnect t IGBT A emitter r lw ptential terminal f the current sense resistr 3 ICM Over-current cmparatr s input. Cnnect t the high ptential terminal f the current sense resistr/igbt emitter. Cnnect t COM pin if unused 4 ACL Active clamping cmparatr s input. See typical applicatin circuit (Fig. 2) fr cnnectin schematic. Cnnect t VEE pin if unused 5 VEE Output f the negative pwer supply fr the gate driver A 1 GATE B Gate driver A utput. Cnnect t the gate f the IGBT B 2 COM Cmmn terminal f the Gate driver B, Cnnect t IGBT B emitter r lw ptential terminal f the current sense resistr 3 ICM Over-current cmparatr s input. Cnnect t the high ptential terminal f the current sense resistr/igbt emitter. Cnnect t COM pin if unused 4 ACL Active clamping cmparatr s input. See typical applicatin circuit (Fig. 2) fr cnnectin schematic. Cnnect t VEE pin if unused 5 VEE Output f the negative pwer supply fr the gate driver B 1 TS Terminal t translate therm sensr infrmatin frm IGBT mdule t MCU. Direct cnnect t pin #12 f the cnnectr J1 2 GND Grund terminal fr therm sensr cnnectin 2017 IXYS Crp. 9 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

10 Nte: 1) If external +3.3 V supply is used t drive internal IX6610 lgic, the pwer-up sequence shuld be implemented. Internal +3.3 V pwer supply shuld be active befre the MODE pin is used t disable it, and nly after that shuld the external vltage be applied t the +3.3 V pin. Pwer dwn sequence requires external +3.3 V remved first, after which the MODE pin shuld be set t lgic zer r left pen. The +15 V surce can be then be remved frm IXIDM1401_O. Blck Diagram Figure 5. IXIDM1401_O Blck Diagram Basic Operatin The IXIDM1401_O device is based n the IX6610/IX6611 chipset, which enables the creatin f an islated IGBT driver with a high vltage islatin barrier between the primary and secndary side and between secndary side drivers. This creates a very flexible architecture, which can be used fr 3-phase mtr driver, half-bridge switches, push-pull cnverters, r ther applicatins which require islatin between the primary and secndary side and/r between secndary side drivers. This device cntains the necessary circuit blcks t perate a bidirectinal interface between the primary and secndary side and prvide the pwer required t drive islated gate drivers and the MCU frm a single +15 V pwer surce, maintaining up t 4 kv islatin between the MCU and gate drivers and als between gate drivers. The IXIDM1401_O mdule implements mnitring/prtectin functins such as +15 V supply under-/ver-vltage lckut, under-/ver-vltage lckut n secndary side, and thermal shutdwn. It als prvides ver-current prtectin n the secndary side and sends infrmatin t the MCU abut such events t allw the MCU t make apprpriate decisins. The IX6610 is lcated n the primary side and implements a dual-channel bidirectinal transfrmer interface, which transmits the primary side input cmmands frm the MCU t the secndary side, and infrmatin frm the secndary side t the MCU. Asynchrnus data transmissin is implemented by narrw pulses t prevent the 2017 IXYS Crp. 10 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

11 transfrmer s cre saturatin. The IX6610 als cntains all the blcks required t implement a pwer cnverter that supplies islated pwer t the secndary side IGBT drivers. The IX6610 utilizes built-in inter-lck and dead time cntrl. Interface TTL level cmpatible input signals INA and INB frm an external MCU are used t perate secndary side drivers. These input signals are fed thrugh the Schmitt trigger buffers t imprve nise immunity. An input signal interlck functin is implemented t prevent the simultaneus cnductin f the secndary side IGBTs, with pririty fr the INA signal. If the INA signal is active (lgic ne), the INB signal is ignred irrespective f its lgic state until the INA signal becmes lgic zer and dead time expires. This feature enables the generatin f cmplimentary signals at Gate A and Gate B utputs using nly ne signal surce applied t INA input, while INB input is set t lgic high. Dead time between pulses at Gate A and Gate B utputs is hardware prgrammed t ~420 ns. A narrw pulse detectr is implemented in the IX6610 t prevent transmissin f very narrw false PWM input signals t the drivers due t nise cupling at the input pins. Input signal pulses with width narrwer than 100 ns are suppressed and pulses with width greater than 350 ns are transferred t the drivers. In the half bridge driver cnfiguratin, dead time shuld be added t the incming input signals, t prevent sht thrugh current due t verlap f the cnducting state fr high and lw side IGBTs. If the dead time required t perate a particular IGBT is mre than that implemented in IXIDM1401_O, it shuld be prgrammed by the MCU. IX6610 als cntains a dead time circuit that adds dead time t the input signals INA and INB after the input signal interlck functin. This dead time is used as a precautin nly in the instance f a sftware failure and it applies if the dead time prgrammed by the MCU is shrter than the dead time set by IXIDM1401_O. T avid limitatins t a transmitted maximum pulse width, IX6610 nly transmits shrt pulses representing rising/falling edges f the INA (INB) signal, while IX6611 restres riginal INA (INB) pulse width n the secndary side (see Figure 6). Legend: Figure 6. PWM Signal Transmissin Channel 1 (blue) input signal (INA/INB) frm MCU Channel 2 (magenta) and Channel 3 (green) IX6610 utputs Channel 4 (red) IGBT gate pulse at IX6611 utput 2017 IXYS Crp. 11 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

12 The secndary side pwer supply faults and IGBT pwer stage faults are transmitted back t the IX6610 (primary side) thrugh a pulse transfrmer. IX6610 has fur single-ended receiver cmparatrs, which sense the presence f signals that are mre psitive than a fixed psitive threshld value. Receiver cmparatrs are high speed Schmitt Trigger buffers with 1 V typical hysteresis. The truth table fr FAULT signals is listed in Table 1. Table 1. Fault Signals Truth Table Befre FAULT RESET After FAULT RESET FAULT1 FAULT2 Synchrnized FAULT1 FAULT2 SOURCE SIGNAL 1 0 n 1 0 IX6610 Under-vltage 0 1 n 0 1 IX6610 Over-vltage 1 1 n 1 1 IX6610 Over-temperature 1 0 yes 0 0 IX6611 Under-vltage 0 1 yes 0 0 IX6611 Over-vltage 0 1 n 0 0 IX6611 Over-current Fault signals generated by IX6610 are nt synchrnized with INA (INB) signals and cannt be reset by the MCU applying the FAULT RESET signal. They will remain active s lng as the fault cnditin exists. Hwever, when the fault cnditin disappears, the FAULT flag will remain active as lng as the MCU des nt reset it. Fault signals generated by IX6611 representing ver-vltage and under-vltage cnditins are synchrnized with INA (INB) signals and are an ech f these signals, which appear at FAULT utputs immediately after an attempt t transmit the INA (INB) signal when a fault cnditin n the secndary side exists. Fault flags representing these faults can be reset by the MCU, but will appear again at the next attempt t transmit the INA (INB) signal until the fault cnditin disappears. This allws the MCU t determine the surce f the fault signals. The fault signal frm IX6611 representing an ver-current cnditin is nt synchrnized with the INA (INB) signal; hwever, the fault flag representing this cnditin can be reset by the MCU. It will be activated again if the ver-current fault ccurs at the next PWM cycle. All fault cnditins fr IX6610 stp executin f the PWM cycle at bth drivers. All fault cnditins fr IX6611 stp the PWM cycle at the affected driver nly. Therefre, it is up t the MCU prgrammer t determine the next steps if a fault cnditin ccurs. If fault cnditins appear befre the start f the PWM cycle, the PWM cycle will be ignred fr the duratin that fault cnditins exist. Pwer Blck The IXIDM1401_O pwer blck is designed t prvide up t 2 W f pwer t drive tw IX6611 islated gate drivers and an external MCU frm a single +15 V supply. IX6610 utilizes push-pull cnverter tplgy, which allws multiple islated utputs, step-up/step-dwn and/r inverted utputs with lw utput ripple. The circuit drives tw internal high current switches cnnected t an external center-tapped transfrmer prviding dual islated secndary side psitive and negative vltages fr the IGBT drivers and an islated 5 V supply t IX6610. The pwer cnverter has a start-up mde and a run mde. In the start-up mde, the cnverter perates frm the internal scillatr and activates nly a prtin f the pwer switches t reduce the dynamic current cnsumptin/pwer dissipatin. After start-up, the cnverter activates the pwer switches and ges int run mde. The run mde is held ff ~1.28 ms. The transmit peratin is als disabled during start-up mde t minimize current draw in the secndary. After run mde begins, it cntinues until a restart ccurs, which returns the pwer cnverter t start-up mde. In the run mde, the pwer cnverter perates either frm an internal r external MCU clck, if it exists. An external clck may be used t minimize nise interference between IXIDM1401_O devices in case f multiphase applicatins such as mtr drivers IXYS Crp. 12 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

13 The push-pull blck repeats the duty cycle f the external clck that allws slight adjustment f secndary utput vltage in case f ver/under-vltage by varying the duty cycle. It is nt recmmended t use an external clck with DC EXT greater than 0.5. T prevent excessive pwer dissipatin and ptential failure f the IC due t fault clck, a watchdg timer is included. Whenever the external clck perid exceeds the watchdg timeut (40 µs), the cnverter switches t the internal clck. IX6610 cntains an internal LDO regulatr with 3.3 V utput vltage t drive the MCU. The maximum lad current at 50 ma fr 100 ms allws fr easy MCU initializatin. If an external 3.3 V surce is used t drive the MCU, the internal LDO regulatr shuld be disabled by applying lgic level t the MODE pin t prevent cmpetitin between regulatrs; hwever, an external 3.3 V shuld be used in this case t drive IX6610 internal lgic circuitry. The Mde pin has an internal pull-dwn resistr and can be left pen with internal LDO active. A lgic high level at the RESTART pin disables the pwer cnverter, the LDO, initiates the pwer cnverter start-up sequence, and resets the fault flags. Hlding RESTART lw fr sufficient time will lwer the LDO vltage t a level that may initiate a POR sequence in the MCU. The RESTART pin has an internal 20 kω pull dwn resistr. Gate Driver The IX6611 used n the IXIDM1401_O secndary side is designed t prvide gate drive fr high pwer IGBTs, cnverting the incming PWM lgic signals int a +15 V/-5 V (with respect t COMMON) biplar gate drive signal with a typical 10 A peak drive current capability. Separate psitive and negative gate driver utputs allw ptimizing f IGBT turn n/ff time withut an external dide by selecting serial gate resistrs f different values (See Blck Diagram, resistrs R1 and R2). The internal dead time circuit eliminates the crss cnductin f the surce and sink utputs. Active Clamping Prtectin Active clamping prtectin prevents IGBT damage if the inductive lad is turned ff with high inductive current. In such instances, the IGBT cllectr vltage may easily exceed the breakdwn limit and destry the IGBT. One f the ways t prevent this cnditin is t keep the IGBT cnducting until the energy stred in the inductr is nt enugh t create cllectr ver-vltage cnditin. The IX6611 utilizes an ACL cmparatr with a 3 V threshld with respect t negative vltage surce that may be used fr implementing an advanced active clamping technique, as shwn in applicatin circuit diagram (Figure 3). The ACL cmparatr mnitrs vltage at resistive divider R1/R2, which is cnnected t the IGBT cllectr thrugh clamp dides Z1, Z2. If the IGBT cllectr vltage exceeds a threshld equal t V Z1 + V Z2 + V Z3 with respect t V EE when the IGBT gate is set LOW, the current starts flwing int the OUTN gate driver utput creating a vltage drp acrss ZD3. The resistive divider shuld be chsen in such a way that the vltage drp acrss R2 exceeds the ACL cmparatr threshld, i.e. V ZD3 *R2 / (R1 + R2) > 3.0 V. Triggering the ACL cmparatr frces the gate driver utput t a tri-state cnditin and the IGBT starts t turn n due t the breakdwn dide current charging the IGBT gate. Once the IGBT turns n, its cllectr vltage falls, the dide recvers frm breakdwn, and the ACL cmparatr turns n the OUTN utput, which frces the IGBT gate lw. This sequence may repeat several times until the energy in the external inductance is dissipated. The ACL cmparatr is active nly when the driver s utput OUTP is OFF. Dide D1 prtects gate driver OUTP utput frm draining current int the cllectr when it becmes less psitive than V CC. Over-Current Prtectin IX6611 cntains an Over Current Cmparatr (OC COMP) with a 300 mv threshld with respect t the COMMON pin. IGBT ver-current prtectin can be implemented either by using a lw value current sense resistr, an IGBT with a secndary current sense utput, r utilizing a de-saturatin event (See Figures 1 and 2) IXYS Crp. 13 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

14 If an IGBT ver current fault ccurs, the IGBT driver utput is frced lw fr the remainder f the cycle. Nrmal peratin resumes at the beginning f the next PWM gate drive cycle. Hwever, prematurely turning the IGBT ff may prvke an ver-vltage cnditin at the IGBT cllectr. In this case, the ACL cmparatr shuld be used t prevent IGBT damage. A nise filter at the current sense input may be required due t lw sense vltage. The IXIDM1401_O ICM input has an internal 100 pf capacitr cnnected in parallel t the ICM; therefre, nly a serial resistr can be added t create such a filter. An IGBT ver-current fault event can ccur any time during the ON time f the gate drive signal. When an vercurrent event ccurs, the Output Faults Pulse Generatr creates a narrw 200 ns pulse that is used by the Fault Cntrl Lgic t cmmunicate the fault cnditin t the MCU. The OC cmparatr s input is grunded during the ff time f the IGBT and remains grunded fr 3.5 µs immediately after the IGBT turns n t prevent false tripping. Traditinal de-saturatin prtectin can als be implemented using a large rati resistive divider acrss the cllectr t emitter (See Figure 1). Resistive divider R1/R2 has tw limitatins regarding its value. Vltage drp acrss R2 shuld be abve 300 mv t trigger the ICM cmparatr in case f the IGBT de-saturatin event and it shuld nt exceed V CC vltage, when IGBT is in OFF state. If it is physically impssible, a Zener dide shuld be used t prevent ICM cmparatr damage as shwn in Figure 1, Z1. Secndary Side Under-/Over-vltage Prtectin IX6611 cntains Under- and Over-vltage Lckut Cmparatrs (UVLO and OVLO respectively) that mnitr the psitive pwer supply terminal. If, at the beginning f the PWM pulse, psitive pwer supply vltage is belw the UVLO threshld r abve the OVLO threshld, the gate driver utput is driven lw and it skips that PWM pulse. Hwever, if UVLO r OVLO cnditins ccur after PWM pulse start, these cnditins are ignred until the next PWM pulse. If the psitive pwer supply recvers frm the fault cnditin, nrmal peratin resumes n the next PWM pulse. Fault infrmatin is cmmunicated t the MCU as narrw pulses. Based n the type f fault, the fault cntrl lgic selects narrw pulses either frm the input interface r frm the utput fault pulse generatr. A UVLO fault cnditin is cmmunicated t the MCU as a FLT1 pulse that is an input interface pulse representing the leading edge f the PWM pulse delayed by IX6611 prpagatin delay time. The OVLO fault cnditin is cmmunicated t the MCU as a FLT2 pulse that is an input interface pulse representing the trailing edge f the PWM pulse, als delayed by IX6611 prpagatin delay time. The IGBT ver-current cnditin is cmmunicated t the MCU as a FLT2 pulse frm the internal utput fault pulse generatr, which is synchrnized with an ver-current event, but nt leading/trailing edges f the input PWM signal. Layut and Use Cnsideratins Place external cmpnents as clse t the package as pssible and use thick, shrt cnnecting traces t reduce the circuit impedance. Pay special attentin t the separatin f islated circuits t implement creepage distance limits fr high vltage applicatins. Switching nise, which ccurs frm the GND, may cause instability; therefre, psitin blcking capacitrs at the +15 V surce as clse t IXIDM1401_O as pssible. The abslute maximum ratings f the mdule and external cmpnents shuld nt be exceeded. The thermal sensr s inputs are nt islated frm the primary side and its grund terminal is a direct cnnectin t the IXIDM1401_O grund terminal. T prevent ESD damage t the mdule, install a 220 pf 470 pf ceramic capacitr with breakdwn vltage abve the islatin barrier vltage between the primary and secndary side grund terminals IXYS Crp. 14 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

15 Typical Perfrmance Characteristics Figure 7 (a). Channel A Prpagatin Delay Time Rising Edge Figure 7 (b). Channel A Prpagatin Delay Time Falling Edge Red INA signal, Green Gate A signal Red INA signal, Green Gate A signal Figure 8 (a). Channel B Prpagatin Delay Time Rising Edge Figure 8 (b). Channel B Prpagatin Delay Time Falling Edge Red INB signal, Magenta Gate B signal Red INB signal, Magenta Gate B signal Figure 9 (a). Cmplementary Signal at Channel B with Bth Channels Active Figure 9 (b). Cmplementary Signal Dead Time Channel A t Channel B Red INA signal, Green Gate A signal, Magenta Gate B signal Red INA signal, Green Gate A signal, Magenta Gate B signal 2017 IXYS Crp. 15 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

16 Typical Perfrmance Characteristics (Cntinued) Figure 10. Cmplementary Signal Dead Time Channel B t Channel A Figure V Supply Pwer Capability fsw = 100 khz, DC = 50%, INB = HIGH Red INA signal, Green Gate A signal, Magenta Gate B signal Figure 12. Gate Lgic 1 Vltage vs. Switching Frequency DC = 50%, CGS = 10 nf Figure 13. Gate Lgic 0 Vltage vs. Switching Frequency DC = 50%, CGS = 10 nf Figure 14. Gate Lgic 1 Vltage vs. Pwer Supply Vltage fsw = 1 khz DC = 50%, CGS = 10 nf Figure 15. Gate Lgic 0 Vltage vs. Pwer Supply Vltage fsw = 1 khz DC = 50%, CGS = 10 nf 2017 IXYS Crp. 16 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

17 Ordering Infrmatin IXIDM1234_5678_9 DESIGNATOR DESCRIPTION SYMBOL DESCRIPTION 1 Mdule Cnfiguratin 1 Tw Islated Gate Drivers 23 Islatin Vltage kv 4 Gate Current 1 10 A 56 Psitive Gate Vltage V 78 Negative Gate Vltage 05 5 V 78 Negative Gate Vltage V 9 Package Infrmatin O Open Frame; M Mlded Package Drawing and Dimensins Units: mm Tp View Bttm View 2017 IXYS Crp. 17 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

18 Side View Recmmended Ftprint (Cmpnent Side View) Marking XX - Represents prductin lt number YY Represents prductin year WW Represents wrk week 2017 IXYS Crp. 18 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice

19 Warranty and Use IXYS CORP. MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIR D PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. IXYS Crp. prducts are nt designed, intended, r authrized fr use as cmpnents in systems intended fr surgical implant int the bdy, r ther applicatins intended t supprt r sustain life, r fr any ther applicatin in which the failure f the IXYS Crp. prduct culd create a situatin where persnal injury r death may ccur. IXYS Crp. reserves the right t make changes t r discntinue any prduct r service described herein withut ntice. Prducts with data sheets labeled "Advance Infrmatin" r "Preliminary" and ther prducts described herein may nt be in prductin r ffered fr sale. IXYS Crp. advises custmers t btain the current versin f the relevant prduct infrmatin befre placing rders. Circuit diagrams illustrate typical semicnductr applicatins and may nt be cmplete. IXYS Crp Buckeye Dr. Milpitas, CA Phne: Dcument N: IXIDM1401_O_DS Fax: Revisin: 02 Issue date: 9/12/ IXYS Crp. 19 IXIDM1401_O_DS, Rev. N. 02 Characteristics subject t change withut ntice