SFDQDB4239F. Specifications and Applications Information. orce LED Driver. Mass: 34 grams typ. 09/25/12. Package Configuration
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1 09/25/12 Specificatins and Applicatins nfrmatin Smart Fr rce LED Driver The ERG Smart Frce Series f LED Drivers are specifically designed fr applicatins which require wide dimmg and LCD brightness stability ver a wide put vltage range. The is designed t prvide backlight pwer fr the Samsung LTM270HT03 display. Designed, manufactured and supprted with the USA, the SFDQD features: Wide put vltage range Cnstant LED current External dimmg r n-bard dimmg High dimmg rati Sft start One year warranty Cnnectr Mlex J1-1,2,3 V(+) J1-4,5,6 V(+) J1-7,8,9 J1-10,11,12 J1-13 N/C J1-14 J1-15 Cntrl Cnnectrs Output Cnnectr * Mlex J2-1 Cathde 1 J2-2 Cathde 2 J2-3 Ande A J2-4 Ande A J2-5 Cathde 3 J2-6 Cathde [126,75].150 [3,81] Package Cnfiguratin Output [31,75] [39.12].125 [3,18] Dia. (2x) [71,12] [45,72] PCB cmpnents are shwn fr reference nly. Actual prduct may differ frm that shwn. * Requires harness: ERG part number H F recmmended Mass: 34 grams typ. page 1 f 5.
2 Abslute Maximum Ratgs Ratg Symbl Value Units Vltage Strage Range Temperature V -0.3 t T -40 t +85 C stg Vltage Cntrl Vltage Operatg Characteristics V V PWM 0 t V 0 t +5.0 Unless therwise nted V = Vlts dc and Ta = 25 C. Characteristic Symbl M Typ Max Units Vltage V Cmpnent Surface ( Nte 1) T C Temperature s Peak nrush Current (Nte 2) peak Adc Current LED Strg Vltage V ED Efficiency Adc L ( Nte 3) h % Output Current (per strg) P (Nte 4) ut madc Turn-n Threshld V thn Turn-ff Threshld V thff mpedance Cntrl P (Ntes 6,7) (Nte 5) R kohms Full-n Threshld V thn Full-ff Threshld V thff Cntrl Bias Current Cbias ua Frequency F PWM Specificatins subject t change withut ntice Hz Nte 1 Surface temperature must nt exceed 80 C. Nte 2 Peak rush ccurs ver a 1 t 3 ms time perid durg itial startup. Nte 3 Efficiency is calculated usg a 51.3V LED strg. Nte 4 p is ternally pulled up abve the turn-n threshld Nte 5 p put impedance is 10kΩ t 12V. Nte 6 Cntrl p is ternally pulled t. Nte 7 Cntrl p put impedance is 485kΩ. page 2 f 5.
3 Applicatin nfrmatin The ERG has been designed t be cnfigured multiple ways: NO DMMNG OPERATON: The SFDQ can be cnfigured t perate withut dimmg by flatg the Cntrl (J1-15) p and (J1-14) p. Ps 1 thrugh 6 f cnnectr J1 must be cnnected t +V, between 10.8 and 18. Ps 7 thrugh 12 f cnnectr J1 must be cnnected t. ONBOARD PWM DMMNG OPERATON: Onbard PWM cnfiguratin as shwn Figure 1 allws the user t cntrl display brightness by cntrllg the nbard PWM generatr. The user is respnsible t prvide an analg cntrl signal. DMMNG: Dimmg is accmplished by applyg an analg vltage t the Cntrl P (J1-15). Display brightness is mdulated by cntrllg the Cntrl P vltage as shwn Graph 1. ENABLE/DSABLE: The driver may be enabled r disabled (turned n and ff) by applyg a DC vltage t the P(J1-14). P n and ff levels are specified the Operatg Characteristics sectin f the data sheet. P is ternally pulled up abve the turn-n threshld. Ps 1 thrugh 6 f cnnectr J1 must be cnnected t +V, between 10.8 and 18. Ps 7 thrugh 12 f cnnectr J1 must be cnnected t. EXTERNAL PWM DMMNG OPERATON: External PWM cnfiguratin as shwn Figure 2 allws the user t cntrl display brightness with an externally generated PWM signal. The user is respnsible t prvide the PWM signal. DMMNG: Dimmg is accmplished by applyg a PWM signal t the P (J1-14). n and ff levels are specified the Operatg Characteristics sectin f the data sheet. Display brightness is mdulated by cntrllg the PWM duty cycle as shwn Graph 2. Ps 1 thrugh 6 f cnnectr J1 must be cnnected t +V, between 10.8 and 18. Ps 7 thrugh 12 f cnnectr J1 must be cnnected t. page 3 f 5.
4 ONBOARD PWM DMMNG Graph 1 J1 J2 +12V V Ande A Optinal Ptentimeter V Cathde 1 Analg Dimmg Vltage (0 t 5V) 15 Cntrl Cathde 2 Cathde 3 Cathde 4 +On -Off 14 Figure 1 page 4 f 5.
5 EXTERNAL PWM DMMNG (1) Nnlear relatinship frm 0 t 2% duty cycle. Graph 2 (1) J1 J2 +12V V Ande A Cathde 1 15 Cntrl Cathde 2 Cathde 3 5V 0V Duty Cycle 0% - 100% 14 Cathde 4 Figure 2 REG UL Endictt Research Grup, SO 9001 RM STERED F A3313 nc. Endictt Research Grup, nc. (ERG) reserves the right t make changes circuit design and/r specificatins at any time withut ntice. Accrdgly, the reader is cautined t verify that data sheets are current befre placg rders. nfrmatin furnished by ERG is believed t be accurate and reliable. Hwever, n respnsibility is assumed by ERG fr its use. page 5 f 5.
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