CM1623. EMI Filter with ESD Protection for SIM Card Applications

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1 EMI Filter with ESD Prtectin fr SIM Card Applicatins Features 4 Channel EMI Filtering with Integrated ESD Prtectin Pi Style EMI Filters in a Capacitr Resistr Capacitr (C R C) Netwrk kv ESD Prtectin n Each Channel (IEC Level 4, Cntact Discharge) 8 Lead UDFN Package with 0.40 mm Pitch Tiny UDFN Package Size:.7 mm x.35 mm x 0.5 mm Increased Rbustness Against Vertical Impacts During Manufacturing Prcess These Devices are Pb Free and are RHS Cmpliant MARKING DIAGRAM UDFN8 DE SUFFIX CASE 57BC P23 M 8 P23 = CM623 04DE M = Date Cde = Pb Free Package (Nte: Micrdt may be in either lcatin) ORDERING INFORMATION Device Package Shipping CM623 04DE UDFN 8 (Pb Free) 3000/Tape & Reel VCC (4,5) ELECTRICAL SCHEMATIC Fr infrmatin n tape and reel specificatins, including part rientatin and tape sizes, please refer t ur Tape and Reel Packaging Specificatin Brchure, BRD80/D. RST IN () CLK IN (2) Data IN (3) RST OUT (8) CLK OUT (7) Data OUT (6) *See Package/Pinut Diagrams fr expanded pin infrmatin. Semicnductr Cmpnents Industries, LLC, 20 April, 20 Rev. 3 Publicatin Order Number: CM623/D

2 Table. PIN DESCRIPTIONS 8 Lead UDFN Package Pin Name Descriptin RST Filter + ESD Channel 2 CLK Filter + ESD Channel 2 3 DATA Filter + ESD Channel 3 4 VCC V External PAD Device Grund 8 RST Filter + ESD Channel 7 CLK Filter + ESD Channel 2 6 DATA Filter + ESD Channel 3 5 VCC V External Pin Marking PACKAGE / PINOUT DIAGRAMS Tp View (Pins Dwn View) P CM623 04DE 8 Lead UDFN Package Bttm View (Pins Up View) PAD SPECIFICATIONS Table 2. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units Strage Temperature Range 65 t +50 C DC Pwer per Resistr 00 mw DC Package Pwer Rating 500 mw Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings nly. Functinal peratin abve the Recmmended Operating Cnditins is nt implied. Extended expsure t stresses abve the Recmmended Operating Cnditins may affect device reliability. Table 3. STANDARD OPERATING CONDITIONS Parameter Rating Units Operating Temperature Range 40 t +85 C Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Nte ) Symbl Parameter Cnditins Min Typ Max Units R Reset Channel Resistance R2 Clck Channel Resistance R3 Data Channel Resistance C Capacitance n Pins, 2, and 3 At MHz, V IN = 0 V pf C 2 Capacitance n Pins 4 and 5 At MHz, V IN = 0 V 8 pf I LEAK Dide Leakage Current (Reverse Bias) V DIODE = 3.3 V 0..0 A V SIG Signal Clamp Vltage a) Psitive Clamp b) Negative Clamp I LOAD = 0 ma I LOAD = 0 ma V V ESD ESD Peak Discharge Vltage Prtectin n All Pins In system ESD Withstand Vltage: a) Cntact Discharge per IEC Level 4 b) Air Discharge per IEC Level 4 T A = 25 C (Nte 2) kv. All parameters specified at T A = 25 C unless therwise nted. 2. Standard IEC with C Discharge = 50 pf, R Discharge =

3 PERFORMANCE INFORMATION Typical Filter Perfrmance (T A = 25 C, DC Bias = 0 V, 50 Envirnment) Figure. Insertin Lss vs. Frequency, Filter (Pins and 8) Figure 2. Insertin Lss vs. Frequency, Filter 2 (Pins 2 and 7) 3

4 PERFORMANCE INFORMATION (Cnt d) Typical Filter Perfrmance (T A = 25 C, DC Bias = 0 V, 50 Envirnment) Figure 3. Insertin Lss vs. Frequency, Filter 3 (Pins 3 and 6) Figure 4. Insertin Lss vs. Frequency, Filter 4 (Pins 4 and 5) 4

5 PERFORMANCE INFORMATION (Cnt d) Figure 5. Dide Capacitance vs. Input Vltage (Nrmalized t Capacitance at 0 VDC and 25 C) 5

6 PACKAGE DIMENSIONS UDFN8,.7x.35, 0.4P CASE 57BC 0 ISSUE O 2X 0.0 C PIN ONE REFERENCE 2X 8X 0.05 C NOTE 4 D ÉÉ 0.0 C TOP VIEW 0.05 C DETAIL B A SIDE VIEW A B E A (A3) C SEATING PLANE EXPOSED Cu A L ÉÉ MOLD CMPD A3 DETAIL B ALTERNATE CONSTRUCTIONS L DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS L NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.5 AND 0.25 mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A A A3 0.3 REF b D.70 BSC D E.35 BSC E e 0.40 BSC K 0.5 L L X L DETAIL A D2 E2 RECOMMENDED SOLDERING FOOTPRINT* 8X K e e/2 8 8X b 0.0 C A B 0.05 C NOTE 3 PACKAGE OUTLINE.40 8X 0.40 BOTTOM VIEW X PITCH DIMENSIONS: MILLIMETERS *Fr additinal infrmatin n ur Pb Free strategy and sldering details, please dwnlad the ON Semicnductr Sldering and Munting Techniques Reference Manual, SOLDERRM/D. ON Semicnductr and are registered trademarks f Semicnductr Cmpnents Industries, LLC (SCILLC). SCILLC reserves the right t make changes withut further ntice t any prducts herein. SCILLC makes n warranty, representatin r guarantee regarding the suitability f its prducts fr any particular purpse, nr des SCILLC assume any liability arising ut f the applicatin r use f any prduct r circuit, and specifically disclaims any and all liability, including withut limitatin special, cnsequential r incidental damages. Typical parameters which may be prvided in SCILLC data sheets and/r specificatins can and d vary in different applicatins and actual perfrmance may vary ver time. All perating parameters, including Typicals must be validated fr each custmer applicatin by custmer s technical experts. SCILLC des nt cnvey any license under its patent rights nr the rights f thers. SCILLC prducts are nt designed, intended, r authrized fr use as cmpnents in systems intended fr surgical implant int the bdy, r ther applicatins intended t supprt r sustain life, r fr any ther applicatin in which the failure f the SCILLC prduct culd create a situatin where persnal injury r death may ccur. Shuld Buyer purchase r use SCILLC prducts fr any such unintended r unauthrized applicatin, Buyer shall indemnify and hld SCILLC and its fficers, emplyees, subsidiaries, affiliates, and distributrs harmless against all claims, csts, damages, and expenses, and reasnable attrney fees arising ut f, directly r indirectly, any claim f persnal injury r death assciated with such unintended r unauthrized use, even if such claim alleges that SCILLC was negligent regarding the design r manufacture f the part. SCILLC is an Equal Opprtunity/Affirmative Actin Emplyer. This literature is subject t all applicable cpyright laws and is nt fr resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distributin Center fr ON Semicnductr P.O. Bx 563, Denver, Clrad 8027 USA Phne: r Tll Free USA/Canada Fax: r Tll Free USA/Canada rderlit@nsemi.cm N. American Technical Supprt: Tll Free USA/Canada Eurpe, Middle East and Africa Technical Supprt: Phne: Japan Custmer Fcus Center Phne: ON Semicnductr Website: Order Literature: Fr additinal infrmatin, please cntact yur lcal Sales Representative CM623/D

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