AN2111. RediSem APFC & LLC LED design guide. Overview. Top-level Design Notes. Resonant Half-Bridge

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1 RediSem APFC & LLC LED design guide AN2111 Overview RediSem s cntrller IC s can be used alngside an Active PFC stage in a 2-stage cnverter. The aim f this design guide is t explain hw t design the LED driver and hw t use RediSem s APFC cntrller IC s. Resnant cnverters, such as the LLC and LCC cnverters ffer lwer EMI, smaller size and higher efficiency than the equivalent Flyback cnverter. RediSem s patented Cntrlled Self-Oscillating Cnverter (CSOC) technlgy fr biplar transistr half-bridge cnverters cmbined with ur patented Primary Sensing Regulatin (PSR) methd ffers a very lw BOM cst fr cnverters ranging in pwer frm 20W up t 300W. In summary the key features and benefits are: Sft-start t minimize cmpnent cst Small size because f high frequency full wave resnant peratin High efficiency because f the biplar transistrs in a resnant half-bridge Lw EMI due t the resnant technlgy Lw cst, high reliability Biplar transistr half-bridge Primary-Side Regulatin (PSR) +/-5% (secndary side regulatin als pssible) On-Chip prtectin fr pen-circuit, shrt-circuit and vertemperature It is recmmended yu always use ne f RediSem s example designs as a starting pint fr new designs. Please check with us regularly fr updates and additinal infrmatin. As RediSem develps mre LED driver IC s and example designs, this Design Guide will be cntinually updated. Tp-level Design Ntes Resnant Half-Bridge The series-resnant half-bridge is ideally suited t LED Driver applicatins, because it prvides excellent efficiency and has inherently gd immunity and lw-nise characteristics t make EMC cmpliance very easy. RediSem s LED Driver Cntrller IC s are specifically designed t use resnant tplgies fr LED Drivers. Typical resnant cnverter technlgies used fr CC pwer cnversin is an LC r LCC cnverter which requires a capacitr and inductr in series with the islatin transfrmer primary winding. RediSem s cntrller ICs are unique in that they cmbine a self-scillating biplar cnverter (CSOC) tplgy with a simple half-bridge cntrl scheme using biplar switching devices, which are bth lwer cst and mre rbust than MOSFET alternatives. Furthermre, the self-scillating design is inherently immune t running in capacitive mde, which is a cnsiderable prblem fr MOSFET-based slutins. [Please see AN2113 fr mre infrmatin abut RediSem s biplar transistr and CSOC drive technlgy.] Applicatin Nte AN2111 1/11 May 2016

2 Using CSOC with Active Pwer Factr Crrectin (APFC) Fr sme applicatins, such as thse with very wide input/utput vltage requirements, it may be necessary t use Active Pwer Factr Crrectin (APFC). RediSem s LED cntrller IC s may be easily cmbined with a PFC regulatr design, as shwn in Figure 1. Bridge Active PFC HT+ Half Bridge Csense L R L N Line Filter, Prtectin Vsense R CS Output Rectific'n + - T MAIN Csense Vsense Cntrller Cmpnent selectin Figure 1: CSOC with APFC (simplified schematic) RediSem prvide a cmpnent calculatr tl t assist with the design prcess. Please check fr updates frm time t time. The guidelines belw shuld be cnsidered as a starting pint. The LED driver is intended t run super-resnantly, ie the tank resnant frequency shuld be lwer than the minimum perating frequency. Please refer t the schematic given in figure 2. Figure 2: APFC LED Driver schematic Applicatin Nte AN2111 2/11 April 2016

3 Pwer cmpnents HT Capacitr The minimum HT capacitr value is scaled at 0.33uF/W, which gives an acceptable amunt f vltage ripple at lw cst. S the apprximate value f the HT capacitr is given by the equatin: C HT = 0.33 V OUT I OUT Inductr, Capacitrs and Transfrmer The recmmended values fr the turns rati, series-resnant inductr, series-resnant capacitr and area prducts are given by the equatins belw: V HT N TURNS = V RATIO V OUT 2. I OUT C SER = 2 π. F RES. Q. V OUT. N TURNS L RES Area Prduct = AP LRES I OUT V OUT T MAIN Area Prduct = AP MAIN I OUT V OUT L RES = 2. Q. V 2 OUT. N TURNS π. F RES. I OUT Where the parameter values are given belw: V OUT Maximum utput vltage; I OUT Maximum utput current; Average HT vltage (frm APFC stage) V HT The recmmended starting values fr Q, FRES, VRATIO, APLRES and APMAIN are given belw: Quality Factr Q Resnant Frequency FRES khz Inductr Area Prduct AP LRES 8mm 4 /W Transfrmer Area Prduct AP MAIN 35 mm 4 /W Cnverter Vltage Rati V RATIO 0.43 The resnant capacitr(s) shuld ideally be lw-lss plyprpylene types, adequately rated fr the primary current and vltage. The ferrites used in LRES and TMAIN cres shuld be lw-lss types, such as PC47, PC95 r equivalents. Base Drive Cmpnents Base drive transfrmer is best prcured fully assembled and tested frm Acme Electrnics. ( 越丰电子 ( 广州 ) 有限公司 ). The ptimum value f the padding inductance L BASE may be estimated using the fllwing equatin: 0.25 L BASE = (F RES I OUT N TURNS 1 L RING ) where L RING is the inductance f the tridal base drive transfrmer, measured acrss the cntrl winding. If using the recmmended base drive transfrmer frm Acme, L RING = 2.5mH. When chsen crrectly, the strage time f the BJT s (Q1, Q2) shuld be rughly 200ns when running at full lad, which gives the mst efficient switching. Base drive resistr values can be calculated frm the equatin belw: R BASE = 0.6 Nturns I OUT Additinally, capacitrs CBASE1, CBASE2 may be fitted acrss the base-emitter f each BJT t prevent switching lsses due t sht-thrugh. Typically 10-22nF, the maximum values f CBASE1, CBASE2 is given by the equatin belw: C BASE < 2 I TXSTART V BE(MAX) t TXSTART N CTRL N BASE Applicatin Nte AN2111 3/11 April 2016

4 where N CTRL N BASE is the turns rati f the base drive transfrmer (nrmally 18 6 ). Auxiliary and VDD supplies The Auxiliary winding n the main transfrmer prvides the pwer fr the Auxiliary and VDD supply rails. The Auxiliary vltage will depend n the utput vltage and the Auxiliary/Secndary turns rati (NA/NS) which can be chsen by the fllwing equatin: N A N S 1.5 V DD V OUT(MIN) RAUX is chsen t deliver enugh pwer (but nt t much) t the IC: (V OUT(MAX) N A V N DD ) R AUX > S I DDSHUNT(MAX) R AUX < (V OUT(MIN) N A V N DD ) I DDREG(MAX) S The VDD decupling capacitr needs t be large enugh t sustain the VDD rail while the driver pulls up the utput, which puts a minimum value n CDD: C DD > I DDREG(MAX) t STARTUP /(V DDREG 2.4V) where: t STARTUP = C OUT V OUT(MIN) /I OUT The Auxiliary rail decupling capacitr CAUX value must be large enugh t prvide pwer t the VDD rail but small enugh t ensure that the primary vltage sensing functin is respnsive: C AUX > 300us/R AUX C AUX < 10ms/R AUX Current Sense Resistr The value f the current sense resistr RCS determines the value f the cnstant current limit and the vercurrent prtectin threshld. Ignring lsses and ther parasitic effects, the theretical value is given by the equatin belw: R CS = V CSREG I OUT N P N S Midpint capacitr A small mid-pint capacitr helps t reduce switching lsses in the BJTs and als helps t suppress RF emissins. If t big a value, the bridge is unable t cmmutate prperly particularly during startup r when running at lw line vltages, causing excessive heat dissipatin in the BJTs. The maximum value is difficult t calculate and is best chsen by experiment, starting with the value given by the equatin belw: C MID = ( 430 V HT ) 2 ( V OUT I OUT ) ( 34k ) 2nF 150 F RES Applicatin Nte AN2111 4/11 April 2016

5 Frmalised Frequency (Freq/F RES ) Operating frequency The typical frequency fr any utput lad range is given in figure 3 belw, shwn in nrmalized values, relative t the resnant frequency: Nrmalised Frequency vs Lad (Freq/F RES ) % 60% 70% 80% 90% 100% Lad Figure 3: Nrmalised Frequency vs Lad Transfrmer Cnstructin The recmmended transfrmer cnstructin fr TMAIN is shwn belw. W1: primary winding W2: auxiliary winding W3a, W3b: secndary windings (wund tgether) [Transfrmer cnstructin and ptimisatin is discussed in greater detail in App Nte AN2112] tape W3a W3b tape W2 W1 Table 1: Recmmended cnstructin fr transfrmer T MAIN Startup sequence Fr a smth startup, the RediSem cntrller IC shuld be started up just as the HT rail has been bsted up t the target vltage. Mst APFC cntrller IC s (e.g. the ST L6562A) have a very slw lp respnse, which means that the bsted HT rail will drp significantly in respnse t a large lad step. The RediSem PFC LED driver ICs prvide a special startup feature s that the lad presented t the bsted HT rail is switched in small steps, t minimize the HT undersht. Applicatin Nte AN2111 5/11 April 2016

6 The ptimum startup arrangement is described fully in AN2114. Hwever, a brief summary f the startup and shutdwn sequences is given here. Start Up 1. The APFC cntrller is started up via a resistr chain ff the rectified AC wavefrm; 2. Once the APFC cnverter starts, it prvides its wn pwer t run via the aux winding in the APFC bst inductr; 3. When the HT bus rises t almst full vltage, the APFC inductr aux winding als prvides pwer t the RediSem cntrller t start it up; 4. The RediSem cntrller delivers utput current starting frm 50%; 5. The RediSem cntrller increases the utput current t 100% ver a perid f abut 100ms, t minimise the transient effect n the APFC cntrller; 6. When the utput vltage rises, the main LLC cnverter pwer transfrmer pwers the RediSem cntrller. Shut Dwn 1. AC mains is lst, s the APFC stage turns ff; 2. The LLC cntinues t deliver pwer t the lad until the HT bus is run dwn; 3. The RediSem cntrller senses that there is a prblem and latches ff; 4. The RediSem cntrller can n lnger restart because the APFC bst inductr aux winding cannt deliver enugh pwer. The startup sequence is shwn belw in figure 4: HT (typically 400Vdc) VCC (APFC stage) ~18Vdc ~12Vdc VDD (CSOC stage) 3.45Vdc RED2621 Output Current 0V RED2601 0A Line input turned n CSOC starts up APFC starts up Output current settles Figure 4: APFC and CSOC startup sequence Applicatin Nte AN2111 6/11 April 2016

7 Creating the PCB There are a few key areas that are imprtant t layut crrectly in rder t have a gd design. Please fllw these guidelines: D nt have the CS resistr RCS t far away frm the IC Star the IC grund t the CS resistr grund. D nt have any ther currents flwing in the IC grund track Psitin the RC cmpnents (CRC, RRC) near the RC pin f the IC. Keep the tracks as shrt and thin as pssible Keep the track cnnected t the VFB, CS pins as shrt as pssible Put the capacitrs as clse t the pins as pssible Use a grund plane arund the IC s inputs (pins 1, 2, 5, 8) wherever pssible D nt have high currents flwing under the IC. Make sure that the main lad current is nt flwing in the IC GND Keep the IC s Aux pwer lp small. Track DAUX and CAUX directly back t the transfrmer GND Keep the base drive tracks shrt Keep the Nisy tracks shrt. These are the switched nde f the transistrs bth befre and after the base drive winding and tracks t the main inductr LRES Keep these Nisy tracks away frm the IC and small signal tracks Make sure that the main inductr LRES is plarized s that the nisy end (which is cnnected t Q1, Q2) is n the inside f the winding Keep the line input CM inductr and input cnnectr as far away frm the nisy tracks as pssible this helps EMI Keep the Nisy ndes away frm the secndary circuit this helps EMI If a transfrmer screen winding is t be used, cnnect it directly t the quiet side f the line input CM inductr using a separate track Make sure that the base drive windings are all crrect - this is a very cmmn prblem fr the driver nt starting An example f gd layut is given in figure 5 belw. Pay particular attentin t the 0V tracking. Figure 5: PCB layut example Trubleshting Checking befre turning n Once the driver has been assembled, please make these simple checks t avid wasting unnecessary time: Check input cnnectin and input fuse Check utput terminal +LED and LED Check the directin f all dides Check the vltage rating f utput Schttky dide in a half bridge it shuld be twice the max rated utput vltage plus a margin Check Transistr pinut is crrect, ECB, BCE Check base drive winding directin, rientatin and cnnectins are crrect Ensure that the transfrmer cre is nt gapped measure the primary winding inductance Applicatin Nte AN2111 7/11 April 2016

8 Check all Ecap plarities Start the driver using 230Vac with full lad applied, preferably an LED lad. It shuld perate well with crrect cmpnent values. If it cannt startup, please fllw the steps belw t debug it: Fault-finding - N utput If there is n utput, r nly a small amunt f scillating befre the driver switches ff again, then check the fllwing: Check HT cap (CHT) vltage. If there is a high vltage, discharge it and d sme mre checking Check base drive cnnectins. Fllw a RediSem schematic t check. Check t see if IC has pwer (3.3V t 3.6V) Check startup capacitr/resistr and RC capacitr cnnectin Check the BJT s are in the crrect way rund base, cllectr, emitter Check main transfrmer phase f secndary winding a half bridge shuld have tw ut-f-phase windings. If the windings are incrrectly in phase, the utput current is nrmally lw. If all are crrect, input AC mains again and lk at sme useful signals Measure the base f the bttm transistr Q2. Are there start pulses and scillatins? Measure the cllectr f the bttm transistr. Des it swing frm HT+ t HT- as it shuld? Measure the current thrugh the main inductr. Is it the crrect magnitude? Measure the IC s Vdd and RC pin. Is Vdd reaching 3.7V s that the IC can turn n? Is the IC scillating at the crrect frequency? Fault-finding - Repeated start-up (LED flashing) A driver may repeatedly start-up in the fllwing cases: Check VHT vltage level. Bad E-lad. Check by using an LED lad. Sme E-lads are slw t respnd s the IC senses an OVP and prtects against it by shutting dwn. See AN2116 fr mre data n using slw E-lads. Incrrect CDD value make it larger and try again. Incrrect scillatr cap value (t high frequency/ t lw frequency) lk at the RC pin and make sure it starts at the frequency yu expect: 50kHz-100kHz. Aux winding r aux dide DAUX is brken (N Aux pwer). Aux resistr RAUX is t large, s Aux pwer is nt enugh. Reduce it t 1k and try again. Current sensing resistrs R5 & R6 are incrrect check that the current in the resnant inductr is as expected. Aux sensing resistrs RFB1 & RFB2 rati is wrng. If VFB pin is t high (>1.2V) then the IC will prtect and shut dwn. CS pin is sensitive t nise in bad PCB layuts, an additinal capacitr 330pF CS t GND helps t reduce the nise. Quick Design Tests After building the first sample r after changing the design, these are sme quick tests t check that the design is prbably k befre ding a cmplete design validatin: Ripple at full lad, minimum line vltage (high frequency can be filtered by a small utput chke). Thermal test at minimum and maximum line inputs, maximum and minimum lads. Lw temperature startup at minimum line, full lad. Check when the unit will restart with higher utput vltage (ne extra LED). Reduce utput vltage until the unit shuts dwn (min lad vltage prtectin), related t RAUX value. Apply maximum line and full lad, then discnnect the lad; check the maximum utput vltage is SELV and will nt damage the utput dides DOUT1, DOUT2. Des the LED flash / flicker during startup r pwer ff? Applicatin Nte AN2111 8/11 April 2016

9 Fine-tuning the design It is smetimes necessary t fine-tune sme parameters arund the IC t ptimise the design: Fine-tune the CS resistr (RCS) t set an accurate utput current. Nte that resistrs generally have a psitive temperature cefficient, s it might be necessary t set the current slightly high at rm temperature. Nte: befre replacing the CS resistr, discharge the HT capacitr prperly therwise yu will destry the IC. RAUX sets the turn-ff utput vltage. A higher value f RAUX will cause the driver t shut ff at a higher vltage. Select RAUX t cpe with high temperature and IC spread. RFB1 / RFB2 rati sets the maximum utput vltage. Allw 10% headrm fr CC LED drivers. Efficiency f the unit might reduce if a lw quality cmpnents are used fr mid-pint capacitr (CMID) resnant capacitrs r switching dides. T reduce the switching frequency utput ripple current it is best t add a small inductr in series with Vut+. Thermals Thermal management is always an issue fr driver design. RediSem designs are intended fr peratin in the temperature range f -20 C t +50 C ambient when cased. Cmpnent temperatures shuld nt rise much abve 105 C except in special cases. If temperatures are high, then please try these suggestins belw: Transistrs t ht at minimum lad It is mst likely switching lsses because f the high HT vltage and high frequency Check the base drive transfrmer is wund crrectly windings shuld be n tp f each ther Check the base drive has the crrect inductance - Is the parallel inductr crrect? Check that the anti-parallel dides are gd (DMID1, DMID2) Replace with TSC s HS1J t make sure Check that the BJT s are gd start with the transistrs that RediSem recmmends Check that the midpint capacitr (CMID) is psitined crrectly and is f gd quality replace with a plyprpylene capacitr t cnfirm. A higher value reduces switching lsses in Q1, Q2. Replace with lwer r higher current rating transistrs. Transistrs are typically perated at a peak f half f their rating current. Smaller transistrs switch faster and larger transistrs have better cnductin lsses. Reducing the switching frequency will help switching lsses significantly Depending n the type f transistrs used, varying the base resistrs can imprve lsses Check base capacitrs are crrect increase and see if it imprves Check the base drive transfrmer lps are nt t lng Midpint capacitr CMID might be t small increase and check again Transistrs t ht at full lad Ht transistrs is mst likely caused by cnductin lsses r capacitive mde prblems Check fr capacitive mde switching. The bridge utput vltage (Cllectr f Q2) shuld always cmmutate befre the current passes thrugh zer. If nt, reduce the inductance f the base drive transfrmer by lwering the value f the parallel inductr If it is switching capacitively, als reduce the size f the midpint capacitr CMID and try again Increase the size f the transistrs Inductr t ht Is the transfrmer made using the crrect material? Use PC44 as a minimum, PC47 is ften a better chice. Resnant cnverters use bth psitive and negative flux density swing. It is therefre much mre imprtant t use better material in RediSem designs when cmpared t Flyback. Check the design using the cmpnent calculatr. Input the chsen material, wire diameter and turns int the calculatr s that it can apprximate the lsses. Because f skin and prximity effects in the wire, it is ften better t use less cpper rather than filling the bbbin. Check using the cmpnent calculatr. Applicatin Nte AN2111 9/11 April 2016

10 Transfrmer t ht Use the calculatr tl and fllw the design It is ften necessary t tweak the design in the calculatr, ptimizing the frequency and number f turns t minimize lsses. Applicatin Nte AN /11 April 2016

11 Abut RediSem RediSem designs and supplies semicnductr ICs fr energy efficient pwer management applicatins. RediSem uniquely cmbines extensive experience in pwer electrnics with in-depth knwledge f IC design and manufacturing and wrks with the wrld s tp suppliers and custmers. RediSem s unique patented IC and cnverter technlgies deliver maximum efficiency and perfrmance, while reducing verall bill f materials cst thrugh the use f biplar transistrs. RediSem s range f LED cntrl ICs can be used with RediSem s patented single stage LED cntrl slutin t prvide very high efficiencies with lw EMI all with a single IC. When cmbined, these features deliver a lw cst, high perfrmance LED driver slutin. RediSem s flurescent driver cntrller ICs achieve the advanced perfrmance f MOSFET drivers by using biplar transistrs at a fractin f the BOM cst. RediSem s range f SMPS (Switched Mde Pwer Supply) cntrl ICs enables lw-cst LLC cnverters with biplar transistrs that deliver very high efficiencies already meeting DE Level VI regulatins, have lw standby pwer and have much lwer EMI cmpared t flyback cnverters. All RediSem ICs are supprted by cmprehensive turn-key applicatin designs enabling rapid time t market. Fr further infrmatin please use ur cntact details belw Cntact Details RediSem Ltd IC Develpment Centre N 6 Science Park West Avenue Hng Kng Science & Technlgy Park Shatin, New Territries Hng Kng Tel Fax inf@redisem.cm Web: Disclaimer The prduct infrmatin prvided herein is believed t be accurate and is prvided n an as is basis. RediSem Ltd assumes n respnsibility r liability fr the direct r indirect cnsequences f use f the infrmatin in respect f any infringement f patents r ther rights f third parties. RediSem Ltd des nt grant any licence under its patent r intellectual prperty rights r the rights f ther parties. Any applicatin circuits described herein are fr illustrative purpses nly. Specificatins are subject t change withut ntice. In respect f any applicatin f the prduct described herein RediSem Ltd expressly disclaims all warranties f any kind, whether express r implied, including, but nt limited t, the implied warranties f merchantability, fitness fr a particular purpse and nn-infringement f third party rights. N advice r infrmatin, whether ral r written, btained frm RediSem Ltd shall create any warranty f any kind. RediSem Ltd shall nt be liable fr any direct, indirect, incidental, special, cnsequential r exemplary damages, hwsever caused including but nt limited t, damages fr lss f prfits, gdwill, use, data r ther intangible lsses. The prducts and circuits described herein are subject t the usage cnditins and end applicatin exclusins as utlined in RediSem Ltd Terms and Cnditins f Sale. RediSem Ltd reserves the right t change specificatins withut ntice. T btain the mst current prduct infrmatin available visit r cntact us at the address shwn abve. Applicatin Nte AN /11 April 2016