3 phase ac voltage source v a. Lac v b v c. 3 phase ac voltage source

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1 Perfrmance Imprvement f Half Cntrlled Three Phase PWM Bst Rectier Jun Kikuchi Madhav D. Manjrekar Thmas A. Lip Department f Electrical and Cmputer Engineering University f Wiscnsin { Madisn 1415 Engineering Drive Madisn, WI USA Astract The ptentl f the half cntrlled three phase pulsewidth mdulated (PWM) st rectier is investigated ased n theretical analysis, simulatins and experiments. The main advantages f this rectier are 1) a simpler and ecnmical system cmpared t a full cntrlled PWM rectier (reduced cntrlled switch cunt, single pwer supply fr gate drives, and shtthrugh free leg structure) and 2) etter perfrmance cmpared t a dide rectier (actively cntrllale dc link vltage and lwer input current ttal harmnic distrtin (THD)). In particular, it is shwn in this paper that input current THD f this rectier can e reduced y intentinally intrducing a lagging pwer factr current cmmand. Several issues fr further perfrmance imprvement are pinted ut fr future wrk. I. Intrductin The dide rectier is ne f the mst cmmnly used frnt end circuits fr pwer cnversin systems. Althugh it is a simple and ecnmical chice, its perfrmance is accrdingly pr, since it results in high input current ttal harmnic distrtin (THD) and prvides n cntrl n the dc link vltage. The full cntrlled pulsewidth mdulated (PWM) rectier has etter perfrmance [1], [2], and sme vartins f it have een reprted [3], [4]. It is hwever dicult t justify its high cst fr lw pwer applicatins. One f the alternatives t realize a cst eective slutin is discntinuus current mde dide rectier which has a single cntrlled switch n the dc link [5], [6]. The switch has t carry a large peak current due t the discntinuus cnductin mde f peratin, ut it can prvide satisfactry perfrmance in applicatins where the pwer rating is limited t aut 6 8 [kw]. Anther pssile chice is t use the half cntrlled rectier. Tw typical tplgies fr three phase applicatins are shwn in Fig. 1 and Fig. 2. The half cntrlled uck tplgy is analgus t the half cntrlled thyristr rectier where the thyristrs are replaced with gate turn switches such as insulated gate iplar transistrs (IGBT's). This uck tplgy is eynd the scpe f this paper. It has een reprted that the half cntrlled st tplgy ers large input current THD [7]. Hwever, the ptentl f this rectier has nt yet een fully investigated. The features f the half cntrlled three phase PWM st rectier can e categrized int tw grups a) nes cmpared t full cntrlled PWM st rectiers and ) nes cmpared t dide rectiers. The frmer are 3 phase ac vltage surce v a Lac v Lac v c Lac Fig phase ac vltage surce v i a a v i v i c c Fig. 2. i a i ic D 1 v ra S 4 S 6 D 3 v r S 2 D 4 D 6 D 5 D 2 dc link C v dc rc v dc Half cntrlled three phase PWM st rectier C ac C ac S 1 S 3 C ac S 5 D 1 D 3 v ra v r D 4 D 6 D 5 v rc D 2 L dc i dc dc link i dc L dc Half cntrlled three phase PWM uck rectier itemized as fllws: a) Simpler structure cmpared t full cntrlled PWM rectier; i) three cntrlled switches and gate drives; ii) single pwer supply fr three gate drives; iii) sht thrugh free leg structure; Item a)i) is self explanatry frm Fig. 1. Item a)ii) cmes frm the cmmn emitter structure in three legs. Item a)iii) results frm the fact that ne f tw switches in a leg is a dide. It may e nted that the half cntrlled st recti er tplgy des nt have pwer regenerating capaility. This disadvantage is incurred at the cst f taining sht thrugh free leg structure y eliminating ne f cntrlled switches in a leg. The features cmpared t the dide rectiers are itemized as fllws: ) Better perfrmance cmpared t dide rectier; i) actively cntrlled dc link vltage; ii) lwer input current THD; Item )i) cmes frm utilizatin f cntrlled switches in each leg. As fr item )ii), ne wuld intuitively expect lwer input current THD than that f dide rectiers ecause the

2 half cntrlled rectier has actively cntrlled switches which can e used fr input current cntrl. This is hwever nt always true as shwn in the fllwing sectins. The main fcus f this prject is t analyze the circuit ehavir f the half cntrlled three phase PWM st rectier and causes f its input current distrtin, and reduce it t a reasnale level. Tplgically, further vartins f cntrlled switches and dides cminatin are pssile. Fr example, ne can tain similar cnguratin t Fig. 1 y putting the upper three cntrlled switches and eliminating lwer three cntrlled switches. Hwever, in rder t take advantage f emitter cmmn structure, the tplgy shwn in Fig. 1 is the fcus in this paper. The ther cminatins f cntrlled switches and dides are nt taken int accunt here, ecause they d nt prduce identical current wavefrms in all the three phases. In the fllwing sectins, theretical analysis, circuit simulatin and experimental results are presented, where all the ntatins representing vltage, current, and switching devices crrespnd t thse in Fig. 1 unless therwise specied. II. Theretical Analysis Thrughut the theretical analysis presented in this sectin, the fllwing assumptins are made: 1) hysteresis current regulatr is used fr input current cntrl; 2) switching frequency cmpnent is negligile (lcal time averaged analysis is applicale); 3) all the pwer lss cmpnents are negligile; 4) dc link vltage is kept suciently high s that the peak f sum f ac surce vltage and ac side inductance vltage drp is less than dc link vltage, that is apprximately V dc > p 2 p 3[V 2 (!L ac I ) 2 ] 1 2 (1) where V and I are phase vltage and current, respectively, in rms. It has een reprted that the half cntrlled PWM st rectier has lw frequency input current distrtin even in the single phase case [8]. This is caused y its incapailitytachieve fur quadrant peratin n instantaneus asis, i.e. the half cntrlled single phase PWM st rectier can nt synthesize rectier terminal vltage whse plarity is ppsite t input current (2nd and 4th quadrants). This leads t distrted input current wavefrm at the eginning f every half cycle [8]. This is nt the case fr the half cntrlled three phase tplgy. Fig. 3 shws ac quantities fr unity pwer factr and sinusidal input current peratin, where the asterisks represent desired quantities. The ac vltages are assumed t e measured with respect t the neutral pint f three phase vltage surce. Lking at the eginning f sectr 6 fr example, since rectier terminal vltage v ra must e lagging ehind i a y angle specied in the gure, a small negative rectier terminal vltage v ra has t e synthesized with psitive phase current i a. This can e dne y utilizing the mst negative rectier terminal vltage v r and duty rati cn φ 6 v a sectr v ra * v v r * v c v rc * i a * i * i* c [deg] Fig. 3. Vltage and current wavefrms f three phase PWM rectier fr unity pwer factr and sinusidal input current peratin trl f switch S 4. The half cntrlled three phase tplgy can successfully synthesize sinusidal psitive half cycle current ased n the same perating principle as that f dcdc st cnverter, as lng as (2), which is tained with a gemetrical p inspectin, is satised. 3 2 V, 3 2!L aci > (2) The cnditin f (2) is relaxed if ne intentinally intrduces a small lagging current cmmand. If input current ecmes in phase with rectier terminal vltage, n such cnditin as (2) is necessary ecause the plarity f input current and rectier terminal vltage is always the same (1st and 3rd quadrants). It is interesting t ntice that if ne intrduces an intentinal lagging current cmmand such that nly 1st and 3rd quadrant peratin is needed, then the avementined lw frequency current distrtin in half cntrlled single phase tplgy can e eliminated at the cst f a small lagging fundamental pwer factr. This issue will e reprted y the authrs in a future paper. Fr negative half cycle current, the circuit ehavir is quite dierent. The situatin can e descried with the transitin frm sectr 2 t sectr 3 in Fig. 3 fr phase a withut lsing generality. Well cntrlled psitive half cycle current f phase a is nw entering int the negative half cycle. The nly way fr i a t ecme negative ist make dide D 4 cnduct. It is, hwever, impssile fr D 4 t immedtely start cnducting ecause D 4 is reverse sed y the mst negative phase, c. A clearer picture can e tained y three phase vectr dgrams as shwn in Fig. 4 which illustrate transitin frm sectr 2 t sectr 3. Physical quantities f vltages and currents can e read frm prjectin f vectrs n the hrizntal axis. If nly ne phase current is in negative half cycle, Fig. 4 (a), tw psitive currents, i a and i, are well cntrlled and the negative current, i c, is autmatically determined y Kirchh's current law. Then, all the three phase currents are well cntrlled as i a = p 2I sin(!t, ) (3) i = p 2I sin(!t,, 12 ) (4) i c = p 2I sin(!t, 12 ) (5) where is lagging angle f current cmmand and = fr the time eing. This mde is called the fully cntrlled mde in the fllwing explanatin.

3 rc jωl ac c a a jωl ac a ra a v D4 a jωl ac a ra c c jωl r ac rc jωl ac c c c jωl ac r v D4 (a) sectr 2 a () undary etween sectr 2 and 3 v D4 c = c = rc jωl jωl ac ac rc r jωl ac c c r jωl ac c c = jωl ac = jωl ac (c) sectr 3 (d) sectr 3 immedtely efre T Dn Fig. 4. Three phase vectr dgrams f half cntrlled three phase PWM st rectier fr unity pwer factr current cmmand peratin On the undary etween sectr 2 and sectr 3, Fig. 4 (), i a tries t reverse frm psitive t negative. It is hwever impssile fr antiparallel dide D 4 t immedtely cnduct ecause it is reverse sed. This reverse vltage is expressed in the gure as V D4, which is difference etween the prjectin f tw rectier terminal vltage vectrs, v ra and v rc, n the hrizntal axis. Until D 4 is frward sed, phase a carries n current as shwn in Fig. 4 (c) and (d). The three phase currents in this situatin are expressed as i a = (6) i = p 2I sin(!t,, 12 ) (7) i c =,i (8) This mde is called the incming negative current zer mde. After D 4 is frward sed, current sharing etween the tw negative phases, a and c, is determined in passive fashin ecause n active switch is eective in these tw phases. Analytical expressin f this case can e tained in the same manner as in the analysis f cmmutatin verlap p perid in a dide r thyristr rectier, as fllws: i a = p 3V [cs(!t 2!Lac 15 ), cs(!t Dn 15 )], I p [sin(!t 2,, 12 ), sin(!t Dn,, 12 )] a (9) i = p 2I sin(!t,, 12 ) (1) i c =,i a, i =, p 3V p [cs(!t 2!Lac 15 ), cs(!t Dn 15 )], I p [sin(!t 2,, 12 ) sin(!t Dn,, 12 )] (11) where T Dn is the instance at which dide D 4 starts cnducting measured frm the time rigin f v a, i.e. psitive I II III IV I II III IV I II III IV I: fully cntrlled mde II: incming negative current zer mde III: passive cmmutatin mde IV: utging negative current zer mde Fig. 5. Operating mdes f half cntrlled three phase PWM st rectier zercrssing pint fv a. This mde is called the passive cmmutatin mde. After this mde, the circuit has tw pssile ehavirs. If i c reaches zer efre i c ecmes psitive, the three phase current expressins are i a =,i (12) i = p 2I sin(!t,, 12 ) (13) i c = (14) In this mde, negative current is cmpletely taken ver y i a frm i c. This pint is clear y cmparing (12) (14) with (6) (8). This mde is called the utging negative current zer mde. After this mde, the circuit ehavir returns t the fully cntrlled mde expressed y (3) (5) when i c ecmes psitive. If i c reaches zer after i c ecmes psitive, the passive cmmutatin mde expressed y (9) (11) cntinues until i c rejins i c. Then, the circuit ehavir returns t the fully cntrlled mde expressed y (3) (5), and the utging negative current zer mde des nt take place. In this case, a certain prtin f psitive half cycle current is distrted y invasin f the passive cmmutatin mde. Fig. 5 shws a simplied sketch f the current wavefrms. Each 12 [deg] can e divided int mde I IV descried ave. Fig. 6 shws analytical input current wavefrms and spectrum calculated ased n (3) (14) with MATLAB, where it is assumed that rms line t line vltage V ll = 23[V ], I =23:5[A] fr = with 9 [kw] pwer transfer, and L ac =3:[mH]. In this example, a large input current THD, 27. [%], is served. One can als recgnize a certain amunt f even harmnics due t asymmetrical current wavefrm etween psitive and negative half cycles. The utging negative current zer mde is excluded and the passive cmmutatin mde enters int the eginning f psitive half cycle. It is dependent n ac side inductance and input current whether r nt the utging negative current zer mde takes place. In PWM rectiers, unity pwer factr peratin and cmmand are always desired and used [1] [4]. It is hwever pssile t reduce the input current THD served

4 [dba],i,ic [A] input current THD = 27. [%] harmnics rder time [sec] Fig. 6. Input current wavefrms and spectrum ased n theretical analysis fr unity pwer factr current cmmand peratin, = [deg], V ll =23 [V], I =23.5 [A], P ut =9 [kw], L ac =3. [mh], input current THD=27. [%] ave y intentinally intrducing a small lagging angle int the current cmmand, i.e. > in (3) (14). Fig. 7 shws ac quantities fr 2 [deg] lagging pwer factr peratin. In this example, the perating regin in which the plarities f rectier input terminal vltage and input current are ppsite (2nd and 4th quadrants) is at the end f each half cycle. The cnditin with which ne can guarantee well cntrlled sinusidal psitive half cycle current is tained with a gemetrical inspectin as V cs(3 ) 3 2!L aci, V sin > (15) Fig. 8 shws three phase vectr dgrams illustrating the transitin frm sectr 2 t sectr 3 in Fig. 7. Fig. 8 (a) shws three phase vectrs twards the end f sectr 2. Just after entering sectr 3, active switch S 4 is still active until i a ecmes zer, ecause i a is in psitive half cycle. When i a reaches zer, Fig. 8 (), phase a lses cntrl. Hwever, the reverse s acrss D 4, i.e. V D4 in Fig. 8 (), is smaller than that f unity pwer factr current cmmand peratin shwn in Fig. 4 (). Fig. 8 (c) and (d) shwvectr dgrams fr an incming negative current zer mde and fr the instance at which D 4 turns n, respectively. Cmparing Fig. 8 () (d) with Fig. 4 () (d), ne can recgnize that the perid during which D 4 can nt cnduct is shrter in Fig. 8, aut 1 [deg], than in Fig. 4, aut 3 [deg]. Fig. 9 shws analytical input current wavefrms and spectrum calculated ased n (3) (14) with MATLAB fr =2 [deg] with the same V ll, P ut (I =24:2[A]), and L ac as in Fig. 6. In this example, utging negative current zer mde is served. The input current THD is decreased dwn t 12.1 [%]. Althugh a certain amunt f even harmnics are still present, they are als smaller than thse f Fig. 6. The slid curves in Fig. 1 and Fig. 11 shw input current THD vs. current cmmand lagging angle characteristics with ac side inductance L ac and dc utput current I dc as parameters, respectively, calculated with MATLAB ased n (3) (14), where 6 [V] dc link vltage and 9 [kw] rated pwer are assumed. Then, 3. [mh] f L ac crrespnds t aut.2 [pu]. 6 v rc * sectr v a v ra * v v r * v c i a * i * i* c θ * θ * [deg] Fig. 7. Vltage and current wavefrms f three phase PWM rectier fr 2 [deg] lagging current peratin jωl ac a a jωl ac a a ra ra v D4 a a rc c c jωl ac c c rc jωl r ac r jωl ac c jωl ac c rc vd4 (a) sectr 2 () sectr 3 at i a = a jωl ac c c = jωl ac c = (c) sectr 3 immedtely efre T Dn φ a c = jωl ac r jωl ac r rc c jωl ac c = jωl ac (d) sectr 3 at T Dn Fig. 8. Three phase vectr dgrams f half cntrlled three phase PWM st rectier fr 2 [deg] lagging current cmmand peratin [dba],i,ic [A] input current THD = 12.1 [%] harmnics rder time [sec] Fig. 9. Input current wavefrms and spectrum ased n theretical analysis fr 2 [deg] lagging current cmmand peratin, =2 [deg], V ll =23 [V], I =24.2 [A], P ut =9 [kw], L ac =3. [mh], input current THD =12.1 [%]

5 3 25. x x} L x ac =.1 [pu] x x x } L 15. ac =.2 [pu] 1 experimental } L ac =.3 [pu] x L ac =.1 [pu] 5. L ac =.2 [pu] theretical simulatin L ac =.3 [pu] I dc = 1. [pu] fixed lagging angle f current cmmand [deg] Fig. 1. Input current THD vs. current cmmand lagging angle characteristics with L ac as a parameter input current THD [%] input current THD [%] 3 x 25. x } I dc =.1 [pu] x x x x } I 15. dc =.2 [pu] 1 experimental } I dc =.3 [pu] x I dc =.1 [pu] 5. I theretical dc =.2 [pu] I simulatin dc =.3 [pu] L ac =.2 [pu] fixed lagging angle f current cmmand [deg] Fig. 11. Input current THD vs. current cmmand lagging angle characteristics with I dc as a parameter It may e seen frm these gures that the input current THD is dependent n ac side inductance and perating pint. These results suggest that ne f pssile cntrl principles is t set up lagging current cmmand such that the rectier traces the trajectry f minimum input current THD. III. Simulatin Results Fig. 12 and Fig. 13 shw simulatin results cmputed with SABER fr the same perating cnditins as thse f Fig. 6 and Fig. 9, respectively. Characteristics f input current THD vs. current cmmand lagging angle tained frm SABER simulatin are shwn as the dashed curves in Fig. 1 and Fig. 11. They are in reasnaly gd agreement with thse f the theretical analysis. The discrepancy etween the circuit simulatin and theretical results mainly arises frm lssy cmpnents mdeled in the SABER simulatin such as resistance in ac side inductrs, dc link capacitr equivalent series resistance (ESR), and vltage drps acrss semicnductr devices. IV. Experimental Results Fig. 14 shws input current wavefrms and spectrum tained frm a hardware experiment fr the same perating cnditin as thse f Fig. 6 and Fig. 12. Fig. 15 shws thse fr 25 [deg] lagging current cmmand peratin. The plts shwn as `x', `' and `' in Fig. 1 and () 6 6 db(i/hz) (A).3k.6k.9k 1.2k f(hz) (A) : t(s) 6 6 Maximum: input current THD = 25.3 [%] t(s) db(i/hz) : f(hz) i ic () : t(s) * Fig. 12. Input current wavefrms and spectrum simulated with SABER fr unity pwer factr current cmmand peratin, = [deg], V ll =23 [V], V dc =6 [V], I dc =15 [A], P ut =9 [kw], L ac =3. [mh], input current THD =25.3 [%] () 6 6 db(i/hz) (A).3k.6k.9k 1.2k f(hz) (A) : t(s) t(s) i* ic* Maximum: 3.76 input current THD = 12.6 [%] db(i/hz) : f(hz) i ic () : t(s) * Fig. 13. Input current wavefrms and spectrum simulated with SABER fr 2 [deg] lagging current cmmand peratin, =2 [deg], V ll =23 [V], V dc =6 [V], I dc =15 [A], P ut =9 [kw], L ac =3. [mh], input current THD =12.6 [%] Fig. 11 are measured pints tained in hardware experiments. The theretical analysis and simulatin results presented in the preceding sectins are veried y the experimental results. i* ic*

6 THD: [%] [db] Y: 1 [db/div] X: 12 [Hz/div] GND Y: 2 [A/div] X: 2 [msec/div] Fig. 14. Experimental input current wavefrms and spectrum fr unity pwer factr current cmmand peratin, = [deg], V ll =23 [V], V dc =6 [V], I dc =15 [A], P ut =9 [kw], L ac =3.1 [mh], input current THD =27.9 [%] THD: [%] [db] Y: 1 [db/div] X: 12 [Hz/div] GND Y: 2 [A/div] X: 2 [msec/div] Fig. 15. Experimental input current wavefrms and spectrum fr 25 [deg] lagging current cmmand peratin, =25 [deg], V ll =23 [V], V dc =6 [V], I dc =15 [A], P ut =9 [kw], L ac =3.1 [mh], input current THD =11.7 [%] V. Scpe fr Future Wrk The input current THD reductin presented in this paper was tained at the cst f lagging fundamental pwer factr. One might cmpensate this eect y placing a three phase capacitr etween the utility input terminals and ac side three phase inductrs. In this case, specl care shuld e taken t avid unwanted LC resnance. It is evident that the even harmnics served in the preceding sectins might excite undesirale resnance. Since the psitive half cycle f input currents is reasnaly under cntrl, ne wuld e ale t reduce the even harmnics y cntrlling psitive half cycle wavefrms t mimic negative half cycle wavefrms s that the half wave symmetry can e maintained. As shwn in Fig. 11, the input current THD reductin eect is highly perating pint dependent. In particular, minimum input current THD tainale y this scheme increases as the lad current decreases. One might mitigate this prlem y switching the cntrl scheme frm PWM current cntrl t simultaneus switching f all the three cntrlled switches with a xed duty rati fr discntinuus current mde f peratin. This peratin is an equivalent t that f the discntinuus current mde dide rectier [5], [6]. Since a half cntrlled three phase st rectier has three cntrlled switches in parallel and the discntinuus mde shuld e applied nly t light lad cnditin, the switching devices d nt have t carry large peak current. VI. Cnclusins The ptentl f the half cntrlled three phase PWM st rectier has een investigated. The circuit ehavir and causes f input current distrtin have een analyzed y theretical apprach. The analytical results have een checked y detailed circuit simulatins and experimental results. Thrugh this prcess, it has een shwn that the input current THD can e decreased y intentinally intrducing a lagging pwer factr current cmmand. Since this eect depends n ac side inductance value and perating pint, quantitative data have een presented with varius values f L ac and I dc as parameters. Several issues fr further perfrmance imprvement have een pinted ut fr future wrk. REFERENCES [1] P. D. Zigas, YG. Kang and V. R. Stefanvic, \PWM cntrl techniques fr rectier lter minimizatin," Prceedings f IEEE PESC '84, 1984, pp [2] B. T. Oi, J. C. Salmn, J. W. Dixn and A. B. Kulkarni, \A 3 phase cntrlled current PWM cnverter with leading pwer factr," Cnference recrd f IEEE IAS annual meeting '85, 1985, pp [3] L. Malesani and P. Tenti, \Threephase AC/DC PWM cnverter with sinusidal AC currents and minimum lter requirement," IEEE Trans. n Industry Applicatins, Vl. IA23, N. 1, January/Feruary 1987, pp [4] Y. Zha, Y. Li and T. A. Lip, \Frce cmmutated three level st type rectier," IEEE Trans. n Industry Applicatins, Vl. IA31, N. 1, January/Feruary 1995, pp [5] A. R. Prasad, P. D. Zigas and S. Mans, \An active pwer factr crrectin technique fr threephase dide rectier," Prceedings f IEEE PESC '89, 1989, pp [6] Y. Jang and M. M. Jvanvic, \A cmparative study f singleswitch threephase, highpwerfactr rectiers," Cnference recrd f IEEE APEC '98, 1998, pp [7] C. H. Trevis, V. J. Fars, J. B. Vier and C. de Freitas, \A three phase PWM st rectier with high pwer factr peratin and an acceptale current THD using nly three switches," Prceedings f EPE '97, 1997, pp [8] J. C. Salmn, \Techniques fr minimizing the input current distrtin f current cntrlled singlephase st rectiers," IEEE Trans. n Pwer Electrnics, Vl. 8, N. 4, Octer, 1993, pp

7 Errata Fig. 11 Replace I dc =.1[pu] y I dc =.5[pu] Replace I dc =.2[pu] y I dc =1.[pu] Replace I dc =.3[pu] y I dc =1.5[pu] Replace x I dc =.1[pu] y xi dc =.5[pu] Replace I dc =.2[pu] y I dc =1.[pu] Replace I dc =.3[pu] y I dc =1.5[pu]