AN IMPROVED HIGH PERFORMANCE THREE PHASE AC-DC BOOST CONVERTER WITH INPUT POWER FACTOR CORRECTION

Transcription

1 let-uk nternatinal Cnference n nfrmatin and Cmmunicatin Technlgy in Electrical Sciences (CTES 2007), Dr. MG.R. University, Chennai, Tamil Nadu, ndia. Dec , pp AN MPROVED HGH PERFORMANCE THREE PHASE AC-DC BOOST CONVERTER WTH NPUT POWER FACTOR CORRECTON V.Jaikumar Assistant Prfessr RGMCET, Nandyal, A.P. jai.mtech@yah.c.in Dr.G.Ravi Assistant Prfessr RGMCET, Nandyal, A.P. ravigpec@yah.cm V.Vijayavelan Assistant Prfessr RGMCET, Nandyal, A.P. vijay.velan@gmail.cm M.Kaliamrthy Assciate Prfessr RGMCET, Nandyal, A.P. kalias_ifet@yah.cm Keywrds: Bst cnverter, Pwer factr crrectin, three phase, ac-dc cnverter, ttal harmnic distrtin. Abstract A three-phase 3-level unidirectinal ACmC cnverter is prpsed t achieve almst unity pwer factr and reductin f harmnics distrtin. A pwer factr crrectr using the hysteresis current cntrl technique is presented t imprve the pwer quality at the rectifier side. A high-pwer-factr rectifier based n a neutral pint switch clamped scheme is presented. A cntrl scheme fr the prpsed rectifier is prpunded t draw a sinusidal line current with nearly unity pwer factr, achieve balanced neutral pint vltage and regulate the DC bus vltage. A hysteresis current cntrl scheme is used t track the line current in phase with the mains vltage. The line current cmmand is derived frm a vltage cntrller and a phaselcked lp circuit. A capacitr vltage cmpensatr is emplyed in the prpsed cntrl algrithm t achieve the balanced neutral pint vltage. The effectiveness and validity f the prpsed cntrl strategy is verified thrugh cmputer simulatin results. The simulatin result reveals that the prpsed cntrl technique ffers cnsiderable imprvement in Pwer factr and reductin in ttal harmnic distrtin. 1. ntrductin n the present scenari, there have been lts fdevelpments in the field f pwer electrnics by shaping the utilitysupplied vltages by means f pwer semicnductr devices. Often electrnic equipment is supplied by 50/60 Hz utility pwer and mre than 50% f pwer is prcessed thrugh sme kind f pwer cnverters. Cnventinally, mst f the pwer cnversin equipment emplys dide rectifiers r thyristr rectifiers t cnvert AC vltage t DC vltage befre prcessing it. Phase-cntrlled rectifiers are widely utilized in the frnt-end cnverter fr bth uncntrllable and cntrllable DC-bus vltage in industrial and cmmercial applicatins. w pwer factr and nn-sinusidal line currents are drawn frm the AC surce wing t large electrlytic capacitr used n the DC link. Pwer pllutin wing t the use fpwer cnverters results in serius pwerquality prblems in transmissin and distributin systems. Thus, internatinal standards such as EC are defined [1] t restrict the harmnic cntents n the AC-surce current. Pwer pllutants such as reactive pwer and current harmnics result in line vltage distrtin, heating f the transfrmer cre and electrical machines and increased lsses in the transmissin and distributin line. n the single-phase vltage-dubler bst rectifiers with ne, tw, three r fur switches were used t achieve pwer factr crrectin and DC-bus vltage regulatin [2]. The DC bus vltage is twice the peak vltage mains. Switched mde rectifiers with three r fur rectifier legs can achieve highpwer factr and lw current harmnics in the three-phase three-wire r fur-wire systems. Six r eight pwer switches are used in the three-leg r fur-leg cnverter [3-7] t generate biplar PWM wavefrms n the AC terminal. fthe bidirectinal pwer flw is nt necessary in the applicatin system, switched-mde rectifiers are nt a gd chice fr the large number f pwer switches. Multilevel rectifiers and inverters have been prpsed [8-12] fr high-pwer and medium-vltage applicatins because they prvide advantages such as the lw vltage rating f pwer semicnductrs and lw vltage harmnics. Pwer factr crrected (PFC) cnverters are an imprtant area f study and research in the Pwer Electrnics field. The prpsed AC-DC cnverters prvide stable DC vltage at the utput with high input pwer factr. This ability makes PFC cnverters are extremely attractive chice fr ftline pwer supplies and ther AC-DC fr pwer cnversin applicatins because f increasing cncerns abut varius pwer quality regulatins and standards. These cnverters cater t the unique requirements f a large number f applicatins. Because f the standards and the prblems related t the distrted line current, pwer supply manufacturers mst prbably have t equip their prducts with pwer factr crrectin (PFC) circuits. 2. AC-DC Cnversin AC t DC rectifiers usually interface with the mains. These devices cnvert the sinusidal line vltage t a de vltage. t is a well-knwn fact that the input current fa SMPS tends t have a nn-sinusidal, distrted wavefrm. The distrted line current f a pwer cnverter is cmpsed f the line frequency cmpnent and higher frequency harmnic cmpnents f the current. t shuld be nted that nly the line frequency cmpnent f the current is carrying pwer when vltage is sinusidal. As use f energy is grwing, the 221

2 let-uk nternatinal Cnference n nfrmatin and Cmmunicatin Technlgy in Electrical Sciences requirements fr the quality f the supplied electrical energy are becming stricter. This means that pwer electrnic cnverters are used t cnvert the input vltage t a precisely regulated de vltage. 2.1 Circuit Cnfiguratin and Operating Principle Operating State 1 Cnventinal3-level AC-DC cnverters are based n neutralpint clamped, flying capacitr and series cnnectins fh- bridge tplgies. A three-level neutral-pint dide-clamped 3. Sxy = 1 (r 0) if active switch Sxy is turned n (r ff), x =a -.. c, y = The capacitr vltages n the DC side are equal (Vcl=Vc2=Vdc/2). Fig. 2 shws the equivalent circuit f the first perating state. n this state, psitive line current flws thrugh the li~c t,;~ : ---;+ V ~ '2 - ~~C ;c) Fig. 2. Equivalent Circuit fr perating state 1 Fig. 1. Three-Phase Circuit Cnfiguratin cnverter needs fur active switches and tw clamping dides in each cnverter leg t achieve pwer factr crrectin. A three-level cnverter with flying capacitr tplgy needs fur active switches and ne flying capacitr t draw a sinusidal line current frm the utility system Fig. 1 shws the prpsed three-phase unidirectinal pwer flw rectifier t draw a sinusidal line current with almst unity pwer factr and maintain the DC-bus vltage cnstant. There are a bst inductr, tw pwer dides Dal and Da2' tw DC-bus capacitrs C1 andc2, and tw active switches Sal and Sa2 in the prpsed cnverter. The vltage stress f switch Sa2 and dide D82 is equal t half the DC-bus vltage and the vltage stress fswitch Sal and dide Dal is equal t the DC-bus vltage. N clamping capacitr r dide isneeded in the prpsed Single-phase cnverter. A uniplar PWM vltage wavefrm is generated n the vltage Va. 2.2 Principle f Operatin bdy dide f active switch Sal and dide Da2 t charge capacitr C. The AC-side vltage Va equals vde/2. v a = v dc /2 () The line current isa is linearly decreasing in this state because the bst inductr vltage is negative. v =V Sa -v dc /2<O Operating State 2 The line current flws thrugh the bdy dide f active switch Sal and active switch Sa2. The AC-side vltage Va equals. (2) There are tw independent active switches in the prpsed cnverter leg. Uniplar PWM vltage wavefrms can be generated n the AC terminal t neutral-pint vltages. The fllwing assumptins are made in the prpsed cnverter.. The pwer switches are ideal. 2. The supply vltage is cnstant during ne switching perid. Fig. 3. Equivalent Circuit fr perating state 2 The bst inductr vltage equals Vsa The line current i sa is linearly increasing ifthe mains vltage Vsa is psitive. 222

3 An mprved High Perfrmance Three Phaseac-DC Bst Cnverter with nput Pwer Factr crrectin Operating State 3 During each half cycle f mains vltage, the high vltage level n the AC side is used t decrease the line current and a The equivalent circuit fthe third perating state is shwn in lw vltage level is adpted t increase line current. The Fig. 4.The negative line current flws thrugh switch Sal and same analysis f phase-b and phase-c can be achieved the bdy dide fswitch Sa2 t btain AC-side vltage va=o. accrding t the same analysis Equivalent Circuit P" V(1 '( The system behavir f the prpsed AC/DC cnverter can be expressed as, Fig. 4. Equivalent Circuit fr perating state 3 The line current is linearly decreasing because, v = VS < 0. Vsa -Va -r r V isa sb isa -V bo -(3) isb isb d -r v -v isc isc + dt ~ Vel -1-1 Vel i V e2 RC RC V e2 C _i RC 2 RC 2 c Operating State 4 The equivalent circuit fthe furth perating state is given in Fig. 5. Fig. 5 Equivalent Circuit fr perating state 4...±." 'f '--- _ The line current flws thrugh capacitr C2 and Dal t generate AC terminal vltage Va=VC2.The negative line current will charge capacitr C2. The bst inductr vltage equals vsa + Vc 2 > 0 such that the line current is linearly increasing. n the state 4 nly ne dide Dal is cnducting as shwn in Figure 5. ;st -. - _2...: --' "i ' 'st ~',- " \ , Based n this analysis f fur perating states in each cnverter leg, tw perating states can be selected in each half cycle f mains vltage t cntrl the line current with almst unity pwer factr. During the psitive line current the states and 2 are used t generate high vltage level (vdj2) and lw vltage level (0) n the vltage V a During the negative line current the states 3 and 4 are selected t generate vltage levels 0 (high vltage level) and -Vdd2 (lw vltage level) n the AC terminal vltage respectively. Fig. 6 Equivalent circuit fr prpsed AC-DC Cnverter where Va,l'b and Vc are AC terminal t neutral-pint vltages and i1 and hare DC-side currents. Based n the n and ff states f the active switches in the prpsed cnverter the DC-side currents and AC terminal vltages can be expressed as, 223

4 let-uk nternatinal Cnference n nfrmatin and Cmmunicatin Technlgy in Electrical Sciences Va = (1-8aJsign~sa)vcl -(1-Sal) ~ -sign~sa) ]ve2 -(4) V b =(-8bJsign~sb)vc1 -(-~)[1-sign~sb)]ve2 -(5) V e =(l-sejsign~se)vc1 -(1-Sc1)[1-sign~se)]ve2 -(6) The DC Side currents i 1 and hare, i 1 =(1-Sa2)sign(vsa )isa + (1- Sb2)sign(vsb ) isb + (1-Sc2)sign(vsc )isc - (7) ~ =(-Sal)[1-sifJl(~a)isa +(-SblX-sigt(v.w,)] ish +(-Sc1)[l-sigr(v~)] i sc - (8) where,. {, Vsx >0 Slgn(V ) sx =,x = a,b,c 0, vsx < 0 a,b and c are the legs fthe three phase ac-dc cnverter. Based n (3)-(8) the system equatins f the prpsed cnverter can be rewritten as, di. di ~ dt -r ~- ~ di - ~ 1-: 02.siF(v.) -G.~.sigl(v..) -G Ṣd.sig(v.,) ~ _1-: (l_sign(v.)] _1~61(l_sign(V..)] _1~d[_sigr(V.,)] 3. Cntrl Scheme _1-:02 sigr(v.) 1-:01 [-sigr(v.)] v. _-s"zligr(v..) -s..(l-ligr(v..)] i. ~ ~ _1-;drigr(V.,) 1-;d[l_s (V",)] i., + ~ -(9) vd -~ -~ v d 0 0 -~ -~ The bjective fthe cntrl scheme fthe bst cnverters is t regulate the pwer flw ensuring tight utput vltage regulatin as well as unity input pwer factr. The cntrl structure shwn in Fig. 7 is the mst extensively used cntrl scheme fr these cnverters and essentially similar cntrl philsphy is applied t all the ther tplgies f bst cnverter. Prprtinal integral vltage cntrller and hysteresis based current cntrller are used in the prpsed cntrl scheme. Tw cntrl lps are used in the prpsed three phase high pwer factr AC-DC cnverter t achieve unity pwer are, 1. Hysteresis Band PWM current cntrl 2. Prprtinal integral Vltage cntrl. The main functins fthe prpsed cntrl scheme are, 1. Pwer-factr crrectin. 2. Current-harmnic reductin. 3. DC-link: vltage regulatin. 4. Neutral pint Vltage Cmpensatin The internal high-bandwidth current cntrl system is designed t achieve a shrt settling time and the uter lwbandwidth vltage cntrl system is designed t be smewhat slwer t maintain the DC bus vltage cnstant. Fig. 7 shws the Cntrl scheme fr prpsed cnverter. n the inner lp a carrier based current cntrller is used t track the reference line current and in the uter lp cntrl a classical prprtinal-integral cntrller was used t balance the AC-side input pwer and DC-side utput pwer s that the DC-side capacitr vltage can be a cnstant value. f the DC-side vltage is lwer than the reference vltage, the utput value fthe P cntrller will increase the amplitude f the line current cmmand t increase the input AC pwer fr cmpensatin f DC-bus vltage drp. fthe DC-bus vltage is higher than the reference vltage, the utput value f P cntrller will decrease the input AC pwer fr cmpensatin the DC side vltage 3.1 Prprtinal ntegral Vltage Cntrller T achieve the pwer balance between the AC-surce side and DC-lad side f the ACmC cnverter, a prprtinal integral vltage cntrller is used t btain the amplitude f the line current cmmands. The prprtinal plus integral (P) is prbably the mst cmmnly used cntrller in the industry that arguably the P cntrller is the simplest practical cntrller that prvides integral actin which required in many prcess cntrl applicatins fr asympttic tracking f set pint cmmands. The amplitude f line current cmmand is expressed as, s =K p l1v dc + K j fl1vdcdt - (10) Where Kp and ~ are prprtinal and integral gains respectively \vde = V*de -vde is the DC-bus vltage errr, v dc is the vltage cmmand and vde is the measured DCside vltage. The parameters f vltage cntrller can be selected frm the given system transfer functin and the designed damping factr and natural angular frequency fthe vltage respnse. The vltage errr between the vltage cmmand and the measured DC-bus vltage can be reduced by adjusting the amplitude f the line currents. T achieve unity pwer factr at the input side f the cnverter, a phaselcked lp circuit generates three unit sinusidal waves with phase shift. These balanced sinusidal waves are synchrnized t three phase surce vltages and expressed as, i sa (t) e a (t) s sinrt isb(t) =s eb(t) = s sin(rt - 2n /3) -(11) ise(t) ee(t) s sin(rt + 2n /3) 3.2 Hysteresis Band PWM Cntrl Hysteresis cntrl shwn in Fig.8 is als called tleranceband r dead-band cntrl. This cntrller type recgnizes that vltage surce cnverters can nly have seven different utput vltages. This leads naturally t a limit-cycle scillatin in the line current vectr, which by the cntrller is kept inside a small area fsme shape in the current vectr space. 224

5 An mprved High Perfrmance Three Phaseac-DC Bst Cnverter with nput Pwer Factr crrectin nfl'utral-pint vttaqe- cnmpf>n-;atr V. C1 Vsa -+- P i \f'd"~t~ \de PV'M generatr T s 'r\' T C H E S Vsb Vsc Vs.. 1 Vst V sc Fig. 7. Cntrl Sche~ fr Prpsed Cnverter. The advantage is a knwn deviatin frm the current reference, but the switching pattern is mre r less randm, making it hard t predict cnverter lsses. Cunverter Output" Vult"aKe _'i. - Tlerance Set:Pi.nt:~ Fig. 8.Hysteresis Band + Tlerance C1.llTent: 3.4 PWM Technique A hysteresis based PWM technique is and used t generate apprpriate switching signals fr the pwer switches.hysteresis current cmparatrs track the inputcurrent references and the PWM generatr btains the switching signals fr the pwer switches. The line-current errrs between the measured line currents and the current cmmands are sent t the hysteresis cmparatrs t generate the prper PWM signals fr active switches. Fig. 9 shws the surce vltage, line current, PWM signals and AC-side vltage fr each cnverter leg where x =a, b, c. 3.3 Neutral pint vltage cmpensatin n the prpsed cntrl scheme, a neutral-pint vltage cmpensatr is used t balance the neutral-pint vltage. T balance the neutral-pint vltage under lad variatin a vltage cmpensatr is used in the cntrl scheme t cmpensate the neutral-pint vltage. This additinal current fr neutral-pint balance is given as, npc =K (VC 2 - Vc l ) - (12) where Vel and Ve2 are average vltages acrss capacitrs Cland C2, respectively, and K is a small gain f the neutral pint vltage cmpensatr. T avid a large X: term in the line current cmmand due t unbalance neutral-pint vltage, a limiter can be placed after the neutral-pint vltage cmpensatr. The resultant line-current cmmands are illustrated as, s sin(o) t) + "pc ssin (0) t - 2n /3) + "pc ss in(0) t + 2n /3) + "pc -(13 ) 225 hys(.jis,~ ),-,-,'',,----, , O Vcfc/2 Fig. 9. PWM Generatin 1 -Vdt 12 Based n the peratin states explained earlier there are three vltage levels vdcl2, 0 and -vdj2 generated in each cnverter leg. During the psitive half cycle, high vltage levels Vdd2 and lw vltage level 0 are generated n the AC terminal t neutral-pint vltage. During the negative half cycle, high vltage level Oand lw vltage level -vdj2 are generated n the AC side t cntrl the line current. The high vltage level is adpted t decrease the line current and lw vltage level is used t increase the line current.

6 let-uk nternatinal Cnference n nfrmatin and Cmmunicatin Technlgy in Electrical Sciences Fig. 10 shws the relatinship between the measured phase vltage, hysteresis current cmparatr and the PWM signals fr active switches in each cnverter leg. The PWM signals factive pwer switch at the cnverter leg A can be expressed as, >0 :--.,'".--_hị s.n S:':20rt 4. Simulatin Results Three-phase unidirectinal ACmC cnverter with pwer filctr crrectin was verified thrugh simulatin. A cmputer sftware package based n MATAB simulated the system behaviur. nput vltage 220 r.m.s Surce inductance 3m.H Output capacitance 2200~ Output vltage 400V DC Switching frequency 7.5 khz ine current T.H.D <5% Frequency 50HZ The Varius Simulated Wavefrms fthree phase AC-DC cnverter fr full lad are shwn belw :0 Fig. 10 Cntrl Strategy fr each Cnverter eg,1'1 S! t ~ Jr j ~ 111"1 ~ i! \, ;- U J~ UJ4 J Jb UJH Sa2=Sign(v sa ) hys(ai sa ) The PWM signals factive pwer switch at the cnverter leg B can be expressed as, Sbl =Sign(vsb) hys(aisb ) Timehecl Fig. 11. Simulatin utput fine Vltage and ine Cmrent at Cnverter eg A! The PWM signals factive pwer switch at the cnverter leg C can be expressed as, where,, ifm >h h ~i sx ys( sx) - { 0, if&sx <-h, ifv > 0 Sign(v ) = sx sx { 0, ifv sx < 0 ~isx =i*ax - iax gives the difference between actual and reference current. where i sx is the actual current i* sx is the reference current Fig. 12 Sillll1atin utput fine Vltage and ine Current at Cnverter e~ B tl, > l ' Fig. 13. Simulatin utput fine Vltage and ine Current at Cnverter eg C Sign(v sa ) =l-sign(v sa ) cnverter legs. x= a, b, c, where a,b and c are 226 Fig. 14. Simulatin utput fthree Phase ine Vltage and ine Current

7 An mprved High Perfrmance Three Phaseac-DC Bst Cnverter with nput Pwer Factr crrectin C~:f~i-.-i.~.-il-'iU.= -j '[(,t- tl..=t._..l... _.~. ; i~[~;i;-;~;j ~ ':(J::;~ n '... '-il ;';lj1-c. ld. -=-10 f ( ( OJ' 0 04 ( Of, 0 08 ( 1 C' 1;. 14 [, F. ~ Figure. 15 Simulatin utput fphase Vltages Vltag~ Arrss Caparhr, Vltag.. ArrS$ ("aparl1. :2.,,:1) T' ~~., TABEt PERFORMANCE COMPARSON BY VARYNG SUPPY VOTAGE AT CONSTANT OAD OF 40 OHMS VS Pin Put Pwer THD (V) (W) (W) Factr TABE 2 PERFORMANCE COMPARSON BY VARYNG OAD FOR CONSTANT SUPPY VOTAGE OF 180 V Fig.16. Simulatin utput fcapacitr Vltage Vcl and Vc t 100 ' Time (Sec) Fig. 17. Neutral Pint Vltage Cmpensatin ldlder lad Variatin R Pin Put Pwer Factr hm (W) (W) THD Table 1 and Table 2 shws the perfnnance cmparisns f the three phase AC-DC cnverter by varying the supply vltage and lad respectively. t's assumed that the pwer factr is clser t unity and ttal harmnic distrtin is als reduced (less than 5%) irrespective f the lad and line vltage variatins lou' O t DC Vltae.. l l! 0'-' (J 1 0,..' -_' Fig. 18 Simulatin utput foc utput Vltage at Full ad. eadcu...ftt Fig. 19 Simulatin utput fad Current 5. Cnclusins The cntrl scheme fr the prpsed three phase AC-DC cnverter has been discussed. The P cntrller is used t regulate the DC link vltage in the uter cntrl lp t maintain the DC bus vltage cnstant. The utput signal f the DC-link vltage cntrller is multiplied by a unit sinusidal wave in phase with supply vltage t btain the reference line current. The current errr between the reference line current and measured line current is given t the current cntrller in the inner cntrl lp t track the reference line current. The simulated results are discussed abve REFERENCES [1] EC : 'Electrmagnetic cmpatability. imits. imits frharmnic current emissins' (equipment input current r16a perphase), [2] Salmn, J.C. 'Techniques fr minimizing the input current distrtin f current- cntrlled single-phase bst rectifier', EEE Trans. Pwer Electrn., 1993,8, (4), pp [3] Salmn, C. 'Circuit tplgies fr single-phase vltage duble bst rectifier', EEE Trans. Pwer Electrn., 1993, 8, (4),pp [4] Wng, C., Mhan, N., and He, J. 'Adaptive phase cntrl fr three phases PWM AC t DC cnverters with cnstant switching frequency'. Prc. Cnf. PCC-Ykhama, Ykhama, Japan, 1993, pp

8 let-uk nternatinal Cnference n nfrmatin and Cmmunicatin Technlgy in Electrical Sciences [5] Kwn, B.-H, and Min, B.-D. 'A fully sftware-cntrlled PWM rectifier with current link', EEE Trans. nd. Electrn., 1993,40, (3),pp [6] Dawarde, M.S., Kanetkar, V.R., and Dubey, G. 'Three-phase switch mde rectifier with hysteresis current cntrl', EEE Trans. Pwer Electrn., 1996, 11, (3), pp [7] th, R., shizaka, K., and Grmarn, T. 'Three-phase vltage-surce cnverter with cntrlled DC fr the minimizatin f filter capacitance', leeprc.-b, 1990, 137, (5), pp [8] Wu, R., Dewan, S.B., and Siemn, G.R. 'A PWMAC-DC cnverter with fixed switching frequency', EEE Trans. nd. Appl., 1990,26, (5), pp [9] ai, J.S., and Peng, F.Z. 'Multilevel cnverters - a new breed fpwer cnverters', EEE Trans. nd. Appl., 1996,32, (3), [10] Sinha,G., and ip, T.A. 'A fur-level rectifier-inverter system fr drive applicatins', EEE nd. Appl. Mag., 1998,4, (1), pp [11] in, B.R., and Yang, T.Y. 'Single-phase half-bridge rectifier with pwer factr crrectin', lee Prc. - Elect. Pwer Appl., 2004, 151, (4), pp [12] Rdriguez, J., ai, 1.-S., and Peng, F.-Z. 'Multilevel inverters a survey f tplgies, cntrls and applicatins', EEE Trans. nd. Electrn., 2002,49, (4), pp