ECE 3829: Advanced Digital System Design with FPGAs A Term 2017

Transcription

1 ECE 3829: Advanced Digital System Design with FPGAs A Term 2017 Lab 2- VGA display and Light Sensr interface Reprt due at start f class Friday September 15 th Use the prvided Ambient Light Sensr mdule and a VGA Mnitr t create a light sensr mnitr n the Basys3 bard. This prject invlves the design f a number f interfaces t peripheral devices. It drives the VGA display using a cntrller, and reads the light sensr using an SPI interface. The lab invlves the use f multiple sequential circuits (cunters, shift registers, etc. but it is nt necessary t use state machines fr this lab), the Xilinx Cre Generatr (fr the MMCM), and use f existing IP (the Digilent VGA cntrller). There are multiple parts t this prject. T be successful will require a gd design and debugging apprach. Make simpler prjects that yu can test and debug separately and then cmbine them tgether. This lab (and reprt) can be cmpleted individually r with a lab partner (recmmended) it will be wrth 35% f yur curse lab grade. Lab Signff Deadline: during a lab sectin (during the week f September 11 th ) use the signff sheet that describes what yu have wrking AND bring alng yur Verilg listings fr the TAs t check (they will return these t yu t hand in with the reprt). The lab reprt is due in class n Friday September 15 th. Descriptin Preliminary: Mdify the simple seven segment display frm lab 1 t create a seven_seg mdule that can display a value frm "0000" t "FFFF" n the fur seven segment displays. The input t the mdule shuld be a 16-bit wide bus, with fur bits used t indicate the value t be displayed n each f the seven segments. Yu will als need a clck t cycle thrugh the fur digits. Make this a separate mdule yu will use this mdule in this and later prjects. Test this ut by using the slide-switches t enter varius numbers. Part 1: VGA display Use a MMCM t create a 25MHz clck required fr the VGA pixel clck. (see the MMCM tutrial fr hw t add this IP t yur design). Nte: nly cnnect the 100MHz FPGA clck t the MMCM (nthing else) Add a perid cnstraint t yur XDC t match the Basys3 bard 100MHz clck frequency. Use this 25MHz clck signal fr all the sequential lgic in this lab 1

2 Create a VGA display using the VGA cntrller prvided by Digilent (just the 640 by 480 versin) see infrmatin at end f this dc. Use the slide-switches t select and display the fllwing patterns Cmplete yellw display Hrizntal bars f alternating red and green clrs with each hrizntal bar 16 pixels high A black screen with a large white blck 64 pixels wide by 64 pixels high in the center f the screen A black screen with a large blck 64 pixels wide by 64 pixels high in the center f the screen with the clr determined by the value frm the light sensr (These shuld be relatively easy nce yu start wrking with the VGA cntrller prvided by Digilent dn t frget t include the blank signal) Part 2: Light Sensr Interface Create an SPI interface t be able t read the 8-bits f light sensr infrmatin frm the PmdALS mdule prvided. Use the 25MHz clck with a cunter and clck enable signal t generate the ADC SCLK at 1MHz Use a cunter r shift register t create the ADC CS signal. Verify the SCLK and CS signals are crrect with an scillscpe. Capture a new light sensr value every 100ms (10Hz) Use a shift register t read in the 8-bits f ADC data Display the light sensr value in hexadecimal n tw f the seven-segment displays (00 t apprx. FF). Display the same value n the ther tw seven-segment displays Capture an SPI ADC 16-bit transfer using an scillscpe (shw the CS, SCLK, and SDO signals n the scpe capture) and include this in yur reprt alng with a descriptin Nte: Fr all scpe pictures, preferably take a screen capture with a USB flash drive rather than a camera picture. Yu shuld be able t clearly see all the signals and the timebase. Extra credit Up t 10% lab bnus pints fr any gd imprvements r enhancements t yur design (must dem n bard and describe in yur reprt). Fr example make a system that can cunt bjects passing thrugh a light beam, r print ECE3829 n the VGA mnitr! 2

3 Reference Material Read the Seven Segment and VGA Prt sectin in the Nexys3 Reference Manual. Read the Digilent PmdALS Reference Manual and the Texas Instruments ADC081S021 ADC data sheet. PmdALS schematic and mdule frm Digilent CS, SDO, SCK example SPI transfer (with CSK at 1MHz) - bright sensr value (0xFB) 3

4 Ntes: Yur final design shuld cmbine parts 1, and 2. Print the sign-ff sheet and dem yur system during ne f yur lab sessins befre the deadline. Have yur printed Verilg surce files ready s they can be checked during the dem (dn t frget t includes names, descriptin, and cmments). Write a reprt including: an intrductin, a descriptin f yur design including gd blck diagrams shwing hw yu implemented the design, a sectin describing hw many flip-flps yur design used and why. Include part f the synthesis file that displays warnings explain these. Include a cnclusin describing any prblems r issues yu had and any lessns learned. Include yur signff sheet and yur surce files in an appendix. 4

5 Grading Guidelines [50 pts] Implementatin [50 pts] Design wrks n bard and meets requirements [20 pts] Surce Cde Verilg in Appendix Cde style and cmments (well-cmmented and tab-indented cde!) Use f case vs. if, spaghetti cde vs. structured, etc. Recgnizable implementatin f "standard" elements (state machines, cunters, shift registers, clck dividers, decders) Gd mdular design N latches r ther synthesis prblems [30 pts] Lab Reprt [5 pts] Brief Intrductin / Prblem Statement [15 pts] General verview f apprach t slutin and descriptin (include gd diagrams with descriptins) and scillscpe pictures with explanatins [5 pts] FPGA resurce usage (# flip-flps with explanatin) and listing and explanatin f warning messages (dn t cpy all the Xilinx reprts just the relevant sectins) [5 pts] Cnclusins Prblems faced in implementatin Slutins used t slve prblems Lessns learned frm the prject Suggestins fr further imprvements and extensins [10 pts] Extra pints Pssible extra pints fr gd additinal features r capabilities (need t dem n bard and include descriptin in reprt) 5

6 ECE 3829: Lab 2 sign-ff sheet Name: ECE Bx #: Name: ECE Bx #: Preliminary (nt required t be shwn) The seven segments display wrks (0000 t FFFF) Part 1 (VGA) Display shws a yellw screen Display shws hrizntal bars Display shws a white blck Display shws a clred blck (clr determined by light sensr value) Part 2 (Light Sensr) The light sensr displays the crrect value n the seven segment displays (00 t FF, dark t light) Value is displayed twice All cmbined All parts are cmbined int ne prject Extra Credit (describe) Example: cunt bjects 6