Data Sheet. HFBR-5984LZ RoHS Compliant, 200 MBd Low-Cost SBCON Transceivers in 2 x 5 SFF Package Style

Transcription

1 HFBR-5984LZ RHS Cmpliant, 200 MBd Lw-Cst SBCON Transceivers in 2 x 5 SFF Package Style Data Sheet Descriptin The HFBR-5984LZ transceiver frm Avag Technlgies prvides the system designer with a prduct t implement the SBCON specificatin and t be cmpatible with IBM ESCON architecture. This transceiver is supplied in the industry standard 2 x 5 SFF with an LC fiber cnnectr interface. Transmitter Sectins The transmitter sectin f the HFBR-5984LZ utilizes a 1300 nm InGaAsP LED. This LED is packaged in the ptical subassembly prtin f the transmitter sectin. It is driven by a custm silicn IC which cnverts differential PECL lgic signals, ECL referenced (shifted) t a +3.3 V supply, int an analg LED drive current. Features Fully RHS Cmpliant Multisurced 2 x 5 SFF package style with LC receptacle Single +3.3 V pwer supply Wave slder and aqueus wash prcess cmpatibility Manufactured in an ISO 9001 certified facility SBCON 200 MBd specificatin Applicatins Intercnnectin with IBM cmpatible prcessrs, directrs and channel attachment units Disk and tape drives Cmmunicatin cntrllers Data cmmunicatin equipment Lcal area netwrks Pint-t-pint cmmunicatin Receiver Sectins The receiver sectin f the HFBR-5984LZ utilizes an InGaAs PIN phtdide cupled t a custm silicn transimpedance preamplifier IC. It is packaged in the ptical subassembly prtin f the receiver. This PIN/preamplifier cmbinatin is cupled t a custm quantizer IC which prvides the final pulse shaping fr the lgic utput and the Signal Detect functin. The Data utput is differential. The Signal Detect utput is singleended. Bth Data and Signal Detect utputs are PECL cmpatible, ECL referenced (shifted) t a +3.3 V pwer supply. The receiver utputs, Data Out and Data Out Bar, are squelched at Signal Detect Deassert.

2 Package The verall package cncept fr the Avag Technlgies transceiver cnsists f three basic elements; the tw ptical subassemblies, an electrical subassembly, and the husing as illustrated in the blck diagram in Figure 1. The package utline drawing and pin ut are shwn in Figures 2 and 5. The details f this package utline and pin ut are cmpliant with the multisurce definitin f the 2 x 5 SFF. The lw prfile f the Avag Technlgies transceiver design cmplies with the maximum height allwed fr the LC cnnectr ver the entire length f the package. The ptical subassemblies utilize a high-vlume assembly prcess tgether with lw-cst lens elements which result in a cst-effective building blck. The electrical subassembly cnsists f a high vlume multilayer printed circuit bard n which the ICs and varius surface-munted passive circuit elements are attached. Bth the receiver and transmitter sectins include an internal shield fr the electrical and ptical subassemblies t ensure high immunity t external EMI fields. The slder psts f the Avag Technlgies design are islated frm the internal circuit f the transceiver. The transceiver is attached t a printed circuit bard with the ten signal pins and the tw slder psts which exit the bttm f the husing. The tw slder psts prvide the primary mechanical strength t withstand the lads impsed n the transceiver by mating with the LC cnnectred fiber cables. SUPPLY DATA OUT DATA OUT SIGNAL DETECT DATA IN DATA IN QUANTIZER IC LED DRIVER IC GROUND GROUND PIN PHOTODIODE PRE-AMPLIFIER SUBASSEMBLY LED OPTICAL SUBASSEMBLY LC RECEPTACLE SUPPLY Figure 1. Blck Diagram. 2

3 RX TX Munting Studs/Slder Psts Tp View RECEIVER SIGNAL GROUND RECEIVER POWER SUPPLY SIGNAL DETECT RECEIVER DATA OUT BAR RECEIVER DATA OUT TRANSMITTER DATA IN BAR TRANSMITTER DATA IN TRANSMITTER DISABLE (LASER BASED PRODUCTS ONLY) TRANSMITTER SIGNAL GROUND TRANSMITTER POWER SUPPLY Figure 2. Pin Out Diagram. Pin Descriptins: Pin 1 Receiver Signal Grund V EE RX: Directly cnnect this pin t the receiver grund plane. Pin 2 Receiver Pwer Supply RX: Prvide +3.3 V dc via the recmmended receiver pwer supply filter circuit. Lcate the pwer supply filter circuit as clse as pssible t the RX pin. Pin 3 Signal Detect SD: Nrmal ptical input levels t the receiver result in a lgic 1 utput. Lw ptical input levels t the receiver result in a fault cnditin indicated by a lgic 0 utput. This Signal Detect utput can be used t drive a PECL input n an upstream circuit, such as Signal Detect input r Lss f Signal-bar. Pin 4 Receiver Data Out Bar RD-: N internal terminatins are prvided. See recmmended circuit schematic. Pin 5 Receiver Data Out RD+: N internal terminatins are prvided. See recmmended circuit schematic. Pin 6 Transmitter Pwer Supply TX: Prvide +3.3 V dc via the recmmended transmitter pwer supply filter circuit. Lcate the pwer supply filter circuit as clse as pssible t the TX pin. Pin 7 Transmitter Signal Grund V EE TX: Directly cnnect this pin t the transmitter grund plane. Pin 8 Transmitter Disable T DIS : N internal cnnectin. Optinal feature fr laser based prducts nly. Pin 9 Transmitter Data In TD+: N internal terminatins are prvided. See recmmended circuit schematic. Pin 10 Transmitter Data In Bar TD-: N internal terminatins are prvided. See recmmended circuit schematic. Munting Studs/Slder Psts The munting studs are prvided fr transceiver mechanical attachment t the circuit bard. It is recmmended that the hles in the circuit bard be cnnected t chassis grund. 3

4 Applicatin Infrmatin The Applicatins Engineering grup is available t assist yu with the technical understanding and design trade-ffs assciated with these transceivers. Yu can cntact them thrugh yur Avag Technlgies sales representative. The fllwing infrmatin is prvided t answer sme f the mst cmmn questins abut the use f these parts. Transceiver Optical Pwer Budget versus Link Length Optical Pwer Budget (OPB) is the available ptical pwer fr a fiber ptic link t accmmdate fiber cable lsses plus lsses due t in-line cnnectrs, splices, ptical switches, and t prvide margin fr link aging and unplanned lsses due t cable plant recnfiguratin r repair. Avag Technlgies LED technlgy has prduced 1300 nm LED devices with lwer aging characteristics than nrmally assciated with these technlgies in the industry. The industry cnventin is 1.5 db aging fr 1300 nm LEDs. The 1300 nm Avag Technlgies LEDs are specified t experience less than 1 db f aging ver nrmal cmmercial equipment missin life perids. Cntact yur Avag Technlgies sales representative fr additinal details. Recmmended Handling Precautins Avag Technlgies recmmends that nrmal static precautins be taken in the handling and assembly f these transceivers t prevent damage which may be induced by electrstatic discharge (ESD). The HFBR-5984LZ series f transceivers meet MIL-STD-883C Methd Class 2 prducts. Care shuld be used t avid shrting the receiver data r signal detect utputs directly t grund withut prper current limiting impedance. PHY DEVICE TERMINATE AT TRANSCEIVER INPUTS TD- 100 Ω TD+ LVPECL TD- TD+ N/C V EE 1 µh C2 C3 10 µf V EE SD RD RD µh C1 100 Ω RD+ LVPECL RD- SD 82 Ω Nte: C1 = C2 = C3 = 10 nf r 100 nf TERMINATE AT DEVICE INPUTS Figure 3. Recmmended Decupling and Terminatin Circuits 4

5 Slder and Wash Prcess Cmpatibility The transceivers are delivered with prtective prcess plugs inserted int the LC receptacle. This prcess plug prtects the ptical subassemblies during wave slder and aqueus wash prcessing and acts as a dust cver during shipping. These transceivers are cmpatible with either industry standard wave r hand slder prcesses. Shipping Cntainer The transceiver is packaged in a shipping cntainer designed t prtect it frm mechanical and ESD damage during shipment r strage. Bard Layut - Decupling Circuit, Grund Planes and Terminatin Circuits It is imprtant t take care in the layut f yur circuit bard t achieve ptimum perfrmance frm these transceivers. Figure 4 prvides a gd example f a schematic fr a pwer supply decupling circuit that wrks well with these parts. It is further recmmended that a cntiguus grund plane be prvided in the circuit bard directly under the transceiver t prvide a lw inductance grund fr signal return current. This recmmendatin is in keeping with gd high frequency bard layut practices. Figures 3 and 4 shw tw recmmended terminatin schemes. TERMINATE AT TRANSCEIVER INPUTS PHY DEVICE 10 nf TD- TD+ LVPECL Ω 82 Ω TD- TD+ N/C V EE V EE SD RD RD µh C2 1 µh C1 10 µf C3 10 nf RD+ RD- LVPECL 10 nf 82 Ω 82 Ω SD 82 Ω Nte: C1 = C2 = C3 = 10 nf r 100 nf TERMINATE AT DEVICE INPUTS Figure 4. Alternative Terminatin Circuits 5

6 Bard Layut - Hle Pattern The Avag Technlgies transceiver cmplies with the circuit bard Cmmn Transceiver Ftprint hle pattern defined in the riginal multisurce annuncement which defined the 2 x 5 SFF package style. This drawing is reprduced in Figure 6 with the additin f ANSI Y14.5M cmpliant dimensining t be used as a guide in the mechanical layut f yur circuit bard. Figure 6 illustrates the recmmended panel pening and the psitin f the circuit bard with respect t this panel. Bard Layut - Art Wrk The Applicatins Engineering grup has develped a Gerber file artwrk fr a multilayer printed circuit bard layut incrprating the recmmendatins abve. Cntact yur lcal Avag Technlgies sales representative fr details. Figure 5. Package Outline Drawing 6

7 Figure 6. Recmmended Bard Layut Hle Pattern and Panel Opening Electrstatic Discharge (ESD) There are tw design cases in which immunity t ESD damage is imprtant. The first case is during handling f the transceiver prir t munting it n the circuit bard. It is imprtant t use nrmal ESD handling precautins fr ESD sensitive devices. These pre-cautins include using grunded wrist straps, wrk benches, and flr mats in ESD cntrlled areas. The secnd case t cnsider is static discharges t the exterir f the equipment chassis cntaining the transceiver parts. T the extent that the LC cnnectr is expsed t the utside f the equipment chassis it may be subject t whatever ESD system level test criteria that the equipment is intended t meet. 7

8 Regulatry Cmpliance These transceiver prducts are intended t enable cmmercial system designers t develp equipment that cmplies with the varius internatinal regulatins gverning certificatin f Infrmatin Technlgy Equipment. See the Regulatry Cmpliance Table fr details. Additinal infrmatin is available frm yur Avag Technlgies sales representative. Electrmagnetic Interference (EMI) Mst equipment designs utilizing this high speed transceiver frm Avag Technlgies will be required t meet the requirements f FCC in the United States, CENELEC EN55022 (CISPR 22) in Eurpe and VCCI in Japan. This prduct is suitable fr use in designs ranging frm a desktp cmputer with a single transceiver t a cncentratr r switch prduct with a large number f transceivers. Immunity Equipment utilizing these transceivers will be subject t radi-frequency electrmagnetic fields in sme envirnments. These transceivers have a high immunity t such fields. Fr additinal infrmatin regarding EMI, susceptibility, ESD and cnducted nise testing prcedures and results. Refer t Applicatin Nte 1166 Minimizing Radiated Emissins f High-Speed Data Cmmunicatins Systems. Transceiver Reliability and Perfrmance Qualificatin Data The 2 x 5 SFF transceivers have passed Avag Technlgies reliability and perfrmance qualificatin testing and are underging nging quality and reliability mnitring. Details are available frm yur Avag Technlgies sales representative. These transceivers are manufactured at the Avag Technlgies Singapre lcatin which is an ISO 9001 certified facility. Ordering Infrmatin The HFBR-5984LZ 1300 nm prduct is available fr prductin rders thrugh the Avag Technlgies Cmpnent There are tw design cases in which immunity t Field Sales Offices and Authrized Distributrs wrld wide. Fr technical infrmatin regarding this prduct, please visit Avag Technlgies website at Use the quick search feature t search fr this part number. Yu may als cntact Avag Technlgies Custmer Respnse Center. Applicatins Supprt Materials Cntact yur lcal Avag Technlgies Cmpnent Field Sales Office fr infrmatin n hw t btain PCB layuts and evaluatin bards fr the 2 x 5 SFF transceivers. Regulatry Cmpliance Table Feature Test Methd Perfrmance Electrstatic Discharge (ESD) t the Electrical Pins Electrstatic Discharge (ESD) t the LC Receptacle JEDEC/EIA JESD22-A114-A and MIL-STD-883 Methd 3015 (Human Bdy Mdel) Variatin f IEC Meets Class 2 (2000 t 3999 Vlts). Withstand up t 3000 V applied between electrical pins. Typically withstand at least 25 kv withut damage when the LC Cnnectr Receptacle is cntacted by a Human Bdy Mdel prbe. Electrmagnetic Interference (EMI) FCC Class B CENELEC CEN55022 VCCI Class 2 Transceivers typically prvide a 10 db margin t the nted standard limits when tested at a certified test range with the transceiver munted t a circuit card withut a chassis enclsure. Immunity Variatin f IEC Typically shw n measurable effect frm a 10 V/m field swept frm 80 t 450 MHz applied t the transceiver when munted t a circuit card withut a chassis enclsure. Eye Safety AEL Class 1 EN (+A11) Cmpliant per Avag Technlgies testing under single fault cnditins. TUV Certificatin #: E UL File #: E

9 Abslute Maximum Ratings Stresses in excess f the abslute maximum ratings can cause catastrphic damage t the device. Limits apply t each parameter in islatin, all ther parameters having values within the recmmended perating cnditins. It shuld nt be assumed that limiting values f mre than ne parameter can be applied t the prduct at the same time. Expsure t the abslute maximum ratings fr extended perids can adversely affect device reliability. Parameter Symbl Minimum Typical Maximum Unit Reference Strage Temperature T S C Lead Sldering Temperature T SOLD +260 C Lead Sldering Time t SOLD 10 Sec. Supply Vltage V Data Input Vltage V I -0.5 V Differential Input Vltage V D 2.0 V Nte 1 Output Current I O 50 ma Recmmended Operating Cnditins Parameter Symbl Minimum Typical Maximum Unit Reference Case Operating Temperature T C C Supply Vltage V Data Input Vltage - Lw V IL V Data Input Vltage - High V IH V Data and Signal Detect Output Lad R L 50 W Nte 2 PCB Assembly Prcess Cmpatibility Parameter Symbl Minimum Typical Maximum Unit Reference Hand Lead Sldering Temperature Time Wave Sldering and Aqueus Wash Temperature Time t slder +260 t time 10 t slder t time 10 sec +260 C Aqueus Wash Pressure 110 psi C sec 1 1 Transmitter Electrical Characteristics (T C = -20 C t +85 C, = 2.97 V t 3.63 V) Parameter Symbl Minimum Typical Maximum Unit Reference Supply Current I CC ma Nte 3 Pwer Dissipatin P DISS W Nte 4 Data Input Current - Lw I IL µa Data Input Current - High I IH µa 9

10 Receiver Electrical Characteristics (T C = -20 C t +85 C, = 2.97 V t 3.63 V) Parameter Symbl Minimum Typical Maximum Unit Reference Supply Current I CC ma Nte 5 Pwer Dissipatin P DISS W Nte 4 Data Output Vltage - Lw V OL V Nte 6 Data Output Vltage - High V OH V Nte 6 Data Output Rise Time t r ns Nte 7 Data Output Fall Time t f ns Nte 7 Signal Detect Output Vltage - Lw V OL V Nte 6 Signal Detect Output Vltage - High V OH V Nte 6 Signal Detect Output Rise Time t r ns Nte 7 Signal Detect Output Fall Time t f ns Nte 7 Transmitter Optical Characteristics (T C = -20 C t +85 C, = 2.97 V t 3.63 V) Parameter Symbl Minimum Typical Maximum Unit Reference Output Optical Pwer BOL 62.5/125 µm, NA = Fiber EOL P O dbm avg. Nte 8 Optical Extinctin Rati 8 db Nte 9 Center Wavelength l c nm Figure 7 Spectral Width - FWHM Dl nm Nte 10 Figure 7 Optical Rise Time t r ns Nte 11, 12 Figure 7 Optical Fall Time t f ns Nte 11, 12 Figure 7 Ttal Jitter Tj ns Nte 13 Receiver Optical Characteristics (T C = -20 C t +85 C, = 2.97 V t 3.63 V) Parameter Symbl Minimum Typical Maximum Unit Reference Input Optical Pwer Minimum at Windw Edge P IN Min. (W) Pin Min (C) +1 db dbm avg. Nte 14 Figure 8 Input Optical Pwer Minimum at Eye Center P IN Min. (C) -29 dbm avg. Nte 15 Figure 8 Input Optical Pwer Maximum P IN Max. -14 dbm avg. Nte 14 Operating Wavelength l nm Systematic Jitter SJ ns Nte 16 Eyewidth t ew 1.4 ns Nte 17 Signal Detect - Asserted P A dbm avg. Nte 18 Signal Detect - Deasserted P D dbm avg. Nte 19 Signal Detect - Hysteresis P A - P D db Signal Detect Assert Time (ff t n) t A µs Nte 20 Signal Detect Deassert Time (n t ff) t D µs Nte 21 10

11 Ntes: 1. This is the maximum vltage that can be applied acrss the Differential Transmitter Data Inputs t prevent damage t the input ESD prtectin circuit. 2. The utputs are terminated with 50 W cnnected t 2 V. 3. The pwer supply current needed t perate the transmitter is prvided t differential ECL circuitry. This circuitry maintains a nearly cnstant current flw frm the pwer supply. Cnstant current peratin helps t prevent unwanted electrical nise frm being generated and cnducted r emitted t neighbring circuitry. 4. The pwer dissipatin value is the pwer dissipated in the receiver itself. Pwer dissipatin is calculated as the sum f the prducts f supply vltage and currents, minus the sum f the prducts f the utput vltages and currents. 5. This value is measured with the utputs terminated int 50 W cnnected t 2 V and an Input Optical Pwer Level f 14.5 dbm average. 6. This value is measured with respect t with the utput terminated int 50 W cnnected t 2 V. 7. The utput rise time and fall times are measured between 20% and 80% levels with the utput cnnected t 2 V thrugh 50 W. 8. These ptical pwer values are measured with the fllwing cnditins: The Beginning f Life (BOL) t the End f Life (EOL) ptical pwer degradatin is assumed t be 1.5 db per the industry cnventin fr lng wavelength LEDs. The actual degradatin bserved in nrmal cmmercial envirnments will be <1.0 db with Avag Technlgies 1300 nm LED prducts. Over the specified perating vltage and temperature ranges. Input Signal: 1010 data pattern, 200 Mb/s NRZ cde. λ - TRANSMITTER OUTPUT OPTICAL SPECTRAL WIDTH (FWHM) - nm t r/f TRANSMITTER OUTPUT OPTICAL RISE/FALL TIMES ns λ C TRANSMITTER OUTPUT OPTICAL RISE/FALL TIMES ns 3.0 HFBR-5930 TRANSMITTER TEST RESULTS OF λ C, λ AND t r/f ARE CORRELATED AND COMPLY WITH THE ALLOWED SPECTRAL WIDTH AS A FUNCTION OF CENTER WAVELENGTH FOR VARIOUS RISE AND FALL TIMES. Figure 7. Transmitter Output Optical Spectral Width (FWHM) vs. Transmitter Output Optical Center Wavelength and Rise/Fall Times. 9. The Extinctin Rati is a measure f the mdulatin depth f the ptical signal. The data 0 utput ptical pwer is cmpared t the data 1 peak utput ptical and expressed in decibels. With the transmitter driven by a HALT Line State (12.5 Mhz square-wave) signal, the average ptical pwer is measured. The data 1 peak pwer is then calculated by adding 3 db t the measured average ptical pwer. The data 0 utput ptical pwer is fund by measuring the ptical pwer when the transmitter is driven by a lgic 0 input. The Extinctin Rati is the rati f the ptical pwer at the 0 level cmpared t the ptical pwer at the 1 level expressed in decibels. 10. Frm an assumed Gaussian-shaped wavelength distributin, the relatinship between FWHM and RMS values fr Spectral Width is 2.35 x RMS = FWHM. 11. Input cnditins: 100 MHz, square wave signal, input vltages are in the range specified fr V IL and V IH. 12. Measured with electrical input signal rise and fall time f 0.35 t 1.3 ns (20-80%) at the transmitter input pins. Optical utput rise and fall times are measured between 20% and 80% levels. 13. Transmitter Systematic Jitter is equal t the sum f Duty Cycle Distrtin (DCD) and Data Dependent Jitter (DDJ). DCD is equivalent t Pulse- Width Distrtin (PWD). Systematic Jitter is measured at the 50% signal level with 200 MBd, PRBS electrical input data pattern. 14. This specificatin is intended t indicate the perfrmance f the receiver sectin f the transceiver when Input Optical Pwer signal characteristics are present per the fllwing cnditins. The Input Optical Pwer dynamic range frm the minimum level (with a windw time-width) t the maximum level is the range ver which the receiver is guaranteed t prvide utput data with a Bit Errr Rati (BER) better than r equal t At the Beginning f Life (BOL). Over the specified perating temperature and vltage ranges. Receiver data windw time-width is 1.4 ns r greater and centered at mid-symbl. Input signal is 200 MBd, Pseud Randm-Bit-Stream data pattern. Transmitter crss-talk effects have been included in Receiver sensitivity. Transmitter shuld be running at 50% duty cycle (nminal) between Mb/s, while Receiver sensitivity is measured. 15. All cnditins f nte 14 apply except that the measurement is made at the center f the symbl with n windw time-width and with a BER better than r equal t The receiver systematic jitter specificatin applies t ptical pwers between 14.5 dbm avg. t 27.0 dbm avg. at the receiver. Receiver Systematic Jitter is equal t the sum f Duty Cycle Distrtin (DCD) and Data Dependent Jitter (DDJ). DCD is equivalent t Pulse-Width Distrtin (PWD). Systematic Jitter is measured at the 50% signal level with 200 MBd, PRBS electrical utput data pattern. 17. Eye-width specified defines the minimum clck time-psitin range, centered arund the center f the 5 ns baud interval, at which the BER must be r better. Test data pattern is PRBS The typical change in input ptical pwer t pen the eye t 1.4 nsec frm a clsed eye is less than 1.0 db. 18. Status Flag switching threshlds: Directin f decreasing ptical pwer: If Pwer > 36.0 dbm avg., then SF = 1 (high) If Pwer < 45.0 dbm avg., then SF = 0 (lw) Directin f increasing ptical pwer: If Pwer < 45.5 dbm avg., then SF = 0 (lw) If Pwer > 35.5 dbm avg., then SF = 1 (high) 19. Status Flag Hysteresis is the difference in lw-t-high and high-t-lw switching threshlds. Threshlds must lie within ptical pwer limits specified. The Hysteresis is desired t avid Status Flag chatter when the ptical input is near the threshld. 20. The Status Flag utput shall be asserted within 500 µs after a step increase f the Input Optical Pwer. The step will be frm a lw Input Optical Pwer < 45.5 dbm avg., t > 35.5 dbm avg. 21. Status Flag utput shall be de-asserted within 500 µs after a step decrease in the Input Optical Pwer. The Step will be frm a high Input Optical Pwer > 36.0 dbm avg. t < 45.0 dbm avg. RELATIVE INPUT OPTICAL POWER (db) EYE SAMPLING TIME POSITION (ns) CONDITIONS: 1. T A = +25 C 2. = 3.3 V dc 3. INPUT OPTICAL RISE /FALL TIMES = 1.0/1.2 ns. 4. INPUT OPTICAL POWER IS NORMALIZED TO CENTER OF DATA SYMBOL. 5. NOTE 15 AND 16 APPLY. Figure 8. Relative Input Optical Pwer vs. Eye Sampling Time Psitin. 11

12 Fr prduct infrmatin and a cmplete list f distributrs, please g t ur web site: Avag, Avag Technlgies, and the A lg are trademarks f Avag Technlgies, Pte. in the United States and ther cuntries. Data subject t change. Cpyright 2006 Avag Technlgies Pte. All rights reserved EN - February 1, 2006