DC-DC CONVERTERS VIA MATLAB/SIMULINK

Transcription

1 Internatinal Jurnal f Scientific & Engineering Research, Vlume 5, Issue 0, Octber-204 ISSN DC-DC CONVERTERS VIA MATLAB/SIMULINK 906 Ali Khajezadeh; Akbar Ahmadipur, Mahdi Shamsadin Mtlagh Abstract the design f pwer electrnic cnverter circuit with the use f clsed lp scheme needs mdeling and then simulating the cnverter using the mdeled equatins. An attempt has been made in this paper t simulate all basic nn-islated pwer cnverters. This can easily be dne with the help f state equatins and MATLAB/SIMULINK as a tl fr simulatin f thse state equatins. S that these mdels can be readily used fr any clse lp design. Index Terms Switching cnverters, MATLAB/SIMULINK, system mdeling, cascade cntrl, subsystems Intrductin MATLAB/SIMULINK sftware package can be advantageusly used t simulate pwer cnverters. This study aims at develpment f the mdels fr all basic cnverters and studying its pen lp respnse, s these mdels can be used in case f design f any clse lp scheme. Als as a cmplete exercise a clsed scheme case has been studied using cascaded cntrl fr a bst cnverter. Cntrller design fr any system needs knwledge abut system behavir. Usually this invlves a mathematical descriptin f the relatin amng inputs t the prcess, state variables, and utput. This descriptin in the frm f mathematical equatins which describe behavir f the system (prcess is called mdel f the system. This paper describes an efficient methd t learn, analyze and Ali Khajezadeh, department f electrical engineering, kerman branch,islamic azad university, kerman, iran; alikhajezadeh@yah.cm Akbar Ahmadipur, department f electrical engineering, kerman branch, islamic azad university, kerman, iran; nadali300@gmail.cm Mahdi Shamsadin Mtlagh, department f electrical engineering, kerman branch, islamic azad university, kerman, iran; mahdikhan92@yah.cm IJSER 204 simulatin f pwer electrnic cnverters, using system level nnlinear, and switched state- space mdels. The 2 Simulink Mdel Cnstructin f DC- DC Switching Cnverter System mdeling is prbably the mst imprtant phase in any frm f system cntrl design wrk. The chice f a circuit mdel depends upn the bjectives f the simulatin. If the gal is t predict the behavir f a circuit befre it is built. A gd system mdel prvides a designer with valuable infrmatin abut the system dynamics. Due t the difficulty invlved in slving general nnlinear equatins, all the gverning equatins will be put tgether in blck diagram frm and then simulated using Matlab s Simulink prgram. Simulink will slve these nnlinear equatins numerically, and prvide a simulated respnse f the system dynamics. A. Mdeling Prcedure T btain a nnlinear mdel fr pwer electrnic circuits, ne needs t apply Kirchhff's circuit laws. T avid the use f cmplex mathematics, the electrical and semicnductr devices must be represented as ideal cmpnents (zer ON vltages, zer OFF currents, zer switching times.

2 Internatinal Jurnal f Scientific & Engineering Research, Vlume 5, Issue 0, Octber-204 ISSN Therefre, auxiliary binary variables can be used t determine the state f the switches. It must be ensure that the equatins btained by the use f Kirchhff's laws shuld include all the permissible states due t pwer semicnductr devices being ON r OFF. The steps t btain a system-level mdeling and simulatin f pwer electrnic cnverters are listed belw. Determine the state variables f the pwer circuit in rder t write its switched state-space mdel, e.g., inductr current and capacitr vltage. 2 Assign integer variables t the pwer semicnductr (r t each switching cell ON and OFF states. 3 Determine the cnditins gverning the states f the pwer semicnductrs r the switching cell. 4 Assume the main perating mdes f the cnverter (cntinuus r discntinuus cnductin r bth r the mdes needed t describe all the pssible circuit peratinal mdes. Then, apply Kirchhff's laws and cmbine all the required stages int a switched state-space mdel, which is the desired systemlevel mdel. 5 Write this mdel in the integral frm, r transfrm the differential frm t include the semicnductrs lgical variables in the cntrl vectr: the cnverter will be represented by a set f nnlinear differential equatins. 6 Implement the derived equatins with "SIMULINK" blcks (pen lp system simulatin is then pssible t check the btained mdel. 7 Use the btained switched space-state mdel t design linear r nnlinear cntrllers fr the pwer cnverter. 8 Perfrm clsed-lp simulatins and evaluate cnverter perfrmance. 9 The algrithm fr slving the differential equatins and the step size shuld be chsen befre running any simulatin. The tw last steps are t btain clsed-lp simulatins [2]. 3 Simulatin Open-Lp Mdeling f DC-DC Cnverters A. Buck Cnverter Mdeling The buck cnverter with ideal switching devices will be cnsidered here which is perating with the switching perid f T and duty cycle D Fig., []. The state equatins crrespnding t the cnverter in cntinuus cnductin mde (CCM can be easily understd by applying Kirchhff's vltage law n the lp cntaining the inductr and Kirchhff's current law n the nde with the capacitr branch cnnected t it. When the ideal switch is ON, the dynamics f the inductr current i ( t and the capacitr vltage v ( t are given by, dil ( Vin v dt L, 0 t dt, Q : ON dv v ( il dt C R and when the switch is OFF are presented by, dil ( v dt L, dt t T, Q : OFF dv v ( il dt C R C L IJSER 204

3 Internatinal Jurnal f Scientific & Engineering Research, Vlume 5, Issue 0, Octber-204 ISSN Fig 2 Open-lp mdeling f Buck DC-DC cnverters dil ( Vin v dt L, dv v ( il dt C R dt t T, Q : OFF Fig. DC-DC Buck Cnverter These equatins are implemented in Simulink as shwn in Fig. 2 using multipliers, summing blcks, and gain blcks, and subsequently fed int tw integratrs t btain the states i ( t and vc ( t [2][3] [4]. B. Bst Cnverter Mdeling The bst cnverter f Fig. 3 with a switching perid f T and a duty cycle f D is given. Again, assuming cntinuus cnductin mde f peratin, the state space equatins when the main switch is ON are shwn by, []. dil ( Vin dt L, 0 t dt, Q : ON dv v ( dt C R L Fig. 4 shws These equatins in Simulink using multipliers, summing blcks, and gain blcks, and subsequently fed int tw integratrs t btain the states i ( t and v ( C t, [2][3][4] Fig. 3 DC-DC Bst Cnverter Fig. 4 Open-lp mdeling f Bst DC-DC cnverters L and when the switch is OFF IJSER 204

4 Internatinal Jurnal f Scientific & Engineering Research, Vlume 5, Issue 0, Octber-204 ISSN C. Buck-Bst Cnverter Mdeling In Fig. 5 a DC-DC buck-bst cnverter is shwn. The switching perid is T and the duty cycle is D. Assuming cntinuus cnductin mde f peratin, when the switch is ON, the state space equatins are given by, [] dil ( Vin dt L, 0 t dt, Q : ON dv v ( dt C R and when the switch is OFF dil ( v dt L, dt t T, Q : OFF dv v ( il dt C R Fig. 5 DC-DC Buck-Bst Cnverter These equatins are implemented in Simulink as shwn in Fig. 6 using multipliers, summing blcks, and gain blcks, and subsequently fed int tw integratrs t btain the states i ( t and vc ( t, [2] [3] [4]. L The Cuk cnverter f Fig. 7 with switching perid f T and duty cycle f D is cnsidered. During the cntinuus cnductin mde f peratin, the state space equatins are as fllws, [] dil ( vin dt L dvc ( il2 dt C2, 0 t dt, Q : ON di ( v L2 v c dt L2 dv v ( il2 dt C R When the switch is OFF the state space equatins are represented by dil ( vin v dt L dvc ( il dt C2, dt t T, Q : OFF dil2 ( v dt L2 dv v ( il2 dt C R Fig.7 DC-DC Cuk cnverter D. Cuk Cnverter Mdeling Fig. 6 Open-lp f Buck-Bst DC-DC Cnverters these equatins are implemented in Simulink as shwn in Fig. 8 using multipliers, summing blcks, and gain blcks, and subsequently fed int tw integratrs t btain the states il( t and vc ( t, [2] [3] [4]. IJSER 204

5 Internatinal Jurnal f Scientific & Engineering Research, Vlume 5, Issue 0, Octber-204 ISSN Fig. 8 Open-lp mdeling f Cuk DC-DC cnverters E. Subsystems Each f the pwer electrnic mdels represents subsystems within the simulatin envirnment. These blcks have been develped s they can be intercnnected in a cnsistent and simple manner fr the cnstructin f cmplex systems. The subsystems are masked, meaning that the user interface displays nly the cmplete subsystem, and user prmpts gather parameters fr the entire subsystem. Relevant parameters can be set by duble-clicking a muse r pinter n each subsystem blck, then entering the apprpriate values in the resulting dialgue windw [4]. T facilitate the subsequent simulatin analysis and feedback cntrller verificatin, the pulse-width-mdulatin signal t cntrl the ideal switch can als be built int the masked subsystem Fig. 9(a and Fig. 9(b. Fr each cnverter t verity it s wrking in pen lp cnfiguratin trigger pulses have been derived using a repeating sequence generatr and duty cycle blck. Functin blck cmpares the duty cycle and saw tth frm repeating sequencederived trigger pulses are cnnected as an input t the switch cntrl. Hence inputs fr the masked subsystem are duty rati and input vltage, and the utputs are chsen t be inductr current, capacitr vltage, and utput vltage. When duble-clicking the pinter n the masked subsystem, ne enters parameter values f the switching cnverter circuit in a dialgue windw. The intuitive signal flw interface in SIMULINK makes this mathematical mdel and its crrespnding masked subsystem very easy t create. 4 Simulatin Clsed-Lp f DC-DC Cnverters Using Cascaded Cntrl The simulatin mdel fr cascaded cntrl f DC-DC switching cnverters is build using the abve-mentined steps is as shwn in Fig. 0. The DC-DC buck, bst, buck-bst, and Cuk cnverters was previusly designed, and simulated n digital cmputer using Matlab package with the parameters given in Table, and Table 2. Inductr current and capacitr vltage fr IJSER 204

6 Internatinal Jurnal f Scientific & Engineering Research, Vlume 5, Issue 0, Octber-204 ISSN pen lp simulatin f all cnverters are as shwn in Fig. (a, b, c, and d. Table Buck, Bst, and Buck-Bst cnverters parameters V L C R f in V Table 2 Cuk cnverter parameters Vin L L 2 C C f R 2 V 50 V 75 mh 400 F 9 50 KHz V 80 mh 22 mh 45 F 00 F 50 8 KHz 24 V Results f Clsed lp using a cascaded cntrl scheme fr a bst cnverter is shwn in Fig. 2(a. Here the utput vltage rises up t 2.3V (6.5% fr the step variatin f lad frm 0 t 3 (30%. The utput vltage resumes its reference value (f 20V within 5ms after the transient variatin f lad. As per fig 2(b, fr a step change at the input vltage frm 0V t8 V (80% (at 0.5 Sec instant, a satisfactry perfrmance is btained in the utput vltage which has a rise up t 22.8V (4%, but it is quickly drpped t its set value (20V within 6 ms. Simulatin results verify that the cntrl scheme in this sectin gives stable peratin f the pwer supply. The utput vltage and inductr current can return t the steady state even when it is affected by line and lad variatin. 5 Cnclusins Fig. 9(a Subsystem fr Buck, Bst and Buck-Bst cnverters Fig. 9(b Subsystem fr Cuk cnverters This paper analysis nnlinear, switched, statespace mdels fr buck, bst, buck-bst, and Cuk cnverters. The simulatin envirnment MATLAB/SIMULINK is quite suitable t design the mdeling circuit, and t learn the dynamic behavir f different cnverter structures in pen lp. The simulatin mdel in MATLAB/SIMULINK fr the bst cnverter is build fr clse lp. The simulatin results btained, shw that the utput vltage and inductr current can return t steady state even when it is affected by input vltage and lad variatin, with a very small ver sht and settling time. IJSER 204

7 Internatinal Jurnal f Scientific & Engineering Research, Vlume 5, Issue 0, Octber-204 ISSN Fig.0 Simulink blck diagram representing clse lp Scheme f Bst cnverter using cascaded cntrl Ripple (peak-t-peak = 0.43% 6 References [] A. Capel, D. O Sullivan, J. C. Marpinard, High-Pwer Cnditining fr Space Applicatins, Prc. f the IEEE, vl. 76, n. 4, pp , Apr [2] T. W. Martin, S. S. Ang, Digital cntrl fr switching cnverters, Prc. f IEEE Int. Symp. n Industrial Electrnics, ISIE'95, vl. 2, pp , July 995. [3] C. Barillt, J. P. Calvel, P. Pirt, Ttal dse and heavy ins evaluatin f UC806 pulse width mdulatr frm Unitrde, Prc. f IEEE Radiatin Effects Data Wrkshp, NSREC, pp , July 995. [4] P. C. Adell, R. D. Schrimpf, B. K. Chi, W. T. Hlman, J. P. Attwd, C. R. Cirba, K. F. Gallway, Ttal-Dse and Single-Event Effects in Switching DC/DC Pwer cnverter, IEEE Trans. Nucl. Sci., vl. 49, n. 6, pp , Dec [5] M. Bellat, M. Ceschia, M. Menichelli, M. Papi, J. Wyss, A. Paccagnella, In beam testing f SRAM-based FPGA s, Prc. f Radiatin and Its Effects n Cmpnents and Systems cnference, RADECS, pp , Sept [6] C. Carmichael, E. Fuller, P. Blain, M. Caffrey, SEU Mitigatin Techniques fr IJSER 204

8 Internatinal Jurnal f Scientific & Engineering Research, Vlume 5, Issue 0, Octber-204 ISSN Virtex FPGAs in Space Applicatins, Prc. f 2 nd MAPLD Internatinal Cnference, Sept [7] J. Rh, S. D. Lee, S. Park, Digital PWM cntrller fr DC-DC cnverters with minimum analgue circuits, Electrnics letters, vl. 39, n. 9, pp , Sept [8] Mahdi Mzaffari Legha, "Determinatin f exhaustin and junctin f in distributin netwrk and its lss maximum, due t gegraphical cnditin", MS.c Thesis; Islamic Azad University, Saveh Branch, Markazi Prvince, Iran; pp. -300, Aug 20. [9] J.Mahdavi, A.Emadi, H.A.Tliyat, Applicatin f State Space Averaging Methd t Sliding Mde Cntrl f PWM DC/DC Cnverters, IEEE Industry Applicatins Sciety Octber 997 [0] Mahdi Mzaffari Legha, Ruhllah Abdllahzadeh, Ardalan Zargar, Mstafa Shadfar. Effective methd fr ptimal allcatin f distributed generatin units in radial electric pwer systems by genetic algrithm and imperialist cmpetitive algrithm, Internatinal Jurnal n Technical and Physical Prblems f Engineering (IJTPE, Issue 5, Vl. 5, N. 2, pp , June 203. [] Mahdi Mzaffari Legha, Mein khsravi, Mhammad Hssein Armand, Mahdiyeh Azh,, Optimizatin f Lcatin and Capacity DGs Using HPSO Apprach Case Study n the Electrical Distributin Netwrk f nrth Kerman Prvince, Middle-East Jurnal f Scientific Research, pp , 203. [2] Mahdi Mzaffari Legha,; Optimal Cnductr Selectin f Radial Distributin Netwrks Using GA Methd CIRED Reginal Iran, Tehran, 3-4 Jan 203; Paper N: 2-F [3] Mahdi Mzaffari Legha, Farzaneh Ostvar, Analysis and Recnductring f Overhead Cnductrs with Cnsidering aging fr Radial Distributin Systems Using Imperialist cmpetitive Algrithm, Internatinal Jurnal f Pure and Applied Sciences and Technlgy, Vl. 20, N., January 204, pp. -8. [4] Mahdi Mzaffari Legha, Human Gadari,, Technical and Ecnmical Evaluatin f Slar Plant fr Electricity Supply Anar City Residential Custmers, Middle-East Jurnal f Scientific Research, pp , 203. [5] Mahdi Mzaffari Legha, Mhammad Mhammadi; Aging Analysis and Recnductring f Overhead Cnductrs fr Radial Distributin Systems Using Genetic Algrithm; Jurnal f Electrical Engineering & Technlgy (JEET; pp. -8, 204. [6] Juing-Huei Su, Jiann-Jng Chen, Dng- Shiuh Wu, Learning Feedback Cntrller Design f Switching Cnverters Via MATLAB/SIMULINK, IEEE Transactins n Educatin, vl. 45, Nvember 2002 [7] Mahdi Mzaffari Legha,; Optimal Cnductr Selectin f Radial Distributin Netwrks Using GA Methd CIRED Reginal Iran, Tehran, 3-4 Jan 203; Paper N: 2-F [8] Mahdi Mzaffari Legha, Hassan Javaheri, Mhammad Mzaffari Legha, Optimal Cnductr Selectin in Radial Distributin Systems fr Prductivity Imprvement Using Genetic Algrithm Iraqi Jurnal fr Electrical and Electrnic Engineering (IJEEE, Vl.9 N., 203, [9] Juing-Huei Su, Jiann-Jng Chen, Dng- Shiuh Wu, Learning Feedback Cntrller Design f Switching Cnverters Via MATLAB/SIMULINK, IEEE Transactins n Educatin, vl. 45, Nvember [20] Mahdi Mzaffari Legha, Mhammad Mhammadi; Aging Analysis and Recnductring f Overhead Cnductrs fr Radial Distributin Systems Using Genetic Algrithm; Jurnal f Electrical Engineering & Technlgy (JEET; pp. -8, 204. [2] Mahdi Mzaffari Legha and et al, A new hybrid particle swarm ptimizatin apprach fr sizing and placement enhancement f distributed generatin IEEE Cnference, ; Pages [22] Web site Electrical Pwer Engineering Specialists, REPORTs, 204. Available at: < [accessed ] [23] Mahdi Mzaffari Legha Majid Gandmkar, Recnfiguratin f MV netwrk fr balancing and reducing lsses t by CYMEDIST sftware in Khrramabad, 6th Electric Pwer Distributin Cnference (EPDC6, pp , 202. [24] Mahdi Mzaffari Legha, Human Gadari,, Technical and Ecnmical Evaluatin f Slar Plant fr Electricity Supply Anar City Residential Custmers, Middle-East Jurnal f Scientific Research, pp , 203. IJSER 204

9 Internatinal Jurnal f Scientific & Engineering Research, Vlume 5, Issue 0, Octber-204 ISSN [25] Mahdi Mzaffari Legha, Farzaneh Ostvar, Analysis and Recnductring f Overhead Cnductrs with Cnsidering aging fr Radial Distributin Systems Using Imperialist cmpetitive Algrithm, Internatinal Jurnal f Pure and Applied Sciences and Technlgy, Vl. 20, N., January 204, pp. -8. [26] [] N. Mhan, T. Undeland, W. Rbbins, Pwer Electrnics Cnverters, Applicatins and Design, ISBN [27] [2] Daniel Lgue, Philip. T. Krein, Simulatin f Electric Machinery and Pwer Electrnics Interfacing Using MATLAB/SIMULINK, in 7th Wrkshp Cmputer in Pwer Electrnics, 2000,pp IJSER 204