Implementation and Performance Comparison of Five DSP-Based Control Methods for Three-Phase Six-Switch Boost PFC Rectifier

Transcription

1 Implementatin and Perfrmance Cmparisn f Fie DSP-Based Cntrl Methds fr Three-Phase Six-Switch Bst PFC Rectifier Laszl Huber, Misha Kumar, and Milan M. Janić Delta Prducts Crpratin P.O. Bx Dais Drie Research Triangle Park, NC 7709, USA Abstract In this paper, implementatin and perfrmance cmparisn f fie cntrl methds fr the aerage-currentcntrlled three-phase six-switch bst PFC rectifier are presented. The cnsidered aerage-current-cntrl methds include implementatins with three independent cntrllers, with six-step PWM, and with three-step PWM all in statinary (a,b,c) reference frame, as well as aerage-current cntrl in rtating (d,q) reference frame with zer-sequence-signal (ZSS) injectin-based PWM and with space ectr mdulatin (SVM). It is shwn that the aerage-current cntrl with three independent cntrllers exhibits the lwest ttal harmnic distrtin (THD) f input currents, whereas, the aeragecurrent cntrl in the rtating (d,q) reference frame with ZSS injectin-based PWM and SVM exhibit the highest pwer factr. It is als shwn that the aerage-current cntrl with three independent cntrllers requires the shrtest calculatin time. The measurements were perfrmed n a 3-kW, threephase, six-switch, bst PFC rectifier prttype cntrlled by the TMS30F808 DSP frm TI. I. INTRODUCTION Tday, actie three-phase PFC rectifiers need t meet ery challenging perfrmance requirements. In the majrity f applicatins, the input current f actie three-phase PFC rectifiers is required t hae a ttal harmnic distrtin (THD) less than 5% and a pwer factr (PF) greater than 0.99 [1]. One f the mst cst-effectie tplgies that can meet these requirements is the three-phase six-switch bst PFC rectifier [], which is usually implemented withut neutral-pint cnnectin. Many cntrl methds that can achiee a high quality f input currents in the three-phase six-switch bst PFC rectifier are aailable [3], [4]. One direct current cntrl methd, well suited fr digital implementatin, is the aerage-current cntrl [6], [7]. The aerage-current cntrl f the three-phase six-switch bst PFC rectifier can be implemented in different reference frames such as statinary (a,b,c), statinary (α,β), and rtating (d,q) reference frame. The implementatin in statinary (a,b,c) reference frame is dne with three current cntrllers [5], [8]-[1], whereas the implementatin in statinary (α,β) reference frame emplys tw current cntrllers and requires signal transfrmatins frm 3-phase t -phase statinary crdinate system [3], [4]. Finally, implementatin in rtating (d,q) reference frame emplys tw current cntrllers [3], [4], [9], [13] and requires signal transfrmatins frm 3-phase statinary t -phase rtating crdinate system [14]. Generally, in three-wire implementatins (i.e., withut neutral-pint cnnectin) in statinary (a,b,c) reference frame, it is pssible t hae nly tw ut f three cntrllers actiely shaping the current at a gien time because the sum f the phase currents is zer. The desired current in the phase f the inactie cntrller is autmatically btained as the negatie sum f the actiely cntrlled currents. One implementatin f this cntrl methd is based n diiding the line cycle f input phase ltages in six 60 -segments (six-step PWM) [8]-[10], as shwn in Fig. 1. In each 60 - segment, the cntrller in the phase f the highest abslute alue ltage is disabled, i.e., switches in the crrespnding leg are turned ff, which results in reduced switching lsses. Anther implementatin f this cntrl methd is based n diiding the line cycle f input phase ltages in three 10 - segments (three-step PWM) [10] as shwn in Fig.. In each 10 segment, the cntrller in the phase f the mst psitie (r mst negatie) phase ltage is disabled, i.e., the switches in the crrespnding leg are turned ff. The a0 b0 c a0 I II III IV V VI Fig segments f six step PWM. b0 c I II III I (a) t enp t c0 a0 b0 enn I II III (b) Fig. 10 segments f three-step PWM referenced t: (a) psitie enelpe, (b) negatie enelpe f input phase ltages. t /15/$ IEEE 101

2 p a0 b0 c0 i a i b i c L a L b L c S ap S bp S cp S an S bn S cn C p C n + - OUTPUT VOLTAGE SENSING K d ANTIALIASING FILTER 1.5V Offset LINE VOLTAGE SENSING Ks ANTIALIASING FILTER 1.5V Offset PHASE CURRENT SENSING K cs LOW-PASS FILTER a0 ZSS ADC 1 ADC 1 DUTY-CYCLE FEEDFORWARD + ZSS INJECTION a0 + ZSS ref ab CURRENT ca i a 1 3 i aref Phase A 1 Phase B Phase C a0 AVG S an d an a0 n S ap DPWM d CCa VOLTAGE FEEDFORWARD K mab B C C A b0 c0 EA ADC 1 VOLTAGE ZSS ZERO-SEQUENCE SIGNAL (ZSS) GENERATOR ref DSP - ntatin fr digital alues Fig. 3 Simplified circuit diagram f pwer stage (L a =L b =L c =1mH, C p =C n =40 H) and blck diagram f cntrl circuit in statinary (a,b,c) reference frame. majr benefit f the three-step er the six-step PWM is that it exhibits much reduced input-current transients at the segment transitins which impres THD and PF perfrmance and reduces susceptibility t false segment detectin [10]. Althugh in three-wire pwer-systems the three phase currents are nt independent, three independent current cntrllers can als be emplyed [5], [11], [1]. As shwn in [5], the whle rectifier system is stable if the equialent single-phase cntrl lps are stable. In bth statinary (a,b,c) and (α,β) reference frames, the current cntrllers can be implemented with P and PI cmpensatin. In [1], it was shwn that in the three-phase six-switch bst PFC rectifier with aerage-current cntrl and with mismatched input-ltage and input-current sensing gains, the current cntrller with P cmpensatin exhibits lwer THD f input currents and higher PF cmpared t that with PI cmpensatin. In additin, when the current references are sinusidal, the PI cmpensatr cannt achiee zer steady-state errr due t the finite gain at the line frequency [15]. T achiee zer steady-state errr with PI cmpensatin, the cntrl is usually implemented in the rtating (d,q) reference frame, where the sinusidal signals are transfrmed t dc signals [3], [4], [13]. Hweer, zer steady-state errr can als be achieed in the statinary (a,b,c) and (α,β) reference frames, if instead f PI cmpensatin, a prprtinal plus resnant (PR) cntrller is emplyed [4], [15]-[17]. When the cntrl is implemented in the rtating (d,q) reference frame, the utput signals f the current cntrllers, after being transfrmed frm the rtating (d,q) back t the statinary (a,b,c) reference frame, can be further prcessed by zer-sequence-signal (ZSS) injectin-based PWM r by space ectr mdulatin (SVM). It can be shwn that the ZSS-injectin-based PWM and SVM are equialent [18]. In this paper, implementatin and perfrmance cmparisn f fie cntrl methds fr the aerage-currentcntrlled three-phase six-switch bst PFC rectifier are presented. Three cntrl methds in the statinary (a,b,c) reference frame and tw in the rtating (d, q) frame are cnsidered. The statinary (a,b,c) reference frame methds include implementatins with three independent cntrllers, with six-step PWM, and with three-step PWM, whereas the rtating (d, q) frame methds include implementatins with ZSS-injectin-based PWM and with SVM. Experimental perfrmance ealuatin f the input-current THD and PF, as well as DSP calculatin time, was perfrmed n a 3-kW, three-phase, six-switch, bst PFC rectifier prttype cntrlled by the TMS30F808 DSP frm TI. II. POWER STAGE AND CONTROL CIRCUIT The simplified circuit diagram f the three-phase sixswitch bst PFC rectifier is shwn in Fig. 3. The switches are implemented with IGBTs in a six-pack mdule [19]. The switching frequency is selected as f sw = 0 khz, which is the maximum recmmended f sw fr the IGBT mdule. The input phase ltage range is 10 ± 15% Vrms, Hz, the nminal utput ltage is 400 V, and the maximum utput pwer is 3 kw. The blck diagram f the cntrl circuit in the statinary (a,b,c) reference frame is als shwn in Fig. 3. Aeragecurrent cntrl is implemented using digital signal prcessr (DSP) TMS30F808 frm TI [0]. Fr aeragecurrent cntrl, the input phase-phase ltages, phase 10

3 currents, and the utput ltage are sensed. The respectie sensing gains are dented as K s, K cs, and K d, as shwn in Fig. 3. The sensed ltages and currents are cnerted t digital signals thrugh the 1-bit analg-digital cnerter (ADC) f the DSP. The input ltage range f the ADC is 0-3 V, i.e., the full-scale range = 3 V. As nly psitie ltages can be applied t the input f the ADC, the biplar phase-phase ltages and phase currents are scaled t ±/ and leel shifted by /. The utput signals f the DSP are the digital PWM (DPWM) gate signals fr the bttm switches S xn, xϵ{a,b,c}. The DPWM perates with a triangular carrier. As the clck frequency f the DSP is f sysclck = 100 MHz, the peak alue f the triangular carrier is C pk = 1/ f sysclck /f sw = 500. All the sensed signals are sampled at the peak f the triangular carrier. The crner frequency f the input- and utput-ltage antialiasing filters is f AAFin = 3 khz and f AAFut = 550 Hz, respectiely, whereas the crner frequency f the lw-pass filter f the sensed inductr-currents is f LPF = 9.5 khz. The ltage cntrller is implemented with PI cmpensatin (fr better regulatin f the utput ltage), whereas, the current cntrller is implemented with P cmpensatin because f its benefits cmpared t PI cmpensatin as explained in [1]. The aerage-current cntrl implementatin als includes ltage feedfrward (VFF) [6], duty-cycle feedfrward (DFF) [1], and zersequence-signal (ZSS) injectin [18]. Generally, VFF can make the utput ltage practically insensitie t lineltage ariatins. Hweer, VFF with P-cmpensated current cntrller is effectie nly if DFF is als implemented, as shwn in [1]. Generally, ZSS injectin is emplyed t extend (up t 15%) the input and/r utput cntrl range f the cnerter [18]. In additin, ZSS injectin impres the THD f input-currents [1]. The ZSS signal ZSS, shwn in Fig. 3, Fig. 4 ZSS injectin methds: (a) Psitie enelpe enp and negatie enelpe enn f input phase ltages, (b) VZSS fr three independent cntrllers, (c) VZSS fr six-step PWM, (d) VZSS fr three-step PWM referenced t enp, (e) VZSS fr three-step PWM referenced t enn. enp max(a0,b0,c0) enn min(a0,b0,c0) ZSS ZSS Vref Vref ZSS ZSS V enp enp ref V enn ref if if enn enp enp enp enn enn enn is btained frm the input phase ltages and the utput reference ltage. Using different segments f the psitie and negatie enelpes f the input phase ltages, different ZSS signals and, cnsequently, different cntrl methds can be btained. The ZSS signal fr the aeragecurrent cntrl methd with three independent cntrllers, with six-step PWM and with three-step PWM referenced t enp and enn is shwn in Figs. 4(b)-4(e), respectiely. It shuld be nted that the ZSS-injectin benefits in aeragecurrent cntrl methds with six-step and three-step PWM can als be btained by emplying phase-t-phase current cntrllers withut ZSS injectin instead f phase-current cntrllers with ZSS injectin [10] since the phase-t-phase current-cntrller implementatin exhibits inherent ZSSinjectin prperty. The blck diagram f the cntrl circuit in the rtating (d,q) reference frame is shwn in Fig. 5. The phase angle f the input phase ltages, required fr the signal transfrmatins frm statinary (a,b,c) t rtating (d,q) reference frame and ice ersa is btained by using a threephase phase-lcked lp (PLL) []. Bth the ltage and current cntrller are implemented with PI cmpensatin. It shuld be nted that the cntrl circuit in Fig. 5 des nt include DFF. Generally, DFF is emplyed when current cntrllers with PI cmpensatin are used in the statinary (a,b,c) reference frame t reduce the phase shift between a phase ltage and phase current caused by the cntrller and, cnsequently, t impre the THD and PF. Because in rtating (d,q) reference frame the signals are dc, DFF is nt necessary. As shwn in Fig. 5, the d and q cmpnents are decupled, which simplifies the design f the current cntrllers. Hweer, it shuld be nted that it was bsered in bth simulatin and experimental circuit that in the described design the decupling f d and q cmpnents has practically n effect n the perfrmance f the circuit in steady state peratin and during line and lad transients. Therefre, the decupling f the d and q cmpnents can be mitted if the additinal calculatin time fr decupling is critical fr the ttal duratin f the interrupt serice rutine. The prcedure fr decupling the d and q cmpnents is described in Appendix A. The scaling factr K L in Fig. 5 is btained in Q1 frmat, scaled t the peak alue f the triangular carrier C pk, as KL Kcs 1 C pk. (1) Finally, it shuld be nted that the cntrl circuit in the rtating (d,q) reference frame in Fig. 5 des nt include ZSS injectin because a cmmn signal injected int three phase (a,b,c) cntrllers is mapped t a zer ectr in (a,b,c)-t-(d,q) transfrmatin. The ZSS signal is added t the duty cycles generated in the (d,q) reference frame after the duty cycles are transfrmed frm rtating (d,q) back t statinary (a,b,c) reference frame, as shwn in Fig. 6(a). Using different segments f the psitie and negatie 103

4 ref q VOLTAGE EA i a i b i c 3-PHASE PLL a0 b0 c0 abc abc d C A K m AB B C dq dq enelpes f the duty cycles d a, d b, and d c, different ZSS signals and, cnsequently, different cntrl methds can be btained. It can be shwn that fr any arbitrary ZSS-injectinbased PWM there is an equialent SVM with an apprpriate distributin f the zer switching state ectrs [18]. The blck diagram f the SVM circuit is shwn in Fig. 6(b). In this paper, symmetrical ZSS signal, btained as the negatie aerage f the psitie and negatie enelpes f the duty cycles d a, d b, and d c, similarly as in Fig. 4(b), and the equialent cnentinal cntinuus SVM are used [18]. The equialence between the symmetrical ZSS-injectinbased PWM and the cnentinal cntinuus SVM is explained in Appendix B. In the design f the ltage and current cntrllers, the digital redesign apprach is used, i.e., the cntrl lps are ptimized in cntinuus-time dmain (s-dmain) and then their cntrllers are translated t discrete-time dmain (zdmain) t btain crrespnding recursie expressins that are cded int the DSP. III. PERFORMANCE COMPARISON OF FIVE CONTROL METHODS Perfrmance ealuatin f the fie cntrl methds is perfrmed with respect t their THD f input currents, PF, and DSP calculatin time. Measured steady-state waefrms f the phase currents at nminal phase ltage f 10 Vrms and fr -kw lad are presented in Figs. 7(a)- 7(e). Figures 7(a)-(e) als shw crrespnding measured THD and PF alues. THD and PF measurements as a functin f lad current fr the 10%-100% lad range are presented in Figs. 8(a) and (b), respectiely. It shuld be nted that the THD and PF alues in Fig. 8 are btained as aerage alues f the measured THD and PF f indiidual phases. i dref i d i q i qref = 0 d q CURRENT d L V L V K L K L CURRENT q d CCd d decupl,d d decupl,q d CCq Fig. 5 Blck diagram f cntrl circuit in rtating (d,q) reference frame. d d d q dq abc d a d b d c d a d b d c d a d b d c d ZSS ZERO-SEQUENCE SIGNAL (ZSS) GENERATOR d azss d bzss d czss It can be cncluded frm Figs. 7 and 8 that the aeragecurrent cntrl with three independent cntrllers exhibits the lwest THD f input currents, whereas, the aeragecurrent cntrl in the (d,q) reference frame with ZSSinjectin-based PWM and SVM, as well as the three-step PWM generate slightly higher THD. The PF f the tw cntrl methds in the (d,q) reference frame is the highest, whereas, the PF btained with the three independent cntrllers and with the three-step PWM is slightly lwer. The THD and PF perfrmance f the six-step PWM is inferir cmpared t that f the ther methds. DSP calculatin times, measured within an interrupt serice rutine frm the ADC utput t the DPWM input, are presented in Table I. It can be seen that the aerage-current cntrl with three independent cntrllers requires the shrtest calculatin time, whereas, the six-step PWM requires the lngest calculatin time due t the additinal cde necessary t achiee reliable 60 -segment detectin. IV. SUMMARY In this paper, implementatin and perfrmance cmparisn f fie cntrl methds fr the aerage-currentcntrlled three-phase six-switch bst PFC rectifier are presented. Three cntrl methds in the statinary (a,b,c) reference frame and tw in the rtating (d, q) frame are cnsidered. The statinary (a,b,c) reference frame methds include implementatins with three independent cntrllers, with six-step PWM, and with three-step PWM, whereas the rtating (d, q) frame methds include implementatins with ZSS-injectin-based PWM and with SVM. 1 (a) SECTOR DETECTION Sectr CALCULATION & DISTRIBUTION OF ON-TIMES OF SSVs TO DPWM d asvm d bsvm d csvm TO DPWM (b) Fig. 6 Blck diagram f: (a) ZSS injectin, (b) SVM circuit. 104

5 Experimental perfrmance ealuatin f the input-current THD and PF, as well as DSP calculatin time was perfrmed n a 3-kW, three-phase, six-switch, bst PFC rectifier prttype cntrlled by the TMS30F808 DSP frm TI. It is fund that the aerage-current cntrl with three independent cntrllers exhibits the lwest ttal harmnic distrtin (THD) f input currents, whereas, the aeragecurrent cntrl in the rtating (d,q) reference frame with ZSS injectin-based PWM and SVM exhibit the highest pwer factr. It is als fund that the aerage-current cntrl with three independent cntrllers requires the shrtest calculatin time. V. APPENDIX A The aeraged circuit mdel f the three-phase six-switch bst PFC rectifier in rtating (d,q) reference frame is shwn in Fig. A1 [13]. It shuld be nted in Fig. A1 that the d and q input circuits are cupled due t the appearance f cntrlled ltage surces Li q and Li d in the d and q input circuits, respectiely. Because f this cupling, an (a) Three independent THDa=.95% PFa= THDb=3.1% PFb=0.998 THDc=3% PFc= (a) (b) Six-step PWM THDa=8.5% PFa=0.996 THDb=6.83% PFb=0.996 THDc=8.19% PFc=0.993 (b) THDa=3.79% PFa=0.998 (c) Three-step PWM THDb=3.9% PFb= THDc=3.56% PFc= THDa=3.67% PFa= (d) (e) (d,q) - ZSS (d,q) - SVM THDb=3.55% PFb= THDc=3.6% PFc= THDa=3.38% PFa=0.999 THDb=3.37% PFb= THDc=3.36% PFc= Fig. 8 Measured perfrmance f fie cntrl methds as functin f lad: (a) THD i [%], (b) PF. TABLE I - PERFORMANCE COMPARISON OF FIVE CONTROL METHODS WITH RESPECT TO DSP CALCULATION TIME Cntrl Methd Calculatin time [µs] Three independent cntrllers 17.6 Six-step PWM 3 Fig. 7 Experimental waefrms during steady-state peratin (10Vrms, kw) f phase currents I a, I b, I c [A] with: (a) three independent cntrllers, (b) six-step PWM, (c) three-step PWM, (d) cntrl in (d,q) reference frame with ZSS injectin-based PWM, (e) cntrl in (d,q) reference frame with SVM. Three-step PWM 0.6 Cntrl in (d,q) with ZSS injectin.36 Cntrl in (d,q) with SVM. 105

6 Fig. A1 Aeraged circuit mdel f the three-phase six-switch bst PFC rectifier in rtating (d,q) reference frame. interactin exists between the d and q cmpnents, which makes the cntrl design mre cmplex. Hweer, the cntrl design can be simplified by using a decupling netwrk as shwn in Fig. A. The effect f the decupling netwrk in the d and q input circuits is such that in steadystate the d and q input circuits are cmpletely decupled, as shwn in Fig. A3. The utput circuit mdel with decupling is btained as shwn in Fig. A4 after perfrming the fllwing simple deriatin, Liq Lid dd id dq iq dccd id id dccq iq iq V V. (A1) d i d i CCd d CCq q VI. APPENDIX B The equialence between the symmetrical ZSS-injectinbased PWM and the cnentinal cntinuus SVM can be explained by bsering the aerage ltage f a rectifier leg. With symmetrical ZSS-injectin-based PWM, rectifier leg ltage arn, fr example, is btained as Fig. A3 Decupled d and q input circuit mdels in steady state. Fig. A4 Decupled utput circuit mdel. 1 a ZSS V arn dap V 0 V a ZSS V 0, (B1) as shwn in Fig. B1. With cnentinal cntinuus SVM, the ON-times f the switching state ectrs within a switching cycle T sw are distributed as shwn in Figs. B(a) and B(b), respectiely fr sectrs I, III, V and sectrs II, IV, VI. The hexagn f Fig. A Input circuit mdel with decupling. Fig. B1 Rectifier leg ltage arn btained by symmetrical ZSS-injectin based PWM. 106

7 Fig. B4 Duty cycles f tw nn-zer switching state ectrs in k-th sectr. Fig. B Distributin f ON-times f switching state ectrs within a switching cycle Tsw with cnentinal cntinuus SVM: (a) Sectrs I, III, V; (b) Sectrs II, IV, VI. Fig. B3 Hexagn f switching state ectrs. the switching state ectrs is defined in Fig. B3. Time interals T k and T k+1 in Fig. B represent the ON-times f the tw nn-zer switching state ectrs f the k-th sectr. The crrespnding duty cycles are btained as dk d m sin( 60 s ), (B) and dk 1 d m sin( s ), (B3) where d m is the mdulatin index, defined as Vm dm 3, (B4) V and s is the phase angle within a sectr as shwn in Fig. B3. Duty cycles d k and d k+1 nrmalized t d m are presented Fig. B5 Switching f rectifier legs in Sectr I. in Fig. B4. Duty cycles f the zer switching state ectrs are defined as 1 d k d d d k, (B5) T btain rectifier leg ltage arn, duty cycle d ap needs t be deried fr each sectr I-VI. Fr example, fr sectr I, d ap 1 d 0, (B6) as fllws frm Fig. B5. By applying (B5) t sectr I, 1 d1 d d 0 d7, (B7) d ap in sectr I is determined as Fig. B6 Rectifier leg ltage arn btained by cnentinal cntinuus SVM. 107

8 1 d 1 d d ap. (B8) Finally, rectifier leg ltage arn = d ap V is btained as shwn in Fig. B6. By cmparing leg ltages arn in Figs. B1 and B6, it can be bsered that they are identical. Therefre, it can be cncluded that the symmetrical ZSS-injectin-based PWM and the cnentinal cntinuus SVM result in identical rectifier leg ltages, i.e., that the symmetrical ZSSinjectin-based PWM and the cnentinal cntinuus SVM are equialent. RERERENCES [1] J.W. Klar and T. Friedli, The essence f three-phase PFC rectifier systems Part I, IEEE Trans. Pwer Electrnics, l. 8, n 1, pp , Jan [] T. Friedli, M. Hartmann, and J.W. Klar, The essence f three-phase PFC rectifier systems Part II, IEEE Trans. Pwer Electrnics, l. 9, n, pp , Jan [3] M.P. Kazmierkwski and L. Malesani, Current cntrl techniques fr three-phase ltage-surce PWM cnerters; A surey, IEEE Trans. Ind. Electrnics, l. 45, n 5, pp , Oct [4] M. Malinwski and M.P. Kazmierkwski, Cntrl f three-phase PWM rectifiers, Cntrl in Pwer Electrnics Selected Prblems, Academic Press, San Dieg, CA, 00. [5] M. Hartmann, H. Ertl, and J.W. Klar, Current cntrl f threephase rectifier systems using three independent current cntrllers, IEEE Trans. Pwer Electrnics, l. 8, n 8, pp , Aug [6] P.C. Tdd, UC3854 cntrlled pwer factr crrectin circuit design, Unitrde Applicatin Nte, U-134, pp [7] M. Fu and Q. Chen, A DSP based cntrller fr pwer factr crrectin (PFC) in a rectifier circuit, Prc. Applied Pwer Electrnics Cnf. (APEC), pp , Mar [8] C. Qia and K.M. Smedley, A general three-phase PFC cntrller fr rectifiers with a parallel-cnnected dual bst tplgy, IEEE Trans. Pwer Electrnics, l. 17, n 6, pp , N. 00. [9] S. Hiti, D. Brjeić, R. Ambatipudi, R. Zhang, and Y. Jiang, Aerage current cntrl f three-phase PWM bst rectifier, Rec. IEEE Pwer Electrnics Specialists Cnf. (PESC), pp , Jun [10] L. Huber, M. Kumar, and M.M. Janić, Perfrmance cmparisn f three-step and six-step PWM in aerage-current-cntrlled three-phase six-switch bst PFC rectifier, Prc. Applied Pwer Electrnics Cnf. (APEC), Mar [11] Y. Jiang, H. Ma, F.C. Lee, and D. Brjeić, Simple highperfrmance three-phase bst rectifiers, Rec. IEEE Pwer Electrnics Specialists Cnf. (PESC), pp , Jun [1] L. Huber, M. Kumar, and M.M. Janić, Perfrmance cmparisn f PI and P cmpensatin in aerage-current-cntrlled three-phase sixswitch bst PFC rectifier, Prc. Applied Pwer Electrnics Cnf. (APEC), pp , Mar [13] V. Blask and V. Kaura, A new mathematical mdel and cntrl f a three-phase AC-DC ltage surce cnerter, IEEE Trans. Pwer Electrnics, l. 1, n 1, pp , Jan [14] D.G. Hlmes and T.A. Lip, Pulse width mdulatin fr pwer cnerters, IEEE Press, Piscataway, NJ, 003. [15] Y. Sat, T. Ishizuka, K. Nezu, and T. Kataka, A new cntrl strategy fr ltage-type PWM rectifiers t realize zer steady-state cntrl errr in input current, IEEE Trans. Ind. Applicatins, l. 34, n 3, pp , May/Jun [16] D.N. Zmd, D.G. Hlmes, and G.H. Bde, Frequency-dmain analysis f three-phase linear current regulatrs, IEEE Trans. Ind. Applicatins, l. 37, n, pp , Mar./Apr [17] R. Tedrescu, F. Blaabjerg, M. Liserre, and P.C. Lh, Prprtinalresnant cntrllers and filters fr grid-cnnected ltage-surce cnerters, IEE Prc. Electr. Pwer Appl., l. 153, n. 5, pp , Sep [18] K. Zhu and D. Wang, Relatinship between space-ectr mdulatin and three-phase carrier-based PWM: a cmprehensie analysis, IEEE Trans. Ind. Electrnics, l. 49, n 1, pp , Feb. 00. [19] Pwerex: PM50CLA10 Intelligent Pwer Mdules, Data Sheets, 009. [0] Texas Instruments: TMS30F808 Digital Signal Prcessr, Data Manual, 011. [1] D.M. Van de Sype, K. De Gusseme, A.P.M. Van den Bssche, and J.A. Melkebeek, Duty-rati feedfrward fr digitally cntrlled bst PFC cnerters, IEEE Trans. Ind. Electrnics, l. 5, n 1, pp , Feb [] S.K. Chung, Phase-lcked lp fr grid-cnnected three-phase pwer cnersin systems, IEE Prc. Electr. Pwer Appl., l. 147, n. 3, pp , May