/13/$ IEEE

Transcription

1 Multiple Cnversin Rati Resnant Switched- Capacitr Cnverter with Active Zer Current Detectin Eli Ham, Aln Cervera, and Mr Mrdechai Peretz Pwer Electrnics Labratry, Department f Electrical and Cmputer Engineering Ben-Gurin University f the Negev P.O. Bx 653, Beer-sheva, 8415 Israel. eliham@walla.cm; cervera@bgu.ac.il; mrp@ee.bgu.ac.il Abstract This paper intrduces an active methd fr zer current switching (ZCS) fr resnant switched capacitr cnverters (SCC) with wide dynamic range. The methd is demnstrated n a Binary SCC that features wide range f cnversin ratis. Due t the resultant high efficiency f the cnverter perating under sft-switching cnditins, it is applicable fr higher pwer levels up t the medium pwer range (1W). The resnant peratin is achieved with single air cre inductr and precise cmmutatin at zer current. The sensing signals f the resnant currents are btained frm the flying capacitrs rather than frm the inductive element in which the current includes a dc cmpnent. The zer detectin methd develped is capable f cmpensating fr bth the prcessing delays (frm detectin t switching actin) and fr the large variatins f the resnant characteristics (due t transitin between sub-circuits) and fr any ther cmpnent variatins. A prttype with maximum input vltage f 1V and 19 cnversin ratis was built and tested experimentally. The current sensing was implemented with a simple, cstefficient, passive, sensr. Fr prper cnstructin f the higher pwer experimental prttype, a simple and efficient, islated gate driver was als develped. I. INTDUCTION Switched capacitr cnverters (SCC) are becming an attractive alternative in many applicatins ranging frm lw t high pwer. These include vltage regulatrs fr mbile electrnic systems, vltage equalizers fr batteries and capacitrs, fr phtvltaic (PV) mdules, and fr autmtive applicatins [1-4]. The efficiency f an SCC linearly depends n the prprtinality between the utput vltage and the target vltage V /V Target [5-8], were V Target =MV in and M is the nlad vltage transfer rati. High efficiency can be reached if M is widely cntrllable with high reslutin. The generic equivalent circuit mdel fr SCC [9], describes the lsses by an equivalent resistance cnnected at the utput f the SCC- R eqt.. Hence, the efficiency can be expressed as: Target eqt V / V R / R R. (1) An effective way t realize many target vltages is the Binary/Fibnacci SCC that exhibits a widely cntrllable cnversin rati [7]. The benefits f resnant peratin with this cnverter have been demnstrated in [1]. Sft switching in resnant cnverts can be btained by switching the transistrs at zer current. Given that the resnant frequency depends n the tank's physical parameters C, L and R, the switching times can be either calibrated in advance t match the resnant frequency, r a cntrl circuit can be implemented t identify zer crssing. Fr the case f cnventinal resnant cnverters, Zer Current Switching (ZCS) peratin and its implementatin have been widely demnstrated [11-15]. Fr the case f resnant SCC hwever, few tplgies have been prpsed e.g. [2-4]. A methdlgical apprach t btain ZCS fr the entire dynamic range f the SCC has nt been reprted hithert. The main prblem f pre-calibrating resnant switched capacitr cnverters fr zer current switching is that the physical parameters f the system are prne t drifts thrughut the peratin range. This is particularly crucial in resnant SCC circuits since the inductance is ften implemented by the stray inductance f the circuit which may vary by design and frm ne sub-circuit t anther while the capacitance values drift as a functin f bias vltages and temperature. Hence, an active zer current crss detectin circuitry is required t cmpensate fr all inaccuracies and uncertainties f the parameters, and t assure zer current switching peratin. Anther challenge fr sensing the current in resnant SCC is the dc cmpnent f the resnant current. In this case, the signal is nt centered arund zer and requires additinal prcessing fr zer detectin. This can be dne using rather cstly active sensrs r by resistive elements alngside with very high gain-bandwidth p-amps [16-19]. The bjective f this study is t intrduce an active ZCS methd fr resnant SCC, and t apply it n a resnant Binary/Fibnacci SCC. The resultant cnverter has a wide range f cnversin ratis with high efficiency that can be applied in higher pwer applicatins. The diagram f Fig. 1 shws the system cnfiguratin f the active ZCS cnverter. A resnant Binary/Fibnacci SCC is implemented by adding This research was supprted by the ISRAEL SCIENCE FOUNDATION (Grant N. 517/11) /13/$ IEEE 85

2 Input Rsense C2 17Ω 17Ω CMPxA 22Ω CMPxB 22Ω CMPxC Rsense Input M Digital Cntrl U X 17Ω 22Ω Pwer Stage Active Path Selectr Cmparatr CMPxD Vref Flating Drivers Input Rsense Vcc S1 Vin S6 - S7 S3 C2 Output DAC S2 S4 S5 Output S8 S9 S11 Output S12 Ls S1 Interrupt Fig. 1: Resnant SCC scheme shwing the current sensrs and analg cmparatr fr zer crss detectin. an inductance at the utput f the cnverter. The cnverter is capable fr either step-up r step-dwn cnversins depending n the surce-lad rientatin. That is, step-up cnversin can be btained by swapping the input and utput. Fr simplicity and withut lsing generality, the active ZCS methd is demnstrated and explained fr Binary SCC case. II. different intercnnectins f the capacitrs, as well as stray inductances, an active methd is essential t assure ZCS. This apprach will als cmpensates fr any parameter variatins r drifts due t changes in the perating cnditins. The cntributin f each flying capacitr t the average utput current (fr M=5/8) may be derived frm the equivalent RCL circuits f Fig. 2. Under steady-state peratin, charge balance f all capacitrs is satisfied (i.e. average current equals zer). The sum f the currents fr each state I1-I5, and the sum f all currents, can be expressed as: THE RESONANT BINARY/FIBONACCI SCC The precursr f the cnverter f Fig. 1 is the hardswitched Binary/Fibnacci step-dwn SCC [5-7], which is capable f generating multiple fractinal cnversin ratis with Binary and/r Fibnacci reslutin. Fr a case f three flying capacitrs (n=3), the cnverter is capable f prducing 19 levels f cnversin ratis with high efficiency [7]. T achieve a desired fractinal cnversin rati, a specific switching sequence that intercnnects the flying capacitrs with summing r subtracting actin t the surce and the utput, is applied. Fr example, a cnversin rati f M=5/8, requires Extended Binary (EXB) cdes that are translated t five sub-circuits as illustrated in Fig. 2. Fllwing the switching sequence, the average vltages acrss the flying capacitrs and the utput vltage will adjust t: V=(1/2)Vin, VC2=(1/4)Vin, V=()Vin, VC=(5/8)Vin. Since slutin is unique [6], cntrl is nt required t assure that the capacitrs have stabilized at their nminal vltages. The vltages f the flying capacitrs hld the same average value fr any cnversin rati available using the EXB cde. I 2 I 3 I 4 I 5 ; I1 I 2 I 3 ; C2, M 5/8. I1 I 2 I 3 I 4 I 5 ; I1 I 2 I 3 I 4 I 5 I ; )2 ( where the currents Ij are average currents f each subcircuit (averaged ver the enire switching perid). Table I summarizes the expected currents fr varius cnversin rati that were btained by slving a set f equatins similar t (2). In each case kj is the prprtinal cefficient between the average current f the flying capacitr and utput current fr state j, namely, Ij = kjiut. Duality can be bserved between ratis t 7/8, and 3/8 t 5/8. The results f Table I indicate that fr a given subcircuit the average currents vary cnsiderably between the switching state and in sme cases, negative current may exist in ne f the states. This implies hwever, that fr sme cnversin ratis, ne f the states, in fact, discharges the utput capacitr. The extra circulating current will f curse increase the lsses. The variability f the average currents between the states adds extra burden t the zer detectin circuitry. Resnant peratin with sinusidal current can be btained by relying n the stray inductances that exist in the cnductin path f each sub-circuit. This apprach may be impractical in applicatins where the switching frequency is limited (by the generatr r drive lsses) [2-4]. A mre practical apprach that is applied in this study is t intrduce a single air-cre inductr, Ls, in series t the utput stage [2-4, 1]. By ding s, the same (dminant) inductance is affecting all sub-circuits (Fig. 2). Transitin between switching states (sub-circuits) under Zer Current Switching (ZCS) cnditins can be carried ut either by manual timing f the switching perid f each state, r by an active ZCS, that is, measuring the resnant current, detecting a zer current level, and then tggling the switches t the next sub-circuit sequence. Since the resnant characteristics, i.e. the natural frequency and quality factr, f the sub-circuits may vary significantly because f TABLE I. SOLUTIONS OF THE AVERAGE CAPACITOR CURRENTS FOR VARIOUS RATIOS. M 3/8 5/8 7/8 86 Prprtinal Cefficient k1 k2 k3 k4 k5 1/4 1/2 -- 3/8 1/2 1/4 1/4 3/8-1/2 1/2 1/4 --

3 C2 I1 1 C2 Vin I3 Vin I2 1 C2 Vin -1-1 I4 I_ I5 I_C Fig 2: Resnant SCC sub-circuits cnfigured frm the EXB cdes f M=5/8. I_ T illustrate the peratin f the resnant SCC, typical currents and vltages wavefrms, are depicted in Fig. 3 fr the case f M=5/8. It can be bserved that the average currents f the flying capacitrs is zer, their vltages are stabilized, and that the DC utput current is built up by the cntributin f all sub-circuits that, in turn, are cnnected t the lad fr half a resnant perid. The prtin f negative current is als bserved. 4 2 Iut (a) III PRACTICAL IMPLEMENTATION Time (s) S5 T realize cst-effective resnant peratin fr the SCC f Fig. 1, that is, t btain sft-switching f all switches fr all transitins between sub-circuits, the fllwing challenges need t be addressed: The seemingly natural current sensing pint, the series inductance t the utput, cntains a dc cmpnent. The resnant characteristics (natural frequency and quality factr) are cnsiderably different frm ne subcircuit t anther. This is due t different intercnnectins f the flying capacitrs accrding t the EXB cde (e.g. Fig. 2). Uncertainties and variatins f the parameters (inductance and capacitance) may be very large. Especially fr different perating cnditins (cnversin rati and pwer levels). The average and the peak current are nt cnstant fr each sub-circuit and fr a given state at different pwer ratings. Zer current detectin at the crssing pint is impractical due t pr signal-t-nise (SNR) rati and the time delay frm detectin t cmmutatin f the switches. Selectin f the reference depends n the abve arguments V_ AVG(V_) V_C2 AVG(V_C2) V_ AVG(V_) ut AVG(ut) (b) Time (s) Fig. 3: Resnant Binary SCC (a) Capacitrs and utput stage current wavefrms. (b) Capacitrs and utput vltages wavefrms. PSIM Simulatins set-up at: M=5/8, Vin=1V, Put=1W, Ls=2nH, all flying capacitrs Cj=9.4µF, and fs=9khz. magnetic current transfrmers are placed n all three flying capacitrs. Since the aim f the current sensing is the detectin f the zer crssing pint rather than regulatin, the dc cmpnent f the current is nt f interest. The reasn fr the apparent redundancy in the current measurements is that there is n single capacitr that participates in all the states fr all vltage rati cnfiguratins. In the example shwn in Fig. 2 f 5/8, participates in all the states, but fr ther ratis such as 2/8 it is mitted. By having three sensrs, current can be read frm any active capacitr. A cmparatr mdule that is integrated in a micrcntrller was utilized in this wrk fr current detectin. Since the cmparatr is a part f the IC and prhibits negative vltages, the sensed current was first rectified and then cnverted t a prprtinal vltage using T vercme these challenges, a zer current detectin and cntrl circuitry was develped in this study and is schematically described in Fig. 1. It includes a current sensr fr each f the flying capacitrs, cmparatr mdule, micrcntrller, and decders. The transitin between switching states f the EXB cde is gverned by cmparing the resnant currents t specified references. These are discussed in this sectin which als addresses issues f limiting the inrush current, stabilizing the capacitrs vltages after startup, and the realizatin f simple and efficient flating gate drivers f the pwer switches. A. Current sensing and zer crssing detectin T eliminate the need fr a rather cstly, active current sensing circuitry that accmmdates dc current, passive 87

4 a resistr Rsense. T prtect the I/O prts f the digital cntrller and since nly the infrmatin in the vicinity f zer current is f interest, the rectified signal is clamped t the vltage rails by dides. The series resistr is used t limit the current t the cntrller. By taking these measures f precautin, the resistr Rsense can be selected t the wrstcase fr the state f the lwest current. At steady-state, switching cmmand is initiated by the analg cmparatr mdule. The cmparatr utput triggers an auxiliary interrupt upn zer detectin in which the switching state f the next sub-circuit is applied n the transistrs, and if required, changes the path selectr f the MUX fr next state. Vm1 Vm2 Ref Value Cmparatr State td t2/2 t1/2 Fig. 4: Wrst-case cnditins f state current variatin and the mismatch f the switching instance due t fixed reference settings. B. Reference ltage As mentined abve, the cmparatr reference vltage cannt be zer since finite respnse time, td, exists in the cntrl system i.e. delay time frm detectin t actual switching actin. The reference vltage is set t cmpensate fr td and fr the slpe f the sensed current [2]. Fig. 4 shws typical difference between tw state pulses being sensed. Assuming a high quality factr (Q>3), the reference vltage, as a functin f the resnant peak and time duratin can be expressed as implies a small deviatin frm the true zer crssing pint, allwing the use f a fixed reference vltage. In this wrk, the reference vltage and the sensing gain are selected such that the true ZCS is btained at higher pwer levels (higher states currents), and the small mismatches in the ZCS will be at lwer pwer levels. T allw peratin in wide range f pwer levels and input vltage variatins and still wrk in the vicinity f ZCS, a carse tuner t switch between peratin ranges is realized. The scaling f the sensing gain is implemented by vltage dividers branching ut t the MUX (Fig. 1). 1 t sin 2 d Rsense (3) 2 tj n where n is the current transfrmer winding rati, Imj is the flying capacitrs currents, tj is the resnant perid, and j {1,2,3,4} is state indicatr. The peak value f the sensed signal is translated int vltage by Vmj=(Imj/n) Rsense. Vref j td Mismatch Im j Anther cnsideratin when setting a lw reference value is the need t avid the grund nise caused by imperfect switching at nnzer, cmmn-mde, etc. that may result in errneus triggering f the cmparatr. This is vercme by a blanking perid f the cmparatr after switching actin, as dne in many cmmercial current sensing riented applicatins. The slpe f the sensed current depends n the circuits resnant frequency and peak currents, and varies frm ne sub-circuit t anther. Variable reference vltage wuld assure accurate ZCS at every switching instance. Hwever, this requires an extremely fast cntrl lp t btain the infrmatin f the state current n-the-fly [21]. T avid this cmplexity, a cmprmise is made based n the expected variatins in the currents due t the peratin in different sub-circuits and parameters variatins. It allws setting f a cnstant reference vltage with the penalty f mismatch in the switching with respect t the zer crssing pint. Cnsidering an extreme wrst-case slpe variatin as depicted in Fig. 4 f 4% increase in peak current and 2% increase in resnant perid, and that td is apprximately.1tj, the rati between the nminal reference vltage (Vref2) and the wrst-case reference (Vref2) can be btained using (3), that is: C. Stabilizing the flying capacitrs vltage n startup The design f the active ZCS methd and circuitry assumes that the vltages f all capacitrs have stabilized t their nminal values (binary fractins). Applying the abve zer detectin methd (demnstrated in detail in the next sectin), assures that at steady state ZCS is realized fr all cnversin ratis and ver a wide peratin range f input vltage and pwer levels. In a practical turn n situatin, the capacitrs vltages are zer. This results in high inrush currents if the cnverter is allwed t perate in the vicinity f the steady-state resnant frequency. Mrever, relying n the cmparatr t trigger cmmutatin is impractical since the inrush current prfile may nt be f a resnant nature. T remedy this, a vltage-stabilizing and current-limiting sequence is required t limit the flying capacitrs current t a safe value and t bring the flying capacitrs vltage t their steady-state value. 1.1t1 sin 2 Rsense n t1 Vref , (4) Vref 2 I m2 1.1t1 sin 2 Rsense n 2 2t1 4 I m1 In this study, as shwn in Fig. 5, a vltage-stabilizing and current-limiting methd that is based n the peratin f the Binary cnverter is applied. The cncept is t rely n the EXB cdes t assure stabilizatin f the capacitrs vltages which translates int an abslute maximum mismatch in the switching time f.1tj. Prvided that the peratin f each sub-circuit is in the range f micrsecnds, the result f (4) 88

5 Inductr Current (a) (b) (c) Time Interval Fig 5: Cnceptual peratin f the sft start sequences fr M=3/8 (resnant current): (a) high-frequency switching; (b) estimated resnant values; (c) active ZCS methd. R1 Gate Drive In Vp Drive Islatin T1 C2 Vs D1 D2 1:1 Pulse Trans. R2 Q1 Q2 Switch Dr.1 M1 G M2 Dr.2 S t the crrect values, and t limit the inrush current by cntrlling the switching frequency, this is dne as fllws: At startup the switching times are made significantly shrter than the resnant perid such that the peak current des nt exceed a set maximum value. This is dne fr few cycles until the vltage acrss the capacitrs has stabilized. Then, a secnd switching sequence that is adjusted t the estimated resnant values is applied fr few cycles t ease the transitin t active current sensing. At the end f this phase, the ZCS circuitry is activated and transitin between subcircuits is gverned by the cmparatr utput. D. Switches and Islated Gate Drivers T facilitate all the intercnnectins f the flying capacitrs as prescribed in the EXB cdes [5-7] fr all cnversin ratis, the cnverter includes twelve furquadrant switches (Fig. 1). Each switch is realized by tw N channel pwer MOSFETs with the gate and surces intercnnected as depicted in Fig. 6. Prper design f that allws peratin at high input vltages requires islated gate drivers. As depicted in Fig. 6, the gate driver structure used in this sudy cnsists f a 1:1 pulse transfrmer fr islatin, a dc blcking capacitr C 1 t prevent the dc cntent f the gate drive frm passing thrugh the pulse transfrmer, C 2 and D 2 t restre the dc level at the secndary side, capacitr C 3 that acts as independent flating supply, and NPN and PNP transistrs cnnected in a pushpull cnfiguratin. Assuming that the vltages acrss C 2 and C 3 are stable, the peratin f the gate driver may be described as fllws: n State: Vp is psitive, D 1 is frward biased and C 3 partially discharges thrugh Q 1 that is saturated, and charges C GS turning n the MOSFET. Then, C 3 recharges thrugh C 2 and D 1. The independent supplier C 3 prvides a quick charging f C GS and therefre, the rise time is relatively fast ff state: V p is negative, D 2 is frward biased, C 2 nw charges in the ppsite directin thrugh D 2. C GS discharges thrugh Q 2 that is saturated, turning ff the MOSFET. R 2 damps ptential vershts that may ccur due t stray inductances. The experimental flating drivers have shwn the capabilities t perate at the switching frequency range f 3kHz-35kHz, wide duty cycle range f.1-.9, and rise and fall times f apprximately 2ns. IV. EXPERIMENTAL RESULTS T demnstrate the perfrmance f the resnant Binary SCC and the peratin f the active zer current switching, a 1W prttype has been built and tested experimentally. Summary f the system cmpnents can be fund in Fig. 6: Islated Gate Driver and fur-quadrant switch using N channel pwer MOSFETs. Table II. The generatin f the EXB cdes has been realized n a dspi3f series micrcntrller. Due t the large number f I/O prts required fr the pwer switches, an auxiliary decder is used. The micrcntrller selected includes an analg cmparatr mdule and a multiplexer t allw selectin f the input feed. The cmparatr mdule features high-speed peratin with a typical delay f 2ns and a typical ffset vltage f ±5mV. Hwever, a typical delay f the zer detectin system, frm cmparatr detectin until the time that an interrupt is triggered was measured t be 5ns. The ttal prcessing time (frm cmparatr t switches cmmutatin) was fund t be apprximately 1µs. Fllwing the design guidelines abve, the wrst-case resnant frequency (highest value) per state is set t 18kHz t allw sufficient prcessing time. The reference vltage t the cmparatr is set t 1.65V t cmpensate fr the prcessing time delay and imprve the SNR f the detectin. Perfrmance f the system and the ZCS methd develped is demnstrated n peratin with the cnversin ratis f, 3/8, 5/8, and 7/8 t cver the entire peratin range. Fr each f the cnversin ratis, the capability f the methd t lck the switching frequency t the resnant frequency is verified fr wide range f line (3-8V) and lad variatins (2-13W). Fr the cnversin ratis f 3/8 and 5/8, the current has been sensed frm C 3 that is active at all sub-circuits and the peak currents frm ne state t anther are f the same rder. Fr the case f, the current levels significantly vary between subcircuits, therefre, the feed t the cmparatr has been switched between C 3 and C 2. A larger R sense is chsen fr C 2 t successfully detect the zer crssing pint at lwer currents. Fr 7/8, t cver the full pwer range f 13W, the current is sensed frm tp f the resistive ladder (39Ω) f C 3 fr lwer pwer range (up t 7W), and is then switched manually t the vltage divisin pint (22Ω) t measure higher pwer levels up t 13W. The measurement circuitry (sensrs, dividers, etc.) is detailed in Fig. 1. Fig. 7 shws exemplary snapshts f the system perating at steady-state with active ZCS fr fur cnversin ratis tested. As described in the practical implementatin sectin and can be bserved frm Fig. 7, large differences exist between the sub-circuits in the peak currents, quality factrs, and the signals slpes at the vicinity f zer current. Minr glitches in the current shapes are the result f small deviatins between the estimated reference vltage and the experimental signal. T verify the peratin f the active ZCS methd, tw sets f experiments have been carried ut. In the first 89

6 experiment, the lad resistance is kept cnstant while the input vltage varied frm 3V t 8V. Active ZCS is btained fr the entire peratin range and all cnversin ratins. Fig. 9 shws the efficiency curves f the cnverter as a functin f the utput pwer fr each f the cnversin ratis. It can be bserved that, as expected frm the thery f SCC, the efficiency is virtually cnstant fr a given lad resistance. The strength f the active ZCS is highlighted in Table III, which summarizes the average values f equivalent resistance and efficiency, and the deviatin (in percentage) f the duratin f each sub-circuit. As described earlier and can als be bserved Fig. 7, the cnductin time f the subcircuit varies frm ne t anther, this is primarily due changes in the verall capacitance. Mrever, Table III indicates that the duratin f a specific sub-circuit may als vary cnsiderably due t changes in cmpnents values fr different perating cnditins, strngly prmting the necessity f an active methd fr zer detectin. The largest variatins in cmpnents values are expected in wider cnversin ratis such as. There, larger rms currents are needed per-unit f transferred pwer which affects the capacitance and inductance within a sub-circuit. The larger rms currents are als the reasn fr the smewhat lwer efficiency in spite f the lwer equivalent resistance btained fr this rati. In the secnd experiment, the input vltage is kept cnstant at 8V while varying the lad. Active ZCS is btained fr the entire peratin range and all cnversin ratins. Fig. 1 shws the efficiency curves f the cnverter as a functin f the utput pwer fr each f the cnversin ratis. Similarly t the previus experiment, the efficiency is nearly cnstant fr a wide peratin range. It shuld be nted hwever, that in the case f, a narrwer pwer range is examined due t practical cnstraints n the stress f the cmpnents. The pwer range fr each cnversin rati that is cvered in this experiment has been intentinally limited due t practical restrictins. That is, the experiment is cnducted such that the maximum current stress n the flying capacitrs des nt exceed 4Arms. The startup sequence that was described earlier is als demnstrated n the experimental setup. Fig. 8 shws the three peratin mdes used limit the inrush currents and stabilize the capacitrs vltages, that is, peratin with EXB cde at: (a) high frequency; (b) estimated times; (c) activating the active ZCS mde and lcking the switching frequency t the resnant frequency. V. DISCUSSION AND NCLUSIONS An active zer current switching methd that allws resnant peratin f Binary and Fibnacci step-up/dwn switch-capacitr cnverter was develped and tested experimentally. Fr high-frequency resnant peratin, the stray inductances f the circuit can be used. T lwer the frequency f peratin, and by ding s t ease the wrklad requirements f the digital prcessr and allw the use f a simple, lw-cst cntrller, a single air-cre inductr in series t the utput stage, was added. The active zer current crss detectin was fund t accurately adjust the switching times fr fur different RCL sub-circuits dictated by the EXB/SFN cdes. The current sensing mechanism was implemented using three current transfrmers strategically munted after the capacitrs t avid measurement f the utput current that includes a dc cmpnent. The majr challenge in the design f a resnant Binary SCC is the significant variatin in switching times that is required fr sft-switching peratin. This variatin is present when switching between ne sub-circuit t anther which may invlve different number f capacitrs in series, and therefre, changes the resnant perid. Anther surce fr different resnant perids is that the capacitance and inductance values are strngly dependent n the perating cnditins. This means that the time perid f a given subcircuit is nt cnstant fr variatins in the pwer level r the input vltage, and rules ut any nn-instantaneus ZCS r pre-calibrated resnant peratin. The experimental validatin cnfirmed that cnjecture and highlighted the advantages f an active methd. It revealed that the changes in the resnant perid within a sub-circuit are significant and may vary up t 3% fr the peratin range tested. It has als been established that althugh the resnant perids vary cnsiderably, the slpe f the sensed current in the vicinity f the zer crssing pint is less prne t variatins. M TABLE II. NVERTER PARAMETERS Cmpnent Pwer Stage Part N. Value Input capacitr C575X7R2A475K 6 x 4.7µF/1V Output capacitr C575X7R2A475K 1 x4.7µf/1v Flying capacitr C575X7R2A475K 3 x 4.7µF/1V MOSFETs (R DSn) IPA3N1N3 2 x 3mΩ Air Inductr Air cre 2.1µH Micrcntrller dspi3fj16gs52 Current FXC -TN16/9.3/6.3 Transfrmer (Ferrite trid) 1:1 Digital Sectin Micrcntrller dspi3fj16gs52 16bit, 4MIPS Decder MC745H39A Flating Driver Driver MIC4427 Pulse Transfrmer GT A 1:1 Transistr (Q 1) JE181 Transistr (Q 2) JE17 Dides (D 1, D 2) 1N914 R ut [Ω] TABLE III. MEASUREMENTS WITH ACTIVE ZCS FOR NSTANT R eqt [Ω] η AV ΔV in [V] ΔI ut [A] Δt s1 [%] Δt s2 [%] Δt s3 [%] Δt s4 [%] / / / Δx Indicates the amunt f variatin in a measured variable x value thrughut the experiment. 81

7 (a) (b) VI_ VI_ (c) VI_C2 Vcmp Vcmp Vint St1 (d) VI_ St2 St3 St4 VI_ Vcmp Vcmp Vint Vint Fig. 7: Experimental result f the Binary cnverter perating in active ZCS mde fr varius cnversin ratis. (a) M=, Vin=8V, Put=31.3W, η=.85; Traces tp t bttm: inductr current ILs (.8A/div), rectified sensed vltage resulting frm Ic3,VIc3 (1V/div), rectified sense vltage resulting frm Ic2, VIc2 (1V/div), cmparatr utput, Vcmp (5V/div). Hrizntal scale (5µs/div). (b) M=3/8, Vin=1V, Put=76.5W, η=.92; Traces tp t bttm: ILs (.8A/div); VIc3 (1V/div); Vcmp (5V/div); interrupt status Vint (5V/div). Hrizntal scale (1µs/div). (c) M=5/8, Vin=8V, Put=73W, η=.95. Traces and hrizntal scale: as in (b). (d) M=7/8, Vin=8V, Put=131.7W, η=.99. Traces tp t bttm: ILs (.4A/div), VIc3 (5V/div); Vcmp (5V/div); Vint (5V/div). Hrizntal scale (5µs/div). Therefre, fr the case f the Binary SCC, the methd can be further simplified by fixed reference vltage settings. This eliminates the need fr additinal fast cmpensatin lp t vary the reference vltage. by rewriting (1) in the fllwing frm:. (5) V V V / I V / I R T eqt That is, since fr a given pwer level, the lad resistance f larger ratis (smaller fractins) such as is significantly smaller the efficiency is expected t drp per-unit f transferred pwer. Anther bservatin n the efficiency and the expected equivalent resistance is made by the current wavefrms and frm the slutin fr the average currents fr each sub-circuit. It shws that fr sme cnversin ratis, there might be a sub-circuit in which the current is negative. This phenmenn can be explained frm a charge-balance perspective and is given in sectin II. Hwever, frm efficiency and ReqT pint f view, that means that fr that particular sub-circuit, current flws frm the utput int the system which may affect the estimatins f ReqT and the expected efficiency. A detailed analysis f this tpic is beynd the scpe f this paper and will be detailed in subsequent publicatins. The experimental results als supprt the need fr a dynamic wide-range reference vltage in rder t cmpensate fr prcessing delay and different current levels f each sub-circuit. Since a reasnable SNR is required, the reference t the cmparatr was kept cnstant (well abve zer) and the reference was changed by the effective sensing gain. This was dne by resistr dividers f the sensed signal and may be useful fr implementatin in ther resnant switch capacitr tplgies. Study n the efficiency was carried ut. It was fund that althugh the calculated [9] equivalent resistance is the lwest at the rati f, that rati prvides the prest efficiency. Mrever, the efficiency increases fr smaller cnversin ratis (larger fractins). This behavir is intuitively explained by the fact that higher ratis (such as, 3/8) have higher rms current fr a given transferred pwer and hence the pwer lsses will be higher. This can be illustrated The methd presented in this study has been verified t successfully perate resnant Binary SCC and t accmmdate wide and dynamic peratin range, and 811

8 Efficiency Efficiency (a) (b) (c) Fig. 8: Experimental results f the inductr current fr the sft-start methd fr M=3/8: (a) High switching frequency; (b) estimated resnant values; (c) active ZCS methd /8.7 5/8.65 7/ Output Pwer [W] Fig. 9: Measured efficiency, M=-7/8, cnstant R, V in=3-8v Output Pwer [W] Fig. 1: Measured efficiency, M=-7/8, cnstant V in=8v. therefre can be applied t ther multi-phase SCC tplgies that invlve number f sub-circuits and wide peratin range. 3/8 5/8 7/8 REFERENCES [1] A. Iinvici, Switched-capacitr pwer electrnics circuits, IEEE Circuits Syst. Mag., vl. 1, Issue 3, pp.37-42, 21. [2] Fang Zheng Peng, Dng Ca, A zer-current switching multilevel switched-capacitr dc-dc Cnverter, IEEE Trans. n Industry Applicatins, vl.46, n.6, 211. [3] Fang Zheng Peng, Dng Ca, Optimal design f multilevel mdular switched-capacitr dc-dc cnverter, IEEE Cnf.- ECCE 211. [4] Dng Ca, Fang Zheng Peng, A family f zer current switching switched-capacitr dc-dc cnverters, IEEE Cnf. - APEC 21, pp [5] S. Ben-Yaakv, A. Kushnerv, Algebraic fundatin f self adjusting switched capacitrs cnverters, IEEE Cnf.- ECCE, sep. 29. [6] A. Kushnerv, S. Ben-Yaakv, Algebraic synthesis f fibnacci switched capacitr cnverters, IEEE Cnf. - MCAS, nv [7] A. Kushnerv, S. Ben-Yaakv, Unified algebraic synthesis f generalized fibnacci switched capacitr cnverters, IEEE Cnf.- ECCE 212. [8] Y. Beck, S. Singer, Capacitive transpsed series-parallel tplgy with fine tuning capabilities, IEEE Tran. On Circuits and System, vl. 58, n.1, pp 51 61, 211. [9] S. Ben-Yaakv, M. Evzelman, Generic and unified mdel f switched capacitr cnverters, IEEE Cnf. - ECCE, 29. [1] E. Ham, M. M. Peretz, S. Ben-Yaakv, Resnant binary and fibnacci switched-capacitr bidirectinal dc-dc cnverter, IEEEI, Cnf [11] Mishima, T. Nakaka, A new family f ZCS-PWM dc dc cnverters with clamping dides-assisted active edge-resnant Cell, Inter. Cnf. n Electrical Machines and Systems, ICEMS 21. [12] Chien-Ming Wang, Huang-Jen Chiu, A family f zer-currentswitching (ZCS) PWM cnverters using a new zer-current switching auxiliary Circuit, Internatinal Cnf. n Pwer Electrnics and Drive Systems - PEDS, vl. 2, pp , 23. [13] Ling Qin, Shajun Xie, Hui Zhu, A nvel family f PWM cnverters based n imprved ZCS switch cell, IEEE Cnf. - PESC 27, pp [14] Chien-Ming Wang, Nvel zer-current-switching (ZCS) PWM cnverters, IEEE Cnf. IEN 23, vl.1, pp [15] Chien-Ming Wang, A new family f zer-current-switching (ZCS) PWM cnverters, IEEE Transactins n Industrial Electrnics, vl. 52, n.4, pp , August 25. [16] Frghani-zadeh, H.P., Rincn-Mra, G.A., Current-Sensing techniques fr dc-dc cnverters, Midwest Sympsium n Circuits and Systems, MWSCAS-22, vl. 2, pp.ii-577-ii-58. [17] Zheng Lu, Chuanyun Wang, Ming Xu, Pengju Kng, Fred C. Lee, Dcr current sensing technique fr PFC circuits, IEEE Cnf. - APEC 28, pp [18] Panda, R.K., Sawade, N.A., Air cred current sensr fr digital metering & micr-prcessr based prtectin unit, IEEE Cnf. - Pwer India 212, pp [19] Y. N. Ning, Z. P. Wang, A. W. Palmer, K. T. V. Grattan, and D. A. Jacksn, Recent prgress in ptical current sensing techniques, American Institute f Physics 1995, pp [2] S. Ben-Yaakv, M. M. Peretz, A self-adjusting sinusidal pwer surce suitable fr driving capacitive lads, IEEE Trans. n Pwer Electrnics, vl. 21, n.4, pp , 26. [21] E. Rtman, S. Ben-Yaakv, Rapid push-pull resnant charger fr high pwer high vltage applicatin using lw input vltage, IEEE Cnf. - ECCE,