8341 FI-1.x Dual-mode Analogue PMR and Digital PMR (dpmr) Baseband Processing Features. CMX8341 dpmr Baseband Processor. Digital PMR Air Interface:

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1 CML Micrcircuits COMMUNICATION SEMICONDUCTORS Digital PMR (dpmr) Baseband Prcessr D/8341/7 January 2014 DATASHEET Advance Infrmatin 8341 FI-1.x Dual-mde Analgue PMR and Digital PMR (dpmr) Baseband Prcessing Features Digital PMR (dpmr) Baseband Prcessr dpmr (ETSI TS ) Cmpliant Air Interface Physical Layer (Layer 1) Air Interface Data Link layer (Layer 2) 4FSK Mdem Sft-decisin Decding AFSD (Autmatic Frame Sync Detectin) RALCWI Vcder Fully Embedded Implementatin N Licensing r Ryalty payments 3600bps Over Air Data Rate (2400bps Vice plus 1200bps Rbust FEC) 4-bit Viterbi Sft-decisin Decding Analgue PMR (Legacy mde) Full Audi Band Prcessing Sub-audi Filtering CTCSS and DCS 12.5 and 25kHz Channel Filters Built n FirmASIC Technlgy Functin Image 8341FI-1.x Required Serial Memry r Hst Lading Integratin Radmap Auxiliary functins 2 System Clck Outputs Tx PA Ramp DAC 3 DACs, 4 inputs Multiplexed t 2 ADCs GPIO Tx Enable and Rx Enable Outputs Half-duplex Operatin Input frm RF Discriminatr 2-pint Mdulatin Drivers Audi Output with Vlume Cntrl Micrphne Input Lw Pwer Operatin LQFP packaging Applicatins Lw Cst Digital PMR Radis Lw Cst Digital PMR with Legacy Analgue PMR Mde dpmr Baseband Prcessr External Sub-audi Mdulatr Discriminatr RF Sectin PLL Clcks GPIO DACs Mux ADC PA Ramp RF Interface Auxiliary Operatins Digital PMR Air Interface: Physical, Data Link and Cntrl Layer Supprt Data Mdem Vcder Analgue PMR: Cre Functinality Audi Interface System Cntrl External Ref. Clck Pwer Supplies C-BUS µc Interface Serial Memry (Optinal) 2014 CML Micrsystems Plc

2 1 Brief Descriptin The 8341FI-1.x Functin Image (FI) implements a half-duplex digital PMR prcessr including: 4FSK mdem, a large prprtin f the dpmr Air Interface; Physical, Data Link and Cntrl layers, and an embedded lw bit rate RALCWI Vcder (with n license r ryalties required). In cnjunctin with a suitable hst and a limiter/discriminatr based RF transceiver, a cmpact, lw cst, lw pwer digital PMR radi cnfrming t ETSI s dpmr standard TS can be realised. Bth ISF and CSF cnfiguratins are supprted, including built-in supprt fr BCD addressing mdes. Dual mde, analgue/digital PMR peratin can als be achieved with the. The device is als cmpatible with ETSI s dpmr standard TS fr Mde 1 peratin. The embedded functinality f the, managing vice and data systems autnmusly including the Vcder minimises hst micrcntrller interactins enabling the lwest perating pwer and therefre the lngest battery life fr a dpmr radi. The utilises CML s prprietary FirmASIC cmpnent technlgy. On-chip sub-systems are cnfigured by a Functin Image : this is a data file that is upladed during device initialisatin and defines the device's functin and feature set. The Functin Image can be laded autmatically frm an external serial memry r hst µcntrller ver the built-in C-BUS serial interface. The device's functins and features may be enhanced by subsequent Functin Image releases, facilitating in-the-field upgrades. This dcument refers specifically t the features prvided by Functin Image 8341 FI-1.x. Other features include tw auxiliary ADCs with fur selectable inputs and fur auxiliary DAC interfaces (with an ptinal RAMDAC n the first DAC utput, t facilitate transmitter pwer ramping). The device has flexible pwersaving mdes and is available in the L8 (LQFP) package. This Datasheet is the first part f a tw-part dcument cmprising Datasheet and User Manual: the User Manual can be btained by registering yur interest in this prduct with yur lcal CML representative. Text in grey may be implemented in later versins f the Functin Image 8341 FI-1.x. dpmr is a registered trademark f the dpmr Assciatin 2014 CML Micrsystems Plc 2 D/8341/7

3 Sectin CONTENTS Page 1 Brief Descriptin Histry Blck Diagram Signal List Signal Definitins External Cmpnents Cmpnent Value Selectin Reference Clck Frequency Serial Memry Cnnectins Other Cnnectins Autnmus Signal Ruting General Descriptin Prduct Features dpmr Features Analgue PMR Features Universal PMR Functins Auxiliary Functins System Interface Aspects f System Design dpmr Data Transfer RSSI Measurement Serial Memry Cnnectin dpmr Mdem Descriptin Mdulatin Internal Data Prcessing Frame Sync Detectin and Demdulatin FEC and Cding Vice Cding Radi Perfrmance Requirements Tne Generatr Analgue PMR Descriptin External Sub-Audi Prcessing Internal CTCSS and DCS Generatin and Detectin Vice Prcessing: Detailed Descriptins Reference Frequency Hst Interface C-BUS Operatin Functin Image Lading FI Lading frm Hst Cntrller FI Lading frm an external Serial Memry Device Cntrl General Ntes Interrupt Operatin CML Micrsystems Plc 3 D/8341/7

4 8.4.3 Signal Ruting Mdem Cntrl dpmr Frmatted Operatin Tx Mde Tx Mde (PRBS) Rx Mde Rx Mde Eye Rx Mde Pass-thrugh Sync Mde Reset/Abrt Data Transfer Vcder Sectin Pass-thrugh Mde Vcder Sectin Nise Gate dpmr Operating Mdes and Addressing ISF Addressing CSF Addressing Tx Mde (dpmr frmatted) Rx Mde (dpmr frmatted) Slw Data Analgue Mde Tx Mde Analgue Rx Mde Analgue Squelch Operatin GPIO Pin Operatin Auxiliary ADC Operatin Auxiliary DAC/RAMDAC Operatin Digital System Clck Generatrs Main Clck Operatin System Clck Operatin Signal Level Optimisatin Transmit Path Levels Receive Path Levels Tx Spectrum Plts C-BUS Register Summary Perfrmance Specificatin Electrical Perfrmance Abslute Maximum Ratings Operating Limits Operating Characteristics Parametric Perfrmance Operating Characteristics Timing Diagrams C-BUS Timing Packaging CML Micrsystems Plc 4 D/8341/7

5 Table Page Table 1 Definitin f Pwer Supply and Reference Vltages Table 2 Recmmended Cmpnent Values Table 3 dpmr Frame Frmat - Call set-up, n ACK Table 4 dpmr Frame Frmat - Call set-up with ACK Table 5 DCS cdes and values Table 6 CTCSS cdes and values Table 7 BOOTEN Pin States Table 8 Mdem Mde Selectin Table 9 Mdem Cntrl Selectin Table 10 C-BUS Data Registers Table 11 C-BUS Registers Figure Page Figure 1 Blck Diagram... 8 Figure 2 Recmmended External Cmpnents Figure 3 Serial Memry Cnnectins Figure 4 Other Cnnectins Figure 5 Tx Ruting Autnmus mde Figure 6 Rx Ruting Autnmus mde Figure 7 4FSK PRBS Wavefrm - Mdulatin Figure 8 4FSK PRBS Wavefrm - Spectrum Figure 9 dpmr Mdulatin Characteristics Figure 10 Internal Data Prcessing Blcks Figure 11 FS Detectin Figure 12 Rx Audi Respnse Figure 13 Tx Audi Respnse Figure 14 CTCSS and DCS filters Figure 15 C-BUS Transactins Figure 16 FI Lading frm Hst Figure 17 FI Lading frm an external Serial Memry Figure 18 Tx Data Flw Figure 19 Rx Data Flw Figure 20 AuxADC IRQ Operatin Figure 21 Digital Clck Generatin Schemes Figure 22 Tx Level Adjustments (Analgue) Figure 23 Tx Levels (Digital) Figure 24 Rx Level Adjustments (Analgue) Figure 25 Rx Level Adjustments (Digital) Figure 26 Tx Mdulatin Spectra bps Figure 27 C-BUS Timing Figure 28 L8 Mechanical Outline: Order as part n. L It is always recmmended that yu check fr the latest prduct datasheet versin frm the Datasheets page f the CML website: [ CML Micrsystems Plc 5 D/8341/7

6 1.1 Histry Versin Changes Date 7 Figure 9 Updated t match latest ETSI versin 28/01/ Add text abut analgue mde selectin Tx mde test added Rx mde dpmr added Rx mde raw added Table 10 Rx mde raw added RAMDAC and DAC2 tnegen updated t latest descriptins Add input invert bit $B0:b Clarificatin t setting $B1:b1, Rx raw mde added, Tx test mde (repeated wrd fr dpmr Assc. test mdes) added $C3 register descriptin describes digital functins (as well as analgue), RAMDAC multiplier added $C5 bit definitins crrected (matches 7131/7141FI-1 and FI-5) $C7:b7 (enable/disable vcder cntrl) added Add nte n Prg Flag cleared in Rx and Tx mdes Pass-thrugh descriptin updated $CA bit definitins crrected (matches FI-1 and FI-5) $CB bit definitins crrected (matches FI-1 and FI-5) Rx analgue pass-thrugh added 6 Pin 50 nw cnnects t Pin 49. Figure 2 and pinut table crrected. 24/10/12 Crrectin f bit rder in Table 8. Sync Mde and Reset/Abrt descriptins added t 8.5. Bit errr and value t stp RAMDAC clarified in Bit settings clarified in Setting f P1.20 added t Bit settings clarified in Rx Pass-thrugh mde added same as RxEye mde, but withut the RRC filter 30/5/12 Bug in setting SPI Cdec SCLK plarity fixed Internal sub-audi nw enabled by default, P2.0 default value changed t $E030 Descriptin f reset/abrt added t Minimum Rx Input Level nw specified in dpmr MU references changed t dpmr Assciatin Crrected Tx PRBS cmmand t $0032 (nt $0023) References t ATB010 remved 4 Added CTCSS and DCS internal generatin/detectin 15/6/11 Remved references t raw mde Added reference t TS Mde 1 Remved Figure 28 and added FI Updates 3 Standardisatin with CMX7141 FI-5.x Datasheet and User Manual 7/6/11 EEPROM references changed t serial memry Minr typgraphical imprvements 2 Crrectins and additins fllwing further review f Advance dcument. 26/1/11 Additin f analgue PMR functins in FI Original dcument, prepared fr initial release 04/11/10 This is Advance Infrmatin; changes and additins may be made t this specificatin. Parameters marked TBD r left blank will be included in later issues. Items that are highlighted r greyed ut shuld be ignred. These will be clarified in later issues f this 2014 CML Micrsystems Plc 6 D/8341/7

7 dcument. Infrmatin in this advance dcument shuld nt be relied upn fr final prduct design CML Micrsystems Plc 7 D/8341/7

8 2 Blck Diagram Cre Operatins AFSD Sft-decisin Decding 4FSK Mdem Demdulatr Filtering Rx Data Buffer Filtering Tx Data Buffer 4FSK Mdem Mdulatr Data Packet Assembly RALCWI Vcder (Decder) dpmr Paylad Decding Physical layer 1 Data Link layer 2 dpmr Paylad Encding Physical layer 1 Data Link layer 2 RALCWI Vcder (Encder) Rx dpmr Prcessing Tx dpmr Prcessing Audi prcessing Vice Filter De-scrambler De-emphasis Expandr CTCSS/DCS Decder Sub-Audi Filter Rx Analgue PMR Audi prcessing AGC Vice Filter Cmpressr Pre-emphasis Scrambler Channel Filter Limiter CTCSS/DCS Encder Sub-Audi Filter Tx Analgue PMR Signal Inputs Signal Outputs DISCFB DISC MICFB MIC VBias VBias Mux dpmr Baseband Prcessr Tx MOD mde MOD1 MOD2 ALTFB ALT AUDIO VBias TXENA RXENA FI Cnfigured GPIO Auxiliary Functins System Cntrl Main Clck PLL Bt Cntrl REFCLK BOOTEN2 BOOTEN1 GPIOA GPIOB SYSCLK1 GPIO (fr ATB10 cntrl) System Clck 1 GPIO C-BUS Cntrl Interface VIRQN IRQN RDATA CSN CDATA SYSCLK2 System Clck 2 System Clck Outputs Registers SCLK SSOUT DAC1 DAC2 DAC3 DAC4 DAC 1 DAC 2 DAC 3 DAC 4 Ramp prfile RAM Sub-Audi DACs Serial Memry Interface EPSCSN EPSCLK EPSO EPSI DVDD VDEC ADC1 ADC2 ADC3 ADC4 MUX ADC 1 ADC 2 Threshlds Averaging Threshlds Averaging Multiplexed ADCs Pwer Cntrl Pwer Supplies DVSS CVDD AVDD VBIAS BIAS AVSS Figure 1 Blck Diagram 2014 CML Micrsystems Plc 8 D/8341/7

9 3 Signal List L8 Pin Descriptin Pin N. Name Type 1 GPIOB IP + PU r OP General-purpse input/utput. 3 SYSCLK1 OP Synthesised Digital System Clck Output 1 7 TXENA OP Tx Enable active lw when in Tx 10 DISC IP Channel 1 inverting input Cnnect t pin DISCFB OP Channel 1 input amplifier feedback Cnnect t pin 27 (BIAS) 15 ALT IP Channel 2 inverting input 16 ALTFB OP Channel 2 input amplifier feedback 18 MICFB OP Channel 3 input amplifier feedback 20 MIC IP Channel 3 inverting input 22 OUTP OP Audi Psitive Output in digital radi mde 23 MOD1 OP Mdulatr 1 utput 24 MOD2 OP Mdulatr 2 utput 25 OUTN OP Audi Negative Output in digital radi mde. Leave uncnnected if switching between the digital (OUTP) utput and the analgue (AUDIO) utput. See Figure AUDIO OP Audi utput in analgue radi mde 29 AUXADC1 IP Auxiliary ADC input 1 Each f the tw ADC blcks 30 AUXADC2 IP Auxiliary ADC input 2 can select its input signal frm any ne f these input pins, r 33 AUXADC3 IP Auxiliary ADC input 3 frm the MIC, ALT r DISC 34 AUXADC4 IP Auxiliary ADC input 4 input pins. See sectin 8.9 fr details. 36 AUXDAC1 OP Auxiliary DAC utput 1 37 AUXDAC2 OP Auxiliary DAC utput Cnnect t pin AUXDAC3 OP Auxiliary DAC utput 3 48 AUXDAC4 OP Auxiliary DAC utput 4 / Filtered Sub-Audi Output 50 SYNC BI SYNC utput. Cnnect t pin Cnnect t pin REFCLK IP Input frm the external clck surce Cnnect t pin CML Micrsystems Plc 9 D/8341/7

10 L8 Pin Descriptin Pin N. Name Type 59 CDATA IP C-BUS Cmmand Data: Serial data input frm the µc. 61 RDATA T/S C-BUS Reply Data: A 3-state C-BUS serial data utput t the µc. This utput is high impedance when nt sending data t the µc. 62 SSOUT OP Serial Memry Interface Chip Select. Cnnect t pin RESETN IP Vcder sectin General Reset (active lw, n pullup) 69 SCLK IP C-BUS Serial Clck: The C-BUS serial clck input frm the µc. 71 SYSCLK2 OP Synthesised Digital System Clck Output 2 73 CSN IP C-BUS Chip Select: The C-BUS chip select input frm the µc - there is n internal pullup n this input (active lw). 76 EPSI OP Serial Memry Interface Data Output frm 78 EPSCLK OP Serial Memry Interface Clck 81 EPSO IP + PD Serial Memry Interface Data Input t 83 EPSCSN OP Serial Memry Interface Memry Select (active lw) 84 BOOTEN1 IP + PD Used in cnjunctin with BOOTEN2 t determine the peratin f the btstrap prgram Cnnect t pin 78 (EPSCLK) 87 BOOTEN2 IP + PD Cnnect t pin 76 (EPSI) Cnnect t pin 81 (EPSO) 91 IRQN OP Used in cnjunctin with BOOTEN1 t determine the peratin f the btstrap prgram Cnnect t pin 62 (SSOUT) C-BUS Interrupt Request: A 'wire-orable' utput fr cnnectin t the Interrupt Request input f the µc. Pulled dwn t DV SS when active and is high impedance when inactive. An external pull-up resistr (R1) is required. 93 VIRQN OP Cnnect an external pull-up resistr (R2) t DVDD 97 RXENA OP Rx Enable active lw when in Rx mde. 98 GPIOA IP + PU r OP General-purpse input/utput CML Micrsystems Plc 10 D/8341/7

11 L8 Pin Descriptin Pin N. Name Type Pwer Supplies and N Cnnectins 32, 47, 57, 60, 66, 70, 72, 74, 94 DVDD PWR 53, 95 VDEC PWR 31, 96 CVDD PWR 4, 6, 44, 49, 51, 52, 63, 65, 68, 85, 89, 100 5, 9, 17, 19, 21, 40 2, 14, 26,35 AVDD PWR DV DD : Digital +3.3V supply rail. This pin shuld be decupled t DV SS by capacitrs munted clse t the device pins. V DEC : Internally generated 2.5V supply vltage. Must be decupled t DV SS by capacitrs munted clse t the device pins. N ther cnnectins allwed. Digital cre +1.8V supply rail. This pin shuld be decupled t DV SS by capacitrs munted clse t the device pins. DVSS PWR DV SS : Negative Digital Supply AVSS PWR AV SS : Negative Analgue Supply 8 VBIAS PWR 27 BIAS PWR 38, 39, 43, 45, 46, 58, 67, 75, 77, 79, 80, 82, 99 AV DD : Analgue +3.3V supply rail. Levels and threshlds within the device are prprtinal t this vltage. This pin shuld be decupled t AV SS by capacitrs munted clse t the device pins. Internally generated bias vltage f abut AV DD /2, except when the device is in Pwersave mde when vltage n VBIAS pin will discharge t AV SS. Must be decupled t AV SS by a capacitr munted clse t the device pins. N ther cnnectins allwed. D nt cnnect t BIAS pin. Internally generated bias vltage f abut AV DD /2, except when the device is in Pwersave mde when vltage n BIAS pin will discharge t AV SS. Must be decupled t AV SS by a capacitr munted clse t the device pins N ther cnnectins allwed. D nt cnnect t VBIAS pin. n/c NC D nt make any cnnectin t this pin Ntes: IP = Input IP + PU = Input with internal pullup resistr IP + PD = Input with internal pulldwn resistr OP = Output BI = Bidirectinal Digital Signal T/S = 3-state Digital Output PWR = Pwer Supply NC = N Cnnectin 2014 CML Micrsystems Plc 11 D/8341/7

12 3.1 Signal Definitins Table 1 Definitin f Pwer Supply and Reference Vltages Signal Name Pins Usage AV DD AVDD 3.3V Pwer supply fr analgue circuits DV DD DVDD 3.3V Pwer supply fr digital circuits DV CORE CVDD 1.8V Pwer supply fr digital circuits V DEC VDEC 2.5V Internally-derived pwer supply fr digital circuits V BIAS VBIAS, BIAS 1.65V Internally-derived pwer supply fr analgue circuits AV SS AVSS Grund fr all analgue circuits DV SS DVSS Grund fr all digital circuits 2014 CML Micrsystems Plc 12 D/8341/7

13 Miscellaneus Auxiliary Signals C-BUS Bt Cntrl DVSS SYSCLK1 AVDD GPIOB AVSS DVSS TXENA VBIAS AVSS DISC DISCFB AVDD ALT ALTFB AVSS MICFB AVSS MIC AVSS OUTP MOD1 MOD2 OUTN t Serial Memry n/c DVDD CSN DVDD SYSCLK2 DVDD SCLK DVSS n/c DVDD DVSS RESETN DVSS SSOUT RDATA DVDD CDATA n/c DVDD REFCLK VDEC DVSS DVSS Digital PMR (dpmr) Baseband Prcessr 4 External Cmpnents DVDD 3.3V DVDD C9 C10 C11 D1 R3 C12 2.5V VDEC 3.3V DVDD C8 2.5V VDEC C7 C6 C5 R1 R2 1.8V DVCORE EPSI n/c EPSCLK n/c n/c EPSO n/c EPSCSN BOOTEN1 DVSS BOOTEN2 DVSS IRQN VIRQN DVDD VDEC CVDD RXENA GPIOA n/c DVSS Digital Grund Plane L8 Analgue Grund Plane SYNC DVSS AUXDAC4 DVDD n/c n/c DVSS n/c AUXDAC3 AVSS n/c n/c AUXDAC2 AUXDAC1 AVDD AUXADC4 AUXADC3 DVDD CVDD AUXADC2 AUXADC1 AUDIO BIAS AVDD C16 3.3V DVDD C13 DVCORE C14 1.8V DVCORE C V VBIAS AVDD 3.3V AVDD Digital Grund 1.65V VBIAS C19 C32 Analgue Grund C18 C17 DVSS RESETN REFCLK SYNC AUXDAC1-4 AUXADC1-4 RXENA TXENA GPIOA GPIOB SYSCLK1 SYSCLK2 CDATA RDATA CSN IRQN SCLK BOOTEN1 BOOTEN2 AVSS Figure 2 Recmmended External Cmpnents T achieve gd nise perfrmance, V DD decupling is very imprtant. It is recmmended that the printed circuit bard is laid ut with analgue and digital grund planes in the area t prvide a lw impedance cnnectin between the V SS pins and the V DD decupling capacitrs CML Micrsystems Plc 13 D/8341/7

14 Table 2 Recmmended Cmpnent Values R1 100kΩ R9 100kΩ C1 n/f C8 10nF C16 100nF C24 100pF R2 100kΩ R10 100kΩ C2 n/f C9 10µF C17 10µF C25 100pF R3 470kΩ R11 22kΩ C3 n/f C10 10nF C18 10nF C26 470pF R4 10kΩ R12 100kΩ C4 n/f C11 1.0µF C19 100nF C27 470pF R5 100kΩ R13 22kΩ C5 100nF C12 10nF C20 1.0µF C28 100pF R6 100kΩ R14 100kΩ C6 10µF C13 10nF C21 1.0µF C29 100pF R7 100kΩ D1 1N4148 C7 10nF C14 10µF C22 n/f C30 1.0µF R8 100kΩ TG1 TS5A459DBVR C15 100nF C23 100pF C31 1.0µF C32 100nF Resistrs 5%, capacitrs and inductrs 20% unless therwise stated. Please als refer t Figure Cmpnent Value Selectin 1. R7 shuld be selected t prvide the desired dc gain f the discriminatr input, as fllws: GAIN DISC = 100k / R7 2. The gain shuld be such that the resultant utput at the DISCFB pin is within the DISC input signal range specified in Fr 4FSK mdulatin, this signal shuld be dc cupled frm the Limiter/ Discriminatr utput. 3. R6 shuld be selected t prvide the desired dc gain (assuming C21 is nt present) f the alternative input as fllws: GAIN ALT = 100k / R6 4. The gain shuld be such that the resultant utput at the ALTFB pin is within the alternative input signal range specified in R5 shuld be selected t prvide the desired dc gain (assuming C20 is nt present) f the micrphne input as fllws: GAIN MIC = 100k / R5 6. The gain shuld be such that the resultant utput at the MICFB pin is within the micrphne input signal range specified in Fr ptimum perfrmance with lw signal micrphnes, an additinal external gain stage may be required. 7. C21 and C20 shuld be selected t maintain the lwer frequency rll-ff f the MIC and ALT inputs as fllws: C21 1.0µF GAIN ALT C20 30nF GAIN MIC 8. ALT and ALTFB cnnectins allw the user t have a secnd discriminatr, micrphne input r external sub-audi signalling surce. Cmpnent cnnectins and values are as fr the respective DISC and MIC netwrks. If this input is nt required, the ALT pin shuld be cnnected t AV SS. 9. AUDIO utput is nly used in the Functin Image TM 8341FI-1.x when analgue audi functins are selected. The OUTP digital audi utput is passed thrugh a transmissin gate (TG1), s that it can be turned ff when digital mde is nt selected. 4.2 Reference Clck Frequency The Functin Image TM 8341 FI-1.x is designed t wrk with an external reference clck surce f 19.2MHz, cnnected t the REFCLK pin CML Micrsystems Plc 14 D/8341/7

15 L8 L8 AT25F512AN-10SH-2.7 L8 Digital PMR (dpmr) Baseband Prcessr 4.3 Serial Memry Cnnectins Cnnectins fr a typical 512Kbyte serial memry are shwn belw: DV DD R4 SI EPSI SO EPSO SCK EPSCLK CSN EPSCSN HOLDN WPN DV SS Jumper Figure 3 Serial Memry Cnnectins 4.4 Other Cnnectins MIC ALT DISC C20 R5 R8 C21 C23 R9 R6 R7 C24 R10 MICFB MIC ALTFB ALT DISCFB DISC C25 OUTP MOD1 MOD2 AUDIO TG1 R11 R14 R12 R13 C26 C28 C29 C27 C30 C31 CTRL SPKR MOD1 MOD2 AVSS Figure 4 Other Cnnectins 2014 CML Micrsystems Plc 15 D/8341/7

16 4.5 Autnmus Signal Ruting MIC Cre Baseband Prcessing Analgue prcessing MOD1 ALT MOD2 RALCWI Vcder dpmr Mdem Analgue Mde dpmr DISC AUDIO Ext Sub-audi MUX MUX Figure 5 Tx Ruting Autnmus mde MIC Cre Baseband Prcessing MOD1 ALT dpmr Mdem RALCWI Vcder MOD2 Analgue Mde DISC Analgue Prcessing AUDIO dpmr DAC4 Ext Sub-audi MUX MUX Figure 6 Rx Ruting Autnmus mde 2014 CML Micrsystems Plc 16 D/8341/7

17 5 General Descriptin A blck diagram f the device is shwn in Figure 1. A flexible pwer cntrl facility allws the device t be placed in its ptimum pwersave mde when nt actively prcessing signals. The device includes a reference clck input and prvides 2 x PLL system clck utputs fr general use, if required. 5.1 Prduct Features dpmr Features The 8341FI-1.x Functin Image is intended fr use in half duplex digital PMR equipment using 4FSK mdulatin at 4800bps suitable fr 6.25kHz channel systems. Cmplete dpmr baseband prcessing is prvided, including the RALCWI Vcder functin. Much f the dpmr ETSI TS standard Air Interface prtcl is embedded in the 8341FI-1.x Functin Image peratin namely: Air Interface Physical Layer 1 4FSK mdulatin and demdulatin Bit and symbl definitin Frequency and symbl synchrnisatin Transmissin burst building and splitting Air Interface Data Link Layer 2 Channel cding (FEC, CRC) Interleaving, de-interleaving and bit rdering Frame and superframe building and synchrnising Burst and parameter definitin Link addressing (surce and destinatin) Interfacing f vice applicatins (vice data) with the Physical Layer Data bearer services Exchanging signalling and/r user data with the Call Cntrl Layer Autmatic Own-ID and Grup-ID detectin Analgue PMR Features The device prvides legacy analgue PMR peratin including: Cmplete vice prcessing 300Hz HPF 12.5kHz channel filter 25kHz channel filter Hard Limiter with anti-splatter filter Cmpandr Scrambler Vice AGC Level adjust Inband Tne generatin External Sub-audi filtering Internal sub-audi (CTCSS and DCS) generatin and detectin 2014 CML Micrsystems Plc 17 D/8341/7

18 The selectin f these Analgue prcessing mdes is cntrlled by the Analgue Mde bits in the Mdem Cntrl register, $C1:b Universal PMR Functins These include: RAMDAC peratin TxEnable (TXENA) and Rx Enable (RXENA) hardware signals Tw-pint mdulatin utputs Hard r sft data utput ptins Embedded RALCWI Vcder Auxiliary Functins Tw prgrammable system clck utputs Tw auxiliary ADCs with fur selectable external input paths Fur auxiliary DACs, ne with built-in prgrammable RAMDAC GPIO pins System Interface Optimised C-BUS (4-wire high-speed synchrnus serial cmmand/data bus) interface t hst fr cntrl and data transfer Open drain IRQ t hst Serial memry bt mde C-BUS (hst) bt mde 5.2 Aspects f System Design dpmr Data Transfer When transmitting, an initial blck f paylad r cntrl channel data will need t be laded frm the hst int the C-BUS TxData registers. The can then frmat and transmit that data while at the same time lading in the fllwing data blcks frm the hst r the Vcder sectin. When receiving, the hst needs t cnsider that when a signal is received ver the air there will be a prcessing delay while the filters, demdulates and decdes the utput data befre presenting it t the hst r the Vcder sectin. Fr the best perfrmance, vice paylad data can be utput in sftdecisin (4-bit lg-likelihd rati) frmat, cmpatible with the Vcder sectin, althugh this mde increases the data transfer rate ver C-BUS by a factr f fur RSSI Measurement The AuxADC prvided by the can be used t detect the Squelch r RSSI signal frm the RF frnt-end while the device is in Rx r Idle mde. This allws a significant degree f pwersaving within the and avids the need t wake the hst up unnecessarily. The hst prgrammable AuxADC threshlds allw fr user selectin f squelch threshld settings Serial Memry Cnnectin A Serial Memry interface with a dedicated chip select pin (EPSCSN) cnnects the external serial memry, which may be used t hld the cntents f the Functin Image, t the CML Micrsystems Plc 18 D/8341/7

19 6 dpmr Mdem Descriptin This mdem is set t run at 4800bps, ccupying a 6.25kHz bandwidth RF channel. It has been designed such that, when cmbined with suitable RF, hst cntrller and apprpriate cntrl sftware, it meets the requirements f the EN standards. See fr details f these standards. TS is available n the ETSI web site ( which describes a 6.25kHz channel spacing FDMA dpmr system. This standard uses a 4FSK mdulatin scheme with an ver-air bit rate f 4800bps (ie symbls per secnd). With respect t dpmr frmatted mdes f peratin, this dcument shuld be read in cnjunctin with the ETSI standard. The dpmr standard des nt specify a vice cding algrithm: the RALCWI Vcder in the is suitable fr this purpse. Versin f TS sectin 5.16 intrduces tw additinal vcder cntrl bits which specify which vcder is in use fr a particular vice call. These additinal bits are supprted by the 8341FI-1.x Functin Image and shuld be set apprpriately by the hst. These have been further defined by the dpmr Assciatin as: Versin Vcder ======= ======= 00 AMBE+2 01 T be selected by Chinese DRA 10 RALCWI 11 Manufacturer defined 6.1 Mdulatin The dpmr 4FSK mdulatin scheme as defined in TS sectin 12 perates in a 6.25kHz channel bandwidth with a deviatin index f 0.29 and has an ver-air bit rate f 4800bps (2400 symbls per secnd). RRC filters are implemented in bth Tx and Rx with a filter alpha f 0.2. The maximum frequency errr is +/-625Hz and the can adapt t the maximum time-base clck drift f 2ppm ver the duratin f a 180-secnd burst. Figure 9 shws the basic parameters f the 4FSK mdulatin, symbl mapping and filtering requirements. Figure 7 and Figure 8 shw a transmitted PRBS wavefrm, as recrded n a spectrum analyser in 36k span and zer-span mde, having been tw-pint mdulated using a suitable RF transmitter CML Micrsystems Plc 19 D/8341/7

20 R e f L v l 3 0 d B m 2. 5 k 3 0 d B O f f s e t 2 k M a r k e r 1 [ T 1 ] F M m s H z C F M H z D E M O D B W : k H z R e a l T i m e O F F A F - S i g n a l F M [ H z ] 1 [ T 1 ] m s F M H z A 1. 5 k 1 k D k H z 1 V I E W k D k H z k - 2 k k S T A R T 0 s S T O P 3 5 m s D a t e : Figure 7 4FSK PRBS Wavefrm - Mdulatin M a r k e r 1 [ T 1 ] R e f L v l d B m 3 0 d B m M H z d B O f f s e t R B W H z R F A t t 2 0 d B V B W 1 k H z S W T 1 8 s U n i t d B m 1 [ T 1 ] d B m M H z C H P W R d B m A C P U p d B A C P L w d B A L T 1 U p d B A L T 1 L w d B A 1 R M c l 2 c l 2 c l 1 c l 1 C 0 C 0 c u 1 c u 1 c u 2 c u C e n t e r M H z 3. 6 k H z / S p a n 3 6 k H z D a t e : Figure 8 4FSK PRBS Wavefrm - Spectrum 2014 CML Micrsystems Plc 20 D/8341/7

21 *Tx Baseband Filter Infrmatin bits input H(f ) Filter Frequency Mdulatr 4FSK Output H( f ) = 1 cs[(t / 4α)(2π f -π( 1 - α)/t] 0,,, 0 f < (1 - α) / 2T (1 - α) / 2T f < (1 + α) / 2T (1 + α) / 2T f α = 0.2 T = 1/ FSK Deviatin Di-bit Symbl Deviatin Hz Hz -350Hz -1050Hz *Rx Baseband Filter FM IF signal Frequency Demd H(f ) Filter D(f ) Filter Infrmatin bits utput H( f ) = 1 cs[(t / 4α)(2π f -π( 1 - α)/t] 0,,, 0 f < (1 - α) / 2T (1 - α) / 2T f < (1 + α) / 2T (1 + α) / 2T f π f T D( f ) = sin (π f T) α = 0.2 T = 1/2400 Figure 9 dpmr Mdulatin Characteristics 6.2 Internal Data Prcessing The perates as a half-duplex device, either receiving signals frm the RF circuits in Rx mde, r surcing signals t the RF circuits in Tx mde. It als has a lw pwer Idle mde t supprt battery saving prtcls. The internal data prcessing blcks fr Tx and Rx mdes are illustrated in Figure CML Micrsystems Plc 21 D/8341/7

22 C-BUS Prt Data Buffer Frame Type Detect FEC Interleave Scramble Packet Frmatter I/Q Lk-up Cntrl inf Data Ruter 4-FSK Mdulatr Filter Mux MOD1 utput Vcder Vice data MOD2 utput Vcder Input DISC input Filter 4-FSK Demd Frame Type Detect Packet Defrmatter De-interleave De-scramble De-FEC Vice data Vcder AFSD Address Matcher Data Ruter Cntrl inf Data Buffer C-BUS Prt Figure 10 Internal Data Prcessing Blcks 6.3 Frame Sync Detectin and Demdulatin The analgue signal frm the limiter/discriminatr f the external RF sectin shuld be applied t ne f the inputs (nrmally the DISC input) where it can be adjusted t the crrect level either by selectin f the feedback resistr r using the Input Gain settings. The signal is filtered using a Rt-Raised Csine filter and Inverse Rx Sinc filter matching the filters applied in the transmitter, then passed t the AFSD (Autmated Frame Sync Detectr) blck which extracts symbl and frame synchrnisatin. During this prcess the 4FSK demdulatr and the fllwing data-prcessing sectins are drmant t minimise pwer cnsumptin. When frame synchrnisatin has been achieved the AFSD sectin is pwered dwn, and timing and symbl-level infrmatin is passed t the 4FSK demdulatr which starts decding the subsequent data bits. The can detect the end f a call by scanning the received cntrl channel fields and will autmatically disable the demdulatr and restart frame sync search when required withut hst interventin. A dpmr call begins with a 72-bit (r lnger) preamble sequence fllwed by an 80ms Header Frame, which cntains a 48-bit frame sync (FS1 r FS4). Subsequent paylad frames cntain either a 24-bit frame sync (FS2) r a 24-bit Clur Cde. The can scan fr all dpmr frame syncs cncurrently. It uses FS1 t detect the start f a transmissin and this is reprted t the hst by setting the FS1 Detect bit in the IRQ Status register. It can als ptinally use FS2 t perfrm a late entry int an existing call, reprted by setting the FS2 Detect bit. The shrt length f FS2 gives a higher prbability f false detectins, s by default the will nly generate an FS2 Detect if tw successive FS2 frame syncs are detected at the crrect frame spacing in the received signal. The frame syncs and Preamble defined in TS are always used. When frame synchrnisatin has been achieved and the 4FSK demdulatr is enabled, frame sync detectin is switched ff and any subsequent frame sync sequences embedded in the received data are nt reprted t the hst CML Micrsystems Plc 22 D/8341/7

23 Table 3 dpmr Frame Frmat - Call set-up, n ACK Bit n press PTT Header Tx Preamble FS1 Header Inf 0 CC Header Inf 1 Frame 1 Tx FS2 CCH Paylad Paylad Paylad Paylad Frame 2 Tx CC CCH Paylad Paylad Paylad Paylad Frame 3 Tx FS2 CCH Paylad Paylad Paylad Paylad Frame 4 Tx CC CCH Paylad Paylad Paylad Paylad Frame 1 Tx FS2 CCH Paylad Paylad Paylad Paylad Frame 2 Tx CC CCH Paylad Paylad Paylad Paylad Frame 3 Tx FS2 CCH Paylad Paylad Paylad Paylad Frame 4 Tx CC CCH Paylad Paylad Paylad Paylad Tx Repeat frames 1 t 4 until PTT released. End Tx FS3 End Flag Table 4 dpmr Frame Frmat - Call set-up with ACK Bit n press PTT Header Tx Preamble FS1 Header Inf 0 CC Header Inf 1 End Tx FS3 End Flag Ack Rx Preamble FS1 Header Inf 0 CC Header Inf 1 Header Tx Preamble FS1 Header Inf 0 CC Header Inf 1 Frame 1 Tx FS2 CCH Paylad Paylad Paylad Paylad Frame 2 Tx CC CCH Paylad Paylad Paylad Paylad Frame 3 Tx FS2 CCH Paylad Paylad Paylad Paylad Frame 4 Tx CC CCH Paylad Paylad Paylad Paylad Frame 1 Tx FS2 CCH Paylad Paylad Paylad Paylad Frame 2 Tx CC CCH Paylad Paylad Paylad Paylad Frame 3 Tx FS2 CCH Paylad Paylad Paylad Paylad Frame 4 Tx CC CCH Paylad Paylad Paylad Paylad Tx Repeat frames 1 t 4 until PTT released. End Tx FS3 End Flag 2014 CML Micrsystems Plc 23 D/8341/7

24 Rx enabled AFSD active 4FSK drmant AFSD prcess n FS2 detected? FS1 detected? n IRQ FS2 IRQ FS1 AFSD ff 4FSK active AFSD ff 4FSK active Demdulate Demdulate n CC detected? n FS2 detected? IRQ FS2 Analyse CCH data decde, de-interleave Analyse HDR data decde, de-interleave n ID & CC matched? ID & CC matched? n IRQ Called IRQ DataRDY (HDR + LE) IRQ Called IRQ DataRDY (HDR) Enable Vcder Transfer data t Vcder Prcess data n END detected? IRQ DataRDY (END) Disable Vcder Figure 11 FS Detectin 2014 CML Micrsystems Plc 24 D/8341/7

25 6.4 FEC and Cding The implements all CRCs, Hamming cdes, interleaving and scrambling required by the dpmr standard. CRC failures in cntrl channel fields and cded data blcks are indicated t the hst by issuing an Event IRQ with a crrespnding errr cde in the Mdem Status register, $C9. This relieves the hst f a substantial prcessing lad and has the added advantage f reducing the cmplexity and timing cnstraints f interfacing between the hst and the. The dpmr Header Frame frmat cntains duplicate cpies f all cntrl channel fields (in the HI0 and HI1 Header Infrmatin blcks) but nly ne decded cpy f each field will be presented back t the hst. On receiving a Header Frame, the decdes bth HI blcks, checks CRCs and can accept the call if either blck is valid (the ther HI blck is discarded). 6.5 Vice Cding The cntains a RALCWI vcder. The uses the Serial Memry Interface prt (shared with the bt serial memry) t issue cntrl cmmands and transfer vice paylad data directly t the Vcder sectin. Vice data transferred t the Vcder sectin in Rx mde always uses sft decisin (4-bit lg-likelihd rati) frmat. This ptin is als available fr vice paylad data ruted t the hst (Tx mde), althugh it increases the required data transfer rate ver C-BUS by a factr f fur. 6.6 Radi Perfrmance Requirements The demdulatr is designed t prcess a 4FSK signal frm a limiter/discriminatr surce. Fr ptimum perfrmance the signal shuld nt be significantly degraded by filters that are excessively narrw and/r cause significant grup delay distrtin. Care shuld be taken in interfacing the device t the radi circuits t maintain the frequency and phase respnse (bth lw and high end), in rder t achieve ptimum perfrmance. Test mdes are prvided t assist in bth the initial design and prductin set-up prcedures. Further infrmatin and applicatin ntes can be fund at Tne Generatr This allws the user t generate audi tnes in the range 300Hz t 3kHz. It will default t 1kHz. A separate level cntrl is prvided. C-BUS register $C3 is available fr setting the tne frequency (shared with ther functins). 7 Analgue PMR Descriptin 7.1 External Sub-Audi Prcessing An external Sub-Audi prcessing path is available fr the hst t generate r detect sub-audi tnes. In Tx, sub-audi tnes applied t the ALT input are filtered and then summed with the in-band signal and presented t the MOD1 and MOD2 utputs. In Rx, the sub-audi tnes are separated by filters frm the received signal applied t the DISC input. The sub-audi signal is then ruted t the Auxiliary DAC4 utput. The filter used in the path can be set by the Prgramming register, either a 260Hz Chebyshev suitable fr CTCSS r a 150Hz 4-ple Bessel fr DCS. 7.2 Internal CTCSS and DCS Generatin and Detectin An internal generatr/detectr is available fr the 51 CTCSS tnes shwn in Table 6 and the 83 DCS cdes shwn in Table 5. Squelch-tail eliminatin is prvided by inverting the MOD utputs in CTCSS mde r a 134Hz turn-ff tne in DCS mde. The tne/cde t be generated is set by the value in the AuxData/Sub-Audi write register ($C2) in Tx mde and read frm the AuxData/Sub-Audi read register ($CC) in Rx mde (see sectin ). The use f the internal generatr/detectr is determined by Prgram Blck P2.0 b5 and b4 (see sectin ) CML Micrsystems Plc 25 D/8341/7

26 7.3 Vice Prcessing: A set f Audi Prcessing blcks are available fr use in Analgue mde: 300Hz HPF 12.5kHz channel filter r 25kHz channel filter Hard Limiter with anti-splatter filter Cmpandr Scrambler Vice AGC Level adjust In-band audi generatr/s in bth Rx and Tx paths The 12.5kHz channel filter will be selected by default, the 25kHz filter can be enabled by setting P2.0:b0. Nte that in analgue mde, the digital mde utput f the Vcder sectin shuld be islated using an external analgue switch (see Figure 4). 300Hz HPF This is designed t reject signals belw 300Hz frm the vice path s that sub-audi signalling can be inserted (in Tx) r remved (in Rx) as apprpriate. It shuld be enabled whenever sub-audi signalling is required. 12.5kHz/25kHz Channel Filters These are designed t meet the requirements f ETSI EN fr Vice signal prcessing and feature an upper rll-ff at 2.55 and 3.0kHz respectively. Hard Limiter This is prvided t limit the peak deviatin f the radi signal t meet the requirements f ETSI EN An anti-splatter filter is included t reduce the effects f any harmnic signals generated in the prcess. The limiter threshld can be set using P2.3. Cmpander A syllabic cmpressr/expander is prvided, similar t that used in the 7031/7041-FI-1.x t increase the dynamic range f the Vice signal. The unity gain pints fr Tx and Rx can be set independently using P2.9 and P2.10. Scrambler A frequency inversin scrambler is prvided t enable a basic level f privacy. The default inversin frequency is 3300Hz, but can be prgrammed using $CD:1001 b, hwever sme lss f signal at the band edges may ccur due t the channel filter rll-ff. Vice AGC An autmatic gain cntrl system is prvided in the vice path, utilising the prgrammable gain settings f the Input 1 amplifier. When used in cnjunctin with the hard limiter functin, this can cmpensate fr large variatins in the MIC input signal withut intrducing significant distrtin. The AGC threshld is prgrammable using P21. whilst the maximum gain setting and the decay time can be set using P2.2. When this feature is enabled, the hst shuld nt attempt t directly cntrl the Input 1 gain setting. Level Adjust Independent level adjustments are prvided using $C3 register fr the vice, in-band and sub-audi signals, see sectin 8.12 fr further details CML Micrsystems Plc 26 D/8341/7

27 db (ref 1kHz) db (ref 1kHz) Digital PMR (dpmr) Baseband Prcessr $C1=$8301, narrw $C1=$8301, wide template frequency (Hz) Figure 12 Rx Audi Respnse $C1=$8302, narrw $C1=$8302, wide template frequency (Hz) Figure 13 Tx Audi Respnse 2014 CML Micrsystems Plc 27 D/8341/7

28 db (ref 1kHz) Digital PMR (dpmr) Baseband Prcessr $C1=$A302, DCS template $C1=$A302, CTCSS frequency (Hz) Figure 14 CTCSS and DCS filters Table 5 DCS cdes and values Register Value Register Value DCS Cde true inverted DCS Cde true inverted Decimal Hex Decimal Hex Decimal Hex Decimal Hex n cde A 142 8E B 143 8F C D E F A B C D A 110 6E B 111 6F C A D B E C F D A 158 9E B 159 9F C 160 A CML Micrsystems Plc 28 D/8341/7

29 Register Value Register Value DCS Cde true inverted DCS Cde true inverted Decimal Hex Decimal Hex Decimal Hex Decimal Hex D 161 A E 162 A F 163 A A A B A C A D A A 126 7E A B 127 7F A C AA D AB E AC F AD A 174 AE B 175 AF C 176 B D 177 B E 178 B F 179 B A B B B C B D B7 user defined B CML Micrsystems Plc 29 D/8341/7

30 Table 6 CTCSS cdes and values Register Value CTCSS tne Register Value CTCSS tne Decimal Hex Frequency Decimal Hex Frequency 200 C8 n tne 228 E C E CA E CB E CC E CD E CE EA CF EB D EC D ED D EE D EF D F D F D F D F D F D F DA F DB F DC F DD F DE FA DF FB E FC user defined 225 E FD E FE DCS turn-ff 227 E FF invalid tne 2014 CML Micrsystems Plc 30 D/8341/7

31 8 Detailed Descriptins 8.1 Reference Frequency This device is suitable fr use with a 19.2MHz external frequency surce nly. 8.2 Hst Interface A serial data interface (C-BUS) is used fr cmmand, status and data transfers between the and the hst µc; this interface is cmpatible with micrwire and SPI. Interrupt signals ntify the hst µc when a change in status has ccurred and the µc shuld read the status register acrss the C-BUS and respnd accrdingly. Interrupts nly ccur if the apprpriate mask bit has been set. See sectin The will mnitr the state f the C-BUS registers that the hst has written-t every 250µs (the C-BUS latency perid) hence it is nt advisable fr the hst t make successive writes t the same C-BUS register within this perid C-BUS Operatin This blck prvides fr the transfer f data and cntrl r status infrmatin between the s internal registers and the hst µc ver the C-BUS serial interface. Each transactin cnsists f a single address byte sent frm the µc which may be fllwed by ne r mre data byte(s) sent frm the µc t be written int ne f the s write nly registers, r ne r mre data byte(s) read ut frm ne f the s read nly registers, as shwn in Figure 15. Data sent frm the µc n the CDATA (Cmmand Data) line is clcked int the n the rising edge f the SCLK (Serial Clck) input. RDATA (Reply Data) sent frm the t the µc is valid when the SCLK is high. The CSN line must be held lw during a data transfer and kept high between transfers. The C-BUS interface is cmpatible with mst cmmn µc serial interfaces. The number f data bytes fllwing an address byte is dependent n the value f the Address byte. The mst significant bit f the address r data is sent first. Fr detailed timings see sectin Nte that, due t internal timing cnstraints, there may be a delay f up t 250µs between the end f a C-BUS write peratin and the device reading the data frm its internal register CML Micrsystems Plc 31 D/8341/7

32 C-BUS Write: CSN See Nte 1 See Nte 2 SCLK CDATA MSB LSB MSB LSB MSB LSB Address/Cmmand byte Upper 8 bits Lwer 8 bits RDATA High Z state C-BUS Read: CSN See Nte 2 SCLK CDATA MSB LSB Address byte Upper 8 bits Lwer 8 bits RDATA High Z state MSB LSB MSB LSB Data value unimprtant Repeated cycles Either lgic level valid (and may change) Either lgic level valid (but must nt change frm lw t high) Figure 15 C-BUS Transactins Ntes: 1. Fr Cmmand byte transfers nly the first 8 bits are transferred ($01 = Reset). 2. Fr single byte data transfers nly the first 8 bits f the data are transferred. 3. The CDATA and RDATA lines are never active at the same time. The Address byte determines the data directin fr each C-BUS transfer. 4. The SCLK input can be high r lw at the start and end f each C-BUS transactin. 5. The gaps shwn between each byte n the CDATA and RDATA lines in the abve diagram are ptinal, the hst may insert gaps r cncatenate the data as required CML Micrsystems Plc 32 D/8341/7

33 8.3 Functin Image Lading The Functin Image (FI), which defines the peratinal capabilities f the device, may be btained frm the CML Technical Prtal, fllwing registratin. This is in the frm f a 'C' header file which can be included int the hst cntrller sftware r prgrammed int an external serial memry. The maximum pssible size f Functin Image TM is 46 kbytes, althugh a typical FI will be less than this. Nte that the BOOTEN pins are nly read at pwer-n r fllwing a C-BUS General Reset and must remain stable thrughut the FI lading prcess. Once the FI lad has cmpleted, the BOOTEN pins are ignred by the until the next pwer-up r C-BUS General Reset. The BOOTEN pins are bth fitted with internal lw current pull-dwn devices. Fr C-BUS lad peratin, bth pins shuld be pulled high by cnnecting them t DV DD either directly r via a 220kΩ resistr (see Figure 16). Fr serial memry lad, nly BOOTEN1 needs t be pulled high in a similar manner, hwever, if it is required t prgram the serial memry in-situ frm the hst, either a jumper t DV DD r a link t a hst I/O pin shuld be prvided t pull BOOTEN2 high when required (see Figure 17). The Serial Memry Interface als cntrls the Vcder sectin using a separate chip select (SSOUT) pin. During bt peratins the SSOUT will be disabled. Once the bt peratin has cmpleted, the serial memry chip select (EPCSN) will be disabled and the SSOUT will becme peratinal. Once the FI has been laded, the perfrms these actins: (1) The prduct identificatin cde ($8341) is reprted in C-BUS register $C5 (2) The FI versin cde is reprted in C-BUS register $C9 (3) The tw 32-bit FI checksums are reprted in C-BUS register pairs $A9, $AA and $B8, $B9 (4) The device waits fr the hst t lad the 32-bit Device Activatin Cde t C-BUS register $C8 (5) Once activated, the device initialises fully, enters idle mde and becmes ready fr use, and the PRG flag (bit 0 f the Status register) will be set. The checksums shuld be verified against the published values t ensure that the FI has laded crrectly. Once the FI has been activated, the checksum, prduct identificatin and versin cde registers are cleared and these values are n lnger available. If an invalid activatin cde is laded, the device will reprt the value $DEAD in register $A9 and must be pwer cycled befre an attempt is made t re-lad the FI and re-activate. Bth the Device Activatin Cde and the checksum values are available frm the CML Technical Prtal. Table 7 BOOTEN Pin States BOOTEN2 BOOTEN1 C-BUS Hst lad 1 1 reserved 1 0 Serial memry lad 0 1 N FI lad 0 0 Nte: In the rare event that a General Reset needs t be issued withut the requirement t re-lad the FI, the BOOTEN pins must bth be cleared t '0' befre the cmmand is issued. The Checksum values will be reprted and the Device Activatin cde will need t be sent in a similar manner as that shwn in Figure 17. There will nt be any FI lading delay. This assumes that a valid FI has been previusly laded and that DV DD has been maintained thrughut the reset t preserve the data CML Micrsystems Plc 33 D/8341/7

34 8.3.1 FI Lading frm Hst Cntrller The FI can be included int the hst cntrller sftware build and dwnladed int the at pwerup ver the C-BUS interface. The BOOTEN pins must be set t the C-BUS lad cnfiguratin, the pwered up and placed int Prgram Mde, the data can then be sent directly ver the C-BUS t the. Each time the Prgramming register, $C8, is written, it is necessary t wait fr the PRG flag (IRQ Status register ($C6) b0) t g high befre anther write t $C8. The PRG flag ging high cnfirms the write t the Prgramming register has been accepted. The PRG flag state can be determined by plling the IRQ Status register r by unmasking the interrupt (Interrupt Mask register, $CE, b0). The dwnlad time is limited by the clck frequency f the C-BUS, with a 5MHz SCLK, it shuld take less than 500ms t cmplete CML Micrsystems Plc 34 D/8341/7

35 BOOTEN 2 = 1 BOOTEN 1 = 1 Pwer-up r write General Reset t device Pll $C6 until b0 = 1 (Prgramming mde entered) Cnfigure PRG flag interrupt if required BOOTEN1 and BOOTEN2 may be changed frm this pint n, if required Write Start Blck 1 Address (DB1_ptr) t $B6 Write Blck 1 Length (DB1_len) t $B7 Write $0001 t $C8 Wait fr PRG flag t g high r interrupt Write next data wrd t $C8 Wait fr PRG flag t g high r interrupt Write Start Blck 2 Address (DB2_ptr) t $B6 Write Blck 2 Length (DB2_len) t $B7 Write $0001 t $C8 Wait fr PRG flag t g high r interrupt Write next data wrd t $C8 Wait fr PRG flag t g high r interrupt Write Start Blck 3 Address (ACTIVATE_ptr) t $B6 Write Blck 3 Length (ACTIVATE_len) t $B7 Write $0001 t $C8 Wait fr PRG flag t g high r interrupt Read and verify checksum values in register pair: $A9 and $AA, $B8 and $B9 Send Activatin Cde hi t $C8 Wait fr PRG flag t g high r interrupt Send Activatin Cde l t $C8 Wait fr PRG flag t g high r interrupt Device is nw ready fr use V DD BOOTEN1 BOOTEN2 Figure 16 FI Lading frm Hst 2014 CML Micrsystems Plc 35 D/8341/7

36 8.3.2 FI Lading frm an external Serial Memry The FI must be cnverted int a suitable frmat fr a serial memry prgrammer (nrmally Intel Hex) and laded int the external serial memry either by the hst r an external prgrammer. The needs t have the BOOTEN pins set t serial memry lad and then n pwer-n, r fllwing a C-BUS General Reset, the will autmatically lad the data frm the serial memry withut interventin frm the hst cntrller. BOOTEN 2 = 0 BOOTEN 1 = 1 Pwer-up r write General Reset t device Pll $C6 until b0 = 1 (FI laded) Cnfigure PRG flag interrupt if required BOOTEN1 and BOOTEN2 may be changed frm this pint n, if required Read and verify checksum values in register pair: $A9 and $AA, $B8 and $B9 Send Activatin Cde hi t $C8 Wait fr PRG flag t g high r interrupt Send Activatin Cde l t $C8 Wait fr PRG flag t g high r interrupt Device is nw ready fr use Vdd BOOTEN1 BOOTEN2 Jumper fr prgramming serial memry (if required) Figure 17 FI Lading frm an external Serial Memry The has been designed t functin with either an Atmel AT25HP512 serial EEPROM r the AT25F512 Serial Flash device 1, hwever ther manufacturers parts may als be suitable. The time taken t lad the FI is dependent n the clck frequency: with a 19.2MHz reference clck it shuld lad in less than 1/3 rd secnd. 1 Nte that these tw devices have slightly different addressing schemes. The is cmpatible with bth schemes CML Micrsystems Plc 36 D/8341/7

37 8.4 Device Cntrl The can be set int the relevant mde t suit its envirnment. These mdes are described in the fllwing sectins and are prgrammed ver the C-BUS: either directly t peratinal registers r, fr parameters that are nt likely t change during peratin, via the Prgramming register ($C8). Fr basic peratin: (1) Enable the relevant hardware sectins via the Pwer Dwn Cntrl register (2) Set the apprpriate mde registers t the desired state (3) Select the required Signal Ruting and Gain (4) Use the Mde Cntrl register t place the device int Rx r Tx mde. T cnserve pwer when the device is nt actively prcessing a signal, place the device int Idle mde. This will als cmmand the Vcder sectin t enter pwersaving mde as well. Additinal pwersaving can be achieved by disabling any unused hardware blcks, hwever, care must be taken nt t disturb any sectins that are autmatically cntrlled. Nte that the BIAS blck must be enabled t allw any f the Input r utput blcks t functin. See: Pwer Dwn Cntrl - $C0 write Mdem Cntrl - $C1 write Mdem Cnfiguratin - $C7 write General Ntes In nrmal peratin, the mst significant registers, in additin t the TxData and RxData blcks, are: Mdem Cntrl - $C1 write IRQ Status - $C6 read Analgue Output Gain - $B0 write Input Gain and Signal Ruting - $B1 write AuxData/Sub-audi Write - $C2 write Analgue Cntrl - $C3 write Setting the Mde register t either Rx r Tx will autmatically increase the internal clck speed t its peratinal speed and bring the Vcder sectin ut f its pwersave mde, whilst setting the Mde register t Idle will autmatically return the internal clck t a lwer (pwersaving) speed. T access the Prgram Blcks (thrugh the Prgramming register, $C8) the device MUST be in Idle mde. Under nrmal circumstances the manages the Main Clck Cntrl autmatically, using the default values laded in Prgram Blck Interrupt Operatin The will issue an interrupt n the IRQN line when the IRQ bit (bit 15) f the IRQ Status register and the IRQ Mask bit (bit 15) are bth set t 1. The IRQ bit is set when the state f the interrupt flag bits in the IRQ Status register change frm a 0 t 1 and the crrespnding mask bit(s) in the Interrupt Mask register is(are) set. Enabling an interrupt by setting a mask bit (01) after the crrespnding IRQ Status register bit has already been set t 1 will als cause the IRQ bit t be set. All interrupt flag bits in the IRQ Status register, except the PRG flag (bit 0), are cleared and the interrupt request is cleared fllwing the cmmand/address phase f a C-BUS read f the IRQ Status register. The PRG flag bit is set t 1 nly when it is permissible t write a new wrd t the Prgramming register. See: IRQ Status - $C6 read Interrupt Mask - $CE write 2014 CML Micrsystems Plc 37 D/8341/7

38 8.4.3 Signal Ruting The ffers a flexible ruting architecture, with three signal inputs, a chice f tw mdulatr cnfiguratins (t suit 2-pint mdulatin r I/Q schemes) and a single audi utput. See: Input Gain and Signal Ruting - $B1 write Mdem Cntrl - $C1 write Mdem Cnfiguratin - $C7 write The analgue gain/attenuatin f each input and utput can be set individually. In dpmr mde, the Mic and Speaker gains are set by the Vcder sectin, which is cntrlled thrugh the Analgue Cntrl - $C3 write register. In Analgue mde, the Mic and Speaker gains are set by the Input Gain and Output Gain registers ($B1 and $B0). See: Analgue Output Gain - $B0 write (Tx MOD1 and 2) Input Gain and Signal Ruting - $B1 write (Rx DISC input, Tx MOD1 and 2) Analgue Cntrl - $C3 write (Vcder sectin Mic. and Speaker) Input 1 shuld be ruted t either f the three input surces (ALT, DISC r MIC), which shuld be cnnected as shwn in Figure 5 and Figure 6. The internal signals Output 1 and Output 2 are used t prvide 2-pint signals and shuld be ruted t the MOD1 and MOD2 pins, as required. In dpmr mde the micrphne and speaker paths are autmatically re-ruted t the Vcder sectin, when apprpriate. This ruting is cntrlled by the data field in the Header Blck, which indicates whether the paylad is speech data, and the Vcder sectin Disable bit in the Mdem Cntrl register, $C Mdem Cntrl The perates in ne f these peratinal mdes: Idle Rx Tx Pass-thrugh, fr direct Vcder access. At pwer-n r fllwing a Reset, the device will autmatically enter Idle mde, which allws maximum pwersaving whilst still retaining the capability f mnitring the AuxADC inputs (if enabled). It is nly pssible t write t the Prgramming register whilst in Idle mde. By default, the selects Digital (dpmr Mdem) mde, unless any f the Vice, Tne r Sub-Audi bits (b15-13) f the Mdem Cntrl register have been set t 1, in which case Analgue mde is selected. See: Mdem Cntrl - $C1 write GPIO1 and GPIO2 pins (allcated t RXENA and TXENA functins by the FI) reflect bits 0 and 1 f the Mdem Cntrl register, as shwn in Figure 7. These can be used t drive external hardware withut the hst having t intervene. There are tw additinal GPIO pins (GPIOA and GPIOB) that are prgrammable under hst cntrl CML Micrsystems Plc 38 D/8341/7

39 Table 8 Mdem Mde Selectin Mdem Cntrl GPIO2 - GPIO1 - Mdem Mde ($C1) b3-0 TXENA RXENA 0000 Idle Lw Pwer Mde Rx Tx reserved x x 0100 Vcder sectin Pass-thrugh reserved x x 0110 reserved x x 0111 reserved x x 1xxx reserved x x The Pass-thrugh mde is used t cntrl and mnitr the Vcder sectin directly. This cannt be accessed if the is in Rx r Tx mdes. This mde will transfer data t/frm the TxData0/RxData0 register t the Vcder sectin C-BUS register address specified in the Prgramming register ($C8). See sectin The Mdem Cntrl bits are ignred in this mde. Table 9 Mdem Cntrl Selectin 4FSK Mdem Cntrl ($C1) b7-4 Rx Tx 0000 Rx Idle Tx Idle 0001 Rx 4FSK Frmatted Tx 4FSK Frmatted 0010 Rx 4FSK Raw reserved 0011 Rx 4FSK EYE Tx 4FSK PRBS 0100 Rx Pass-thrugh Tx 4FSK Preamble 0101 reserved Tx 4FSK Md Set-up 0110 Sync Test 0111 Reset/Abrt Reset/Abrt 1xxx reserved reserved The Mdem Mde bits and the Mdem Cntrl bits shuld be set tgether in the same C-BUS write. Analgue mde is selected by setting any f bits Fr digital mdem peratin, b15-13 MUST be cleared t 0. In Tx mde, the perates in dpmr Frmatted mde. The first blck f cntrl channel r paylad data shuld be laded int the C-BUS TxData registers befre executing the mde change. A DataReady IRQ will be issued when the registers have been read by the and the hst can then supply further blcks f paylad data. When all paylad data has been transmitted, the will issue a TxDne IRQ and the hst can then reset the Mde bits t either Rx r Idle as required. In Rx mde, the received signal shuld be ruted thrugh Input1 (DISC). In dpmr Frmatted mde, the will first search fr frame synchrnisatin and, when this has been achieved, the fllwing data is demdulated and supplied t the hst thrugh the RxData registers. A DataReady IRQ indicates when each new blck becmes available. In dpmr Frmatted mde, the mdem can detect the end f a call and restart frame sync search autmatically. 8.5 dpmr Frmatted Operatin The perfrms all frame building/splitting and FEC cding/decding, which relieves the hst cntrller f a significant prcessing lad. During vice calls the can autmatically enable and 2014 CML Micrsystems Plc 39 D/8341/7

40 cntrl the Vcder sectin, and transfer vice paylad data frm/t it withut hst interventin. In Rx mde, the mnitrs address fields in incming transmissins and nly accepts calls if the prgrammed address requirements are satisfied. This allws the hst t remain in a pwer-dwn r sleep state until it is really necessary t wake up, extending the battery life f the final prduct design Tx Mde In Tx mde peratin ($C1, Mdem Cntrl = $0012), the preamble and frame sync are transmitted autmatically and data frm the TxData Blck is then frmatted and assembled fr transmissin, until the mde is changed t Rx, Pass-thrugh r Idle. The first blck f data shuld be laded int the TxData registers befre executing the Mdem Mde change t Tx. Data is transmitted msb (mst significant bit) first. The hst shuld write the initial data t the C-BUS TxData registers and then set the Mdem Mde t TxFrmat and the Mde bits t Tx. As sn as the data blck has been read frm the C-BUS TxData registers, the DataRDY IRQ will be asserted and the next blck f data may be laded. The call shuld be terminated by the hst sending an END frame t the device. After the last data bit has left the mdulatr a TxDne IRQ will be issued. At this pint it is nw safe fr the hst t change the Mdem Cntrl and Mdem Mde t Idle ($C1, Mdem Cntrl = $0000) and turn the RF transmitter ff. If the Header frame laded by the hst indicates that a vice call is in prgress, the device will autmatically enable the Vcder and rute encded Vice packets t the mdulatr in preference t any data prvided by the hst ver C-BUS. When the hst lads the END frame, the device will autmatically disable the Vcder Tx Mde (PRBS) In PRBS mde Tx peratin ($C1, Mdem Cntrl = $0032), the preamble and frame sync are transmitted autmatically, fllwed by a PRBS pattern cnfrming t ITU-T O.153 (para 2.1) giving a 511-bit repeating sequence Tx Mde Test In Test mde ($C1 = $0062), simple test wavefrms are generated (defined by the dpmr Assciatin TWG). See sectin CML Micrsystems Plc 40 D/8341/7

41 Tx_Prcess nte: RAMDAC has been enabled Data is in 9 byte blcks Lad data t C-BUS TxDataBlck transactin cunt =0, byte cunt =9 Set Mdem Cntrl t: TxRaw, Mde = Tx Ensure that RAMDAC speed is fast enugh t allw fr hardware and internal prcessing delays nte: Execute RAMDAC up nte: GPIO2 and GPIO1 will change t 01 and the Mdem will transmit the preamble, frame sync and data The hst shuld ensure that any external hardware is als set int Tx mde (if nt autmatically cntrlled by the GPIO pins). N IRQ = DataRdy? yes N mre data t send? IRQ=Errr, Mdem status = Underflw may ccur at this pint, if enabled. nte: yes Lad data t C-BUS TxDataBlck transactin cunt ++, byte cunt =9 N IRQ = TxDne? nte: Due t internal prcessing delays in the filters etc, the Hst shuld wait fr IRQ=TxDne r implement its wn delay t ensure all data has been transmitted. Yes Execute RAMDAC dwn Gt Rx_Prcess Set Mdem Cntrl t Idle: Mde = Idle nte: See Rx_Prcess flw diagram nte: GPIO2 and GPIO1 will change t 11 and the Mdem will drp int Idle mde. The hst shuld ensure that any external hardware is als set int Idle mde (if nt autmatically cntrlled by the GPIO pins). Gt Idle Mde Figure 18 Tx Data Flw 2014 CML Micrsystems Plc 41 D/8341/7

42 8.5.4 Rx Mde In Rx mde peratin ($C1, Mdem Cntrl = $0011), the autmatically starts searching fr frame synchrnisatin. When a valid frame sync sequence is detected, an FS1 Detect r FS2 Detect IRQ is asserted and the data demdulatr is enabled. All fllwing paylad data is laded directly int the C-BUS RxData registers with a DataReady IRQ t indicate when each new blck is available. This cntinues until the END frame is detected r the Mde is changed t Idle r Tx. The hst MUST respnd t each DataReady IRQ befre the RxData registers are verwritten by subsequent paylad data blcks. If sft data mde has been selected, the paylad data is encded in 4-bit lg-likelihd-rati frmat. In this mde the hst must be able t service the DataReady IRQs and RxData registers at fur times the nrmal rate t avid verflw. Alternatively, additinal pwer saving may be achieved by the hst mnitring the Called IRQ instead, which will nly be asserted when the ID match criteria are satisfied. If the recvered Header frame indicates that a Vice call is in prgress, the device will autmatically rute the paylad data t the Vcder in preference t the hst C-BUS Rx Mde dpmr In Rx dpmr mde peratin ($C1, Mdem Cntrl = $0011), the will autmatically start searching fr frame synchrnisatin. When a valid frame sync sequence is detected, an FS detect IRQ is asserted and the data demdulatr is enabled. If the burst is then accepted a Called IRQ is asserted and the first Message Inf r CCH Inf blck is laded int the C-BUS RxData registers with a Data Ready IRQ. If the cntrl channel fields indicate that the burst is a vice call, received paylad data will be sent t the vcder fr decding. Otherwise paylad data is laded int the C-BUS RxData registers with a Data Ready IRQ t indicate when each new blck is available. If sft data mde has been selected, the paylad data is encded in 4-bit lg-likelihd-rati frmat and the hst must be able t service the Data Ready IRQs and RxData registers at fur times the nrmal rate t avid verflw Rx Mde Raw Rx Mde Raw is included t facilitate BER measurements. In this mde ($C1, Mdem Cntrl = $0021), nce a valid frame sync has been detected, all fllwing data received is laded directly int the C-BUS RxData registers. This cntinues until the end f the burst (even if there is n valid signal at the input). On exiting Rx Mde Raw, there may be a DataRdy IRQ pending which shuld be cleared by the hst. Nte that Rx Mde Raw peratin always requires the incming data t be preceded with a valid Preamble and Frame Sync pattern in rder t derive timing infrmatin fr the demdulatr. The device will update the C- BUS RxData registers with Rx paylad data as it becmes available. The hst MUST respnd t the DataRDY IRQ befre the RxData registers are ver-written by subsequent data frm the mdem CML Micrsystems Plc 42 D/8341/7

43 Rx_Prcess nte: RAMDAC has been enabled Data is in 9 byte blcks Set Mdem Cntrl t: RxRaw, Mde = Rx If enabled, IRQ=FrameSync will ccur befre IRQ=DataRdy nte: N nte: GPIO2 and GPIO1 will change t 10, the Mdem will start t lk fr frame sync. The hst shuld ensure that any external hardware is als set int Rx mde (if nt autmatically cntrlled by the GPIO pins). IRQ = DataRdy? yes Lad data frm C-BUS RxDataBlck check transactin cunt and byte cunt An IRQ=DataRdy may still be pending at this pint nte: N mre data t receive? yes Gt Tx_Prcess Set Mdem Cntrl t: RxIdle, Mde = Idle nte: See Tx_Prcess Flw Diagram nte: GPIO2 and GPIO1 will change t 11, and the Mdem will drp int Idle mde. The hst shuld ensure that any external hardware is als set int Idle mde (if nt autmatically cntrlled by the GPIO pins). Gt Idle_Prcess Figure 19 Rx Data Flw Rx Mde Eye In Rx 4FSK EYE mde ($C1 = $0031), the filtered received signal is utput at the MOD1 pin as an eye diagram fr test and alignment purpses. A trigger pulse is utput at the MOD2 pin t allw viewing n a suitable scillscpe. The trigger pulse is generated directly frm the receiver clck surce, nt frm the input signal CML Micrsystems Plc 43 D/8341/7

44 8.5.8 Rx Mde Pass-thrugh Rx Pass-thrugh mde ($C1 = $0041), similar t Rx 4FSK Eye mde, but withut the RRC filter. The typical respnse is: 300Hz -0.6dB 1kHz 0dB (reference) 2kHz -0.7dB 2.5kHz -1.4dB 3kHz -2.4dB 4kHz -4.9dB 6kHz -12.2dB Sync Mde Sync mde ($C1 = $0061), enters cntinuus AFSD Synch search mde. Used fr test/debug nly Reset/Abrt Frm each mde, a Reset/Abrt abrts the current state machine and drps int the crrespnding (Rx r Tx) Idle mde. The nly difference between this and ging directly int the crrespnding Idle mde is that all f the buffers and filters are flushed ut first with Reset/Abrt. In Tx mde a number f test and set-up mdes are prvided t facilitate test and alignment. PRBS (Preamble and Synchrnisatin Wrd are autmatically transmitted first) Cntinuus preamble: a repeating sequence f [ ] symbls Mdulatin set-up: in tw-pint mde, a repeating sequence f eight +3 symbls fllwed by eight -3 symbls, and in I/Q mde a cntinuus sequence f +3 symbls Data Transfer Paylad data is transferred frm/t the hst using blcks f five Rx and five Tx 16-bit C-BUS registers, allwing up t 72 bits (9 bytes) f data t be transferred in sequence, see Table 10. The lwest 8 bits f the register blck are reserved fr a Byte Cunter, Blck ID and a Transactin Cunter. The byte cunt indicates hw many bytes in the data blck are valid and avids the need t perfrm a full five wrd C-BUS read/write if nly a smaller blck f data need t be transferred. Table 10 C-BUS Data Registers C-BUS Address Functin C-BUS Address Functin $B5 Tx data 0-7 and inf $B8 Rx data 0-7 and inf $B6 Tx data 8-23 $B9 Rx data 8-23 $B7 Tx data $BA Rx data $CA Tx data $BB Rx data $CB Tx data $C5 Rx data Bits 7 and 6 hld the Transactin Cunter, which is incremented mdul 4 n every read/write f the Data Blck t allw detectin f data underflw and verflw cnditins. In Tx mde the hst must increment the cunter n every write t the TxData blck and, if the identifies that a blck has been written ut f sequence, the Event bit (C-BUS register $C6, b14) will be asserted and an IRQ raised, if enabled. The device detects that new data frm the hst is available by the change in the value f the Transactin Cunter, therefre the hst shuld ensure that all the data is available in the TxData blck befre updating this register (ie, it shuld be the last register the hst writes t in any blck transfer). In Rx mde, the will autmatically increment the cunter every time it writes t the RxData blck. If the hst 2014 CML Micrsystems Plc 44 D/8341/7

45 identifies that a blck has been written ut f sequence, then it is likely that a data verrun cnditin has ccurred and sme data has been lst Vcder Sectin Pass-thrugh Mde T allw the hst t cmmunicate directly with the Vcder sectin fr test and cnfiguratin purpses, a Pass-thrugh mde is available which allws any Vcder sectin C-BUS register t be read r written (as apprpriate). This mde uses the Mdem Cntrl, TxData0, RxData0, IRQ Status and Prgram Blcks n the. T write t the Vcder sectin: Set the t 'Pass-thrugh' mde (Mdem Cntrl register, $C1=$0004) Wait fr the PRG flag t be set ($C6 b0) Write the Vcder sectin data value t the Txdata0 register ($B5) Write the Vcder sectin C-BUS address t the Prgramming register ($C8) with b15=0 and b14=1 Wait fr the PRG flag t be set ($C6 b0). T read frm the Vcder sectin: Set the t 'Pass-thrugh' mde (Mdem Cntrl register, $C1=$0004) Wait fr the PRG flag t be set ($C6 b0) Write the Vcder sectin C-BUS address t the Prgramming register ($C8) with b15=1 and b14=1 Wait fr the PRG flag t be set ($C6 b0) Read the Vcder sectin data value frm the RxData0 register ($B8). Vcder sectin C-BUS addresses are all 8 bits lng and shuld be written t bits 0-7 f the Prgramming register. Bit 15 is the read/write flag (1 = read, 0 = write) and bit 14 is the register-size flag (0 = 16-bit, 1 = 8-bit). Unused bits shuld be cleared t zer. When an 8-bit register is read r written, the data ccupies the lwer 8 bits f the apprpriate data register (TxData0 r RxData0) Vcder Sectin Nise Gate The Vcder sectin has an ptinal, prgrammable nise gate. This is cntrlled by the additin f five new 16-bit C-BUS write registers, accessed by Pass-thrugh mde (see sectin ). Once the Functin Image has been laded, these new registers will all be set t an initial value f zer. Fr details f hw t cnfigure these registers, see sectin The purpse f the encder's nise gate is t remve backgrund nise in between speech pauses. This culd be used t remve nise generated in any frnt-end analgue circuitry, r culd be used t help reduce the effects f ambient nise, perhaps with sme degree f user cntrl. Three parameters cntrl this nise gate. An upper threshld level cntrls the pint at which the gate pens and allws audi t pass. A lwer threshld level cntrls the pint at which the gate clses, thereby preventing audi frm passing. These tw parameters tgether cntrl the hysteresis and prevent 'chattering'. A third parameter cntrls hw many cnsecutive frames f audi must be belw the lwer threshld befre the gate clses. This 'gate shut delay' prevents the tail end f wrds (like a trailing 's') frm being clipped. Once the gate shut delay has expired, the gate des nt shut abruptly, but clses ver a perid f 16 frames. Each 20ms frame has prgressively mre attenuatin applied, until the frames are silent. This happens in apprximately 6dB steps CML Micrsystems Plc 45 D/8341/7

46 Original Signal Vice Nise Gate Output Upper threshld level Gate shut delay Prgressive attenuatin Backgrund nise Lwer threshld level The purpse f the decder's nise gate is t remve audi artefacts after decding packets f vcded silence. The nise gate peratin is exactly the same as the encder's nise gate, hwever, nly the lwer threshld level is prgrammable. The upper threshld level is fixed t be twice the lwer threshld level, and the gate shut delay is fixed t be 10 frames, which is 200ms dpmr Operating Mdes and Addressing TS describes tw perating mdes fr a dpmr radi: ISF Initial Services and Facilities ut f the bx mde CSF Cnfigured Services and Facilities managed mde. The can supprt either f these mdes, as selected by b9 f the Mdem Cnfiguratin register, $C7 (see User Manual sectin ). The standard als defines tw addressing schemes: 24-bit binary r 7-digit BCD (binary-cded-decimal). Radis perating in ISF mde are required t use binary addressing, but in CSF mde either binary r BCD addressing can be used. Bth addressing schemes are supprted by the, selected by b11 in the Mdem Cnfiguratin register, $C7 (see User Manual sectin ). The hst can lad tw Own IDs (binary r BCD) int Prgram Blck 1 fr use in bth Tx and Rx mdes. In Tx mde the hst can select which f these t send in the Caller ID field f the utging call. In Rx mde, the cmpares the Called ID field frm incming calls against each f its Own IDs, and will accept the call if a valid ID match is fund. Address matching can be disabled using b12 f the Mdem Cnfiguratin register, $C7, in which case the will accept all incming calls. The implements BCD address translatin in bth Tx and Rx, t relieve the hst f the prcessing required t map BCD digits t ver-air binary values. BCD addresses can include wildcard digits in any f the lwer fur digits, and there are ten BCD All-Call addresses with wildcards in all six lwer digits. The handles wildcard digits apprpriately during address matching in Rx. Binary addresses d nt supprt grup calling with wildcards, but the prvides six binary-nly Grup Call IDs in additin t the tw Own IDs. These can be prgrammed by the hst t be used fr address matching in Rx nly. TS als specifies a system-wide All Call facility using the Cmmunicatin Frmat field in the Header Frame (TS sectin 5.8). The nrmal setting fr this field is Peer-t-Peer, but when set t Call ALL the will always accept the call regardless f ISF/CSF mde and all ther address settings. The hst shuld take care nt t transmit in All Call mde unless actually intended ISF Addressing The services available in ISF mde are described in TS sectin 8.1. Radis using ISF mde prvide a style f peratin bradly similar t analgue PMR CML Micrsystems Plc 46 D/8341/7

47 ISF mde requires 24-bit binary addressing t be used, with nly the tp 8 bits (the Cmmn ID field) in active use fr addressing ISF mde devices. The remaining 16 bits must be set t all 1s. This is the default mde f the and the default Cmmn IDs are: ID1: $01 ID2: $02. The ISF Cmmn All-Call ID is $FF. When in ISF mde the will always accept calls t this address regardless f ther address settings CSF Addressing The services available in CSF mde are described in TS sectin 8.2 and Annex A. CSF mde des nt mandate BCD addressing unless the hst implements the Standard User Interface, but the advantages f BCD addressing are direct mapping f user keypad entries t destinatin addresses and the ptin f wildcard digits t implement grup calls. The hst can select the addressing mde using b11 f the Mdem Cnfiguratin register, $C Tx Mde (dpmr frmatted) In Tx dpmr Frmatted mde ($C1, Mdem Cntrl = $0012), the builds Header, Cntrl Channel and End Infrmatin blcks, perfrms all FEC cding, interleaving and scrambling functins and inserts Frame Sync and Clur Cde sequences t generate the required frame frmats fr transmissin. During vice calls the can autmatically enable and cntrl the Vcder sectin and transfer vice paylad data frm/t it withut hst interventin. The TxData registers are used t transfer Header and End Infrmatin fields in additin t paylad data. The Blck ID field in the TxData0 register infrms the hw t prcess each transfer. b5-4 Blck ID 00 HDR - Header Data 01 PLD - Paylad Data 10 PLS - Paylad Data with Slw Data 11 END - End Data The hst shuld prelad the TxData registers with Header Data befre placing the device in Tx dpmr Frmatted mde. The reads the Header Type field t determine the burst type and then sends the Preamble and Header Frame. If the Call Infrmatin field indicates that repeated extended wake-up Headers are t be sent, the will d s autmatically. The Header fields are saved fr re-use when building the Cntrl Channel Infrmatin blcks in fllwing paylad frames: the hst des nt need t re-lad them. Header Data: TxData RxData LE 0 Own ID Header Type Cunter Call Infrmatin Cmms Mde 2 Versin Frmat Clur Cde Binary mde: Address lwer 12 bits BCD mde: Address lwer 4 digits K4, K5, K6, K Binary mde: Address upper 12 bits BCD mde: Address upper 3 digits K1, K2, K CML Micrsystems Plc 47 D/8341/7

48 Header Type: See TS sectin 5.11 (Cmmunicatin Start, ACK, etc.) Own ID: 00 = Tx: reserved Rx: All call received 01 = Tx: send Own ID 1 (frm Prgram Blck 1) Rx: Own ID1 matched 10 = Tx: send Own ID 2 (frm Prgram Blck 1) Rx: Own ID2 matched 11 = reserved reserved: See TS sectin 5.4 (00) Cmms Mde: LE: Call Infrmatin: Cmms Frmat: Versin: See TS sectin 5.7 (sets data type and surce, hst r vcder) Late-Entry (Rx nly) sme data fields may be missing due t Late Entry int the call See TS sectin 5.10 (includes extended headers, data frame size etc.) See TS sectin 5.8 (All-Call r Peer-t-Peer) 00 = Call ALL (Bradcast) 01 = Peer-t-Peer cmmunicatin 10 = reserved 11 = reserved See TS sectin 5.16 (Vcder Versin) Nte: the dpmr Assciatin has agreed standard bit allcatins fr the vice burst and the hst shuld set this field accrdingly. 00 = DVSI AMBE+2 01 = T be selected by Chinese DRA 10 = RALCWI 11 = Manufacturer defined Clur Cde: 6-bit index int the Clur Cde table as shwn in TS sectin Address: Tx: destinatin (Called) address. Rx: riginating (Caller) address. Paylad Data: See Table 10 and User Manual sectin Paylad Data with Slw Data: See Table 10 and User Manual sectin CML Micrsystems Plc 48 D/8341/7

49 End Data: TxData RxData Tx Wait Ack Req End Type Cunter reserved 0 Status Message 2 Nt used 3 Nt used 4 Nt used End Type: See TS sectin 5.12 Ack Request: See TS sectin 5.13 Tx Wait: See TS sectin 5.14 Status Msg: See TS sectin 5.15 reserved: 0000 Depending n the burst type, the will expect the hst t lad a series f paylad data blcks and/r an End Data blck (except fr ACK bursts which cnsist f a bare Header Frame). Discnnect bursts cntain a repeated Header/End Frame pair but the hst shuld nly lad single blcks f Header and End Data fields, as the will send the duplicate frames autmatically. If the Vcder sectin is enabled and the Cmmunicatin Mde field in the Header Frame indicates a vice call, the will autmatically enable the Vcder sectin micrphne input and rute paylad data frm the Vcder sectin fr transmissin. Nte that the Vcder sectin takes a finite time t encde the incming vice data, during which the will autmatically insert silence data int the paylad frames. The hst can lad an End Frame at any pint during the call. T terminate the vice call, the hst shuld place the mdem int Tx Idle mde ($C1, Mdem Cntrl = $0002). The will disable the Vcder sectin and send the End Frame that was laded previusly. At the end f all dpmr transmissins the will issue a TxDne IRQ when it is safe fr the hst t place the device back int Idle mde ($C1, Mdem Cntrl = $0000) Rx Mde (dpmr frmatted) In Rx dpmr mde ($C1, Mdem Cntrl = $0011), the autmatically splits incming calls t extract Header Infrmatin, Cntrl Channel Infrmatin and End Infrmatin blcks and perfrms all the necessary de-scrambling, de-interleaving and FEC decding functins. In speech calls, the can autmatically enable the Vcder sectin when required and transfer received speech data withut hst interventin. The RxData registers are used t transfer Header and End Data fields in additin t paylad data. The Blck ID field in the RxData0 register infrms the hst what type f data blck each transfer cntains. The field layut in the RxData registers fr the different transfer types is the same as fr Tx dpmr Frmatted mde (sectin ). When placed in Rx dpmr Frmatted mde, the autmatically starts searching fr the dpmr frame sync sequences. In additin t detecting the 48-bit FS1 frame sync at the start f a transmissin, the can als perfrm late entry int a call by detecting tw successive cpies f the 24-bit FS2 sequence at the crrect tw-frame spacing. When a valid frame sync sequence has been detected, an FS1 Detect r FS2 Detect IRQ is issued and the data demdulatr is enabled. The then decdes the cntents f the Header Frame (after an FS1 detect) r the fllwing fur Cntrl Channel Infrmatin blcks (after an FS2 detect). The Header Infrmatin r Cntrl Channel Infrmatin CRCs are checked and prcessing cntinues nly if a full set f valid fields has been received. Header Frames cntain tw duplicate Header Infrmatin blcks: the checks bth blck CRCs, uses the first valid blck and discards the ther CML Micrsystems Plc 49 D/8341/7

50 When repeated extended wake-up Header Frames are received (see TS sectin 11.1), the will decde the first valid Header but delay address checking until all fllwing repeat Headers have been received. This maximises the time the hst can be kept in pwersave. Address checking nw takes place depending n ISF/CSF mde and the addressing mde selected. The Cmmunicatins Frmat field is checked first: if this is set t Call ALL the call is accepted. If nt, the Called statin ID is checked against the device s Own IDs (prgrammed by the hst int Prgram Blck 1) and if a match is fund the call is accepted. In ISF mde, the Cmmn All-Call ID $FF is als always accepted. In any f these cases a Called IRQ is issued t the hst, therwise the call is drpped with n further hst ntificatin and the returns t frame sync search. Address matching can be disabled by setting b12 f the Mdem Cnfiguratin register, in which case the will accept all incming calls. The Header fields are presented t the hst in the RxData blck. Late entry is indicated by bit 15 f RxData0: in this case the Header Type and Call Infrmatin fields in the Header Data blck returned t the hst will nt cntain valid data, as these fields are nly sent in Header Frames and are nt re-sent in the Cntrl Channel Infrmatin blcks during a call. Depending n the burst type, the will decde the fllwing paylad and/r End Frames and present their cntents t the hst r vcder. If the Vcder sectin is enabled and the Cmmunicatin Mde field in the Header Frame indicates a vice call, the will autmatically enable the Vcder sectin speaker utput and rute paylad data t the Vcder sectin fr decding. In this mde, the data is transferred in 4-bit Lg-Likelihd-Rati frmat. Otherwise, paylad data is presented t the hst in the RxData registers in sft r hard frmat, as specified. When an End Frame is received, the will reprt its cntents t the hst, disable the vcder (if necessary) and return t frame sync search. All frame sync sequences, Clur Cdes and CRCs cntained in paylad superframes are checked and an Event IRQ is issued when any are received incrrectly. If all the frame sync sequences, Clur Cdes and CRCs in a superframe are received incrrectly, the superframe is cnsidered crrupt. The hst can set a threshld fr cnsecutive crrupt superframes (in Prgram Blck 0), after which the will issue an Event IRQ, drp the call and return t frame sync search. See: RxData 0 - $B8 read AuxData/Sub-audi Read - $CC read Slw Data Slw Data may be transferred in vice calls alngside Vice Paylad Data, by setting the Blck ID t Paylad with Slw Data and using the AuxData registers. If the Vcder sectin is enabled, there will be n vice paylad transfers and s dummy paylad transfers are used with the Byte Cunter field cleared t zer. In Type1 and Type 2 Data calls, the Slw Data field is used t cntrl the data flw ver-air and s is generated r decded by the itself and the nly data field that is visible t the hst is the Frmat field as defined in TS sectin which is made available, r supplied by the hst, in the lwest 4 bits f the AuxData register. In Tx mde: Lad AuxData register with tw bytes f Slw Data: AuxData/Sub-audi Write - $C2 write Set Cmmunicatins Mde t Vice with Slw Data Set BlckID t Paylad with Slw Data : TxData 0 - $B5 write Set Byte Cunter field (t zer if Vcder sectin is in use): TxData 0 - $B5 write. The has an internal 64-byte buffer fr Slw Data. While the hst keeps this internal data buffer tpped-up the will cntinue t transmit Slw Data and add the cntinuatin bits t the verair data. Nte that nly tw bytes f Slw Data are sent ver-air fr every 36 bytes f vice paylad, s the buffer may verflw if a large quantity f Slw Data is laded cntinuusly. The hst is expected t track the number f bytes in the buffer. Bit 10 f the Status register $C6 is set t 1 and an interrupt raised, if unmasked, when there are nly tw bytes left in the FIFO. When the hst allws the internal buffer t empty, the will terminate the 2014 CML Micrsystems Plc 50 D/8341/7

51 transmissin f Slw Data in the current burst. It is nt pssible t re-start Slw Data transmissin within a burst. In Rx mde: BlckID will reprt Paylad with Slw Data : RxData 0 - $B8 read Cmmunicatins Mde will reprt Vice with Slw Data If paylad is being sent t the Vcder sectin, then the Byte Cunter field will be cleared t zer Slw Data is available in the AuxData register: AuxData/Sub-audi Read - $CC read When the Slw Data transfer has cmpleted, the will stp presenting data t the hst. 8.6 Analgue Mde Tx Mde Analgue In Analgue PMR mde, the MIC input is prcessed and summed with either the external sub-audi signal n the ALT input r the internally generated sub-audi signal and then presented at the MOD1 and MOD2 pins. The chice is determined by Prgram Blck P2.0 b5 (see sectin ) Rx Mde Analgue In Analgue PMR mde the received signal shuld be ruted thrugh Input1 (DISC). The signal is filtered and prcessed s that the inband signal is utput n the Audi pin and the sub-audi signal is either utput n the AuxDAC4 pin r ruted t the internal sub-audi detectr. The chice is determined by Prgram Blck P2.0 b4 (see sectin ). 8.7 Squelch Operatin Many Limiter/Discriminatr chips prvide a nise-quieting squelch circuit arund an p-amp cnfigured as a filter. This signal is cnventinally passed t a cmparatr t prvide a digital squelch signal, which can be ruted directly t ne f the s GPIO pins r t the hst. Hwever with the, the cmparatr and threshld peratins can be replaced by ne f the AuxADCs with prgrammable threshlds and hysteresis functins. See: IRQ Status - $C6 read Mdem Cnfiguratin - $C7 write 8.8 GPIO Pin Operatin The prvides fur GPIO pins. RXENA (GPIO1) and TXENA (GPIO2) are cnfigured t reflect the Tx/Rx state f the Mde register (TXENA and RXENA, active lw). See: Mdem Cnfiguratin - $C7 write. Nte that RXENA and TXENA will nt change state until the relevant mde change has been executed by the. This is t allw the hst sufficient time t lad the relevant data buffers and the time t encde the data required prir t its transmissin. There is thus a fixed time delay between the GPIO pins changing state and the data signal appearing at the MOD utput pins. During the pwer-n sequence (until the FI has cmpleted its lad sequence) these pins have nly a weak pull-up applied t them, s care shuld be taken t ensure that any lading during this perid des nt adversely affect the peratin f the unit. GPIO A and B are hst prgrammable fr input r utput using the AuxADC Cnfiguratin register, $A7. The default state is input, with a weak pull-up. When set fr input, the values can be read back using the Mdem Status register, $C CML Micrsystems Plc 51 D/8341/7

52 8.9 Auxiliary ADC Operatin The inputs t the tw auxiliary ADCs can be independently ruted frm any f the signal input pins under cntrl f the AuxADC Cnfiguratin register, $A7. Cnversins will be perfrmed as lng as a valid input surce is selected. T stp the ADCs, the input surce shuld be set t ff. Register $C0, b6, BIAS, must be enabled fr auxiliary ADC peratin. Averaging can be applied t the ADC readings by selecting the relevant bits in the AuxADC Cnfiguratin register, $A7. The length f the averaging is determined by the value in P3.0 and P3.1 and defaults t a value f 0. This is a rlling average system such that a prprtin f the current data will be added t the last average value. The prprtin is determined by the value f the average cunter in P3.0 and P3.1. Fr an average value f: 0 = 50% f the current value will be added t 50% f the last average value 1 = 25% f the current value will be added t 75% f the last average value 2 = 12.5% etc. The maximum useful value f this field is 9. High and Lw threshlds may be independently applied t bth ADC channels (the cmparisn is applied after averaging, if this is enabled) and an IRQ generated when a rising edge passes the High threshld r a falling edge passes the Lw threshld, see Figure 20. The threshlds are prgrammed via the AuxADC Threshld register, $CD. IRQ IRQ IRQ IRQ High Threshld Signal Lw Threshld Figure 20 AuxADC IRQ Operatin Auxiliary ADC data is read back in the AuxADC Data registers ($A9 and $AA) and includes the threshld status as well as the actual cnversin data (subject t averaging, if enabled). See: AuxADC Cnfiguratin - $A7 write AuxADC1 Data and Status - $A9 read AuxADC2 Data and Status - $AA read AuxADC Threshld Data - $CD write Auxiliary DAC/RAMDAC Operatin The fur auxiliary DAC channels are prgrammed via the AuxDAC Data/Cntrl register, $A8. AuxDAC channel 1 may als be prgrammed t perate as a RAMDAC, which will autmatically utput a preprgrammed prfile at a prgrammed rate. The AuxDAC Data/Cntrl register, $A8, with b12 set, cntrls this mde f peratin. The default prfile is a raised csine (see Table 15), but this may be ver-written 2014 CML Micrsystems Plc 52 D/8341/7

53 with a user-defined prfile by writing t P3.11. The RAMDAC peratin is nly available in Tx mde and, t avid glitches in the ramp prfile, it is imprtant nt t change t Idle r Rx mde whilst the RAMDAC is still ramping. The AuxDAC utputs hld the user-prgrammed level during a pwersave peratin if left enabled, therwise they will return t zer. Nte that access t all fur AuxDACs is cntrlled by the AuxDAC Data/Cntrl register, $A8, and therefre t update all AuxDACs requires fur writes t this register. It is nt pssible t simultaneusly update all fur AuxDACs. AuxDAC4 is used in Analgue mde t utput the filtered Sub-Audi signal. See: AuxDAC Data/Cntrl - $A8 write Digital System Clck Generatrs Ref CLK div /1 t 512 $AC b0-8 SysCLK1 Ref PD kHz (96kHz typ) SysCLK1 Div LPF PLL div /1 t 1024 $AB b0-9 VCO SysCLK1 VCO MHz (49.152MHz typ) SysCLK1 Pre-CLK $AC b11-15 VCO p div /1 t 64 $AB b10-15 SysCLK1 Output 384kHz-20MHz Ref CLK div /1 t 512 $AE b0-8 SysCLK2 Ref PD kHz (96kHz typ) SysCLK2 Div LPF PLL div /1 t 1024 $AD b0-9 VCO SysCLK2 VCO MHz (49.152MHz typ) SysCLK2 Pre-CLK $AE b11-15 VCO p div /1 t 64 $AD b10-15 SysCLK2 Output 384kHz-20MHz Ref CLK div /1 t 512 P3.4 MainCLK Ref PD kHz (96kHz typ) MainCLK Div LPF PLL div /1 t 1024 P3.5 VCO MainCLK VCO MHz (49.152MHz typ) MainCLK Pre-CLK VCO p div /1 t 64 P3.3 & 3.6 MainCLK Output 384kHz-50MHz (24.576MHz typ) T Internal ADC / DAC dividers OSC 19.2MHz Reference Clck AuxADC Div P3.3 & P3.6 Aux_ADC (83.3kHz typ) Figure 21 Digital Clck Generatin Schemes The requires a 19.2MHz reference clck surce CML Micrsystems Plc 53 D/8341/7

54 Main Clck Operatin A digital PLL is used t create the Main Clck (nminally MHz) fr the internal sectins f the. At the same time, ther internal clcks are generated by divisin f either the Reference Clck r the Main Clck Pre-Clck. These internal clcks are used fr determining the sample rates and cnversin times f A-t-D and D-t-A cnverters, running a General Purpse (GP) Timer and the signal prcessing blck. In particular, it shuld be nted that in Idle mde the setting f the GP Timer divider directly affects the C-BUS latency (with the default values this is nminally 250μs). The defaults t the settings apprpriate fr a 19.2MHz scillatr, as given in P3.2 t P3.7. See: Prgram Blck 3 AuxDAC, RAMDAC and Clck Cntrl System Clck Operatin Tw System Clck utputs, SYSCLK1 and SYSCLK2, are available t drive additinal circuits, as required. These are digital phase lcked lp (PLL) clcks that can be prgrammed via the System Clck registers with suitable values chsen by the user. The System Clck PLL Cnfigure registers ($AB and $AD) cntrl the values f the VCO Output divider and Main Divide registers, while the System Clck Ref. Cnfigure registers ($AC and $AE) cntrl the values f the Reference Divider and signal ruting cnfiguratins. The PLLs are designed fr a reference frequency f 96kHz. If nt required, these clcks can be independently pwersaved. The clck generatin scheme is shwn in the blck diagram f Figure 21. Nte that at pwern, these pins are disabled. See: SYSCLK 1 and SYSCLK 2 PLL Data - $AB, $AD write SYSCLK 1 and SYSCLK 2 REF - $AC and $AE write Signal Level Optimisatin The internal signal prcessing f the will perate with wide dynamic range and lw distrtin nly if the signal level at all stages in the signal prcessing chain is kept within the recmmended limits. Fr a device wrking frm a 3.3V ±10% supply, the maximum signal level which can be accmmdated withut distrtin is [(3.3 x 90%) - (2 x 0.3V)] Vlts pk-pk = 838mV rms, assuming a sine wave signal. This shuld nt be exceeded at any stage. In Analgue mde, an Input AGC functin is prvide t ptimise the Mic input level acrss a wide dynamic range. In this mde the effects f Pre-emphasis and De-emphasis as well as verlad cnditins shuld be taken int accunt when determining apprpriate input levels Transmit Path Levels Fr the maximum signal ut f the MOD1 and MOD2 attenuatrs, the signal level at the utput f the Mdem blck is set t be 0dB, The Fine Output adjustment ($C8 P ) has a maximum attenuatin f 3.5dB and n gain, whereas the Carse Output adjustment ($B0: b14-12, b10-8) has a variable attenuatin f up t 12dB in 2dB steps and a mute setting (>40dB), and n gain CML Micrsystems Plc 54 D/8341/7

55 Audi DISC ALT MIC Input1 Gain: $B1:b12-10 MUX $B1: b5-2 Input1 Audi Tnes Audi Tne Tx Level: $C3:6xxx Vcder Input Gain: $B0:b6-4 MUX $C1: b15-12 Sub-audi Prcessing Vice Prcessing SA Tx Level: $CD:4xxx Vice Tx Level $C3:2xxx SUM Output1 MUX P2.1: b5 MUX P2.1: b6 MUX $B1: b9-6 Carse Gain: $B0:b3-0 Fine Gain: $CD:1xxx Fine Gain: $CD:1xxx Carse Gain: $B0:b14-12 MOD1 Carse Gain: $B0:b10-8 MOD2 Input2 Output2 Input2 Gain: $B1:b15-13 Figure 22 Tx Level Adjustments (Analgue) Audi Input1 Gain: $B1:b12-10 Output1 DISC ALT MUX Input1 Vcder Input Secndary Gain: $C3:b7-4 RALCWI Vcder dpmr frmatter 4FSK mdulatr MUX P2.1: b5 MUX Carse Gain: $B0:b3-0 Fine Gain: $CD:1xxx Carse Gain: $B0:b14-12 MOD1 MIC $B1: b5-2 Vcder Input Gain: $B0:b6-4 encde FEC MUX P2.1: b6 $B1: b9-6 Fine Gain: $CD:1xxx Carse Gain: $B0:b10-8 MOD2 Input2 Output2 Input2 Gain: $B1:b15-13 Figure 23 Tx Levels (Digital) Receive Path Levels The Carse Input adjustment ($B1) has a variable gain f up t +22.4dB and n attenuatin. With the lwest gain setting (0dB), the maximum allwable input signal level at the DISCFB pin wuld be 838mV rms. This signal level is an abslute maximum, which shuld nt be exceeded CML Micrsystems Plc 55 D/8341/7

56 Audi DISC ALT Input1 Gain: $B1:b12-10 MUX $B1: b5-2 Input1 Audi Tnes Audi Tne Rx Level: $C3:7xxx Vcder Input Gain: $B0:b6-4 Vice Prcessing MUX $C1: b15-12 Vice Rx Gain $C3:3xxx MUX $B1: b9-6 Fine Gain: $CD:1xxx Carse Gain: $B0:b3-0 Carse Gain $B0:b14-12 MOD1 MIC Sub-audi Prcessing SA Rx Level: $CD:5xxx Fine Gain: $CD:1xxx Carse Gain: $B0:b10-8 MOD2 Input2 Input2 Gain: $B1:b15-13 DAC4 Figure 24 Rx Level Adjustments (Analgue) Audi Input1 Gain: $B1:b12-10 Input1 Audi Tne Rx Level: $C3:7xxx Vcder Speaker Gain $C3:b3-0 DISC ALT MUX $B1: b5-2 Vcder Input Gain: $B0:b6-4 4FSK Demdulatr dpmr De-frmat FEC RALCWI Vcder decde MUX $B1: b9-6 Fine Gain: $CD:1xxx Carse Gain: $B0:b3-0 Carse Gain $B0:b14-12 MOD1 MIC Fine Gain: $CD:1xxx Carse Gain: $B0:b10-8 MOD2 Input2 Input2 Gain: $B1:b15-13 OUTP Figure 25 Rx Level Adjustments (Digital) 8.13 Tx Spectrum Plts The fllwing figure shws the Tx spectrum when using a suitable signal generatr as measured n a spectrum analyser using the internal PRBS generatr CML Micrsystems Plc 56 D/8341/7

57 R e f L v l d B m M a r k e r 1 [ T 1 ] d B m M H z R B W 500 H z V B W 2 k H z S W T 700 m s R F A t t U n i t 1 0 d B 1 V I E W 1 S A d B m 1 [ T 1 ] d B m M H z C H P W R d B m A C P U p d B A C P L w d B A L T 1 U p d B A L T 1 L w d B A c u 1 c u 2 c u 2 c u c l 2 c l 1 c l 1 C 0 C 0 c l C e n t e r M H z 3. 5 k H z / S p a n 35 k H z D a t e : 13 : 45 : 44 Figure 26 Tx Mdulatin Spectra bps 2014 CML Micrsystems Plc 57 D/8341/7

58 8.14 C-BUS Register Summary Table 11 C-BUS Registers ADDR. Wrd Size REGISTER (hex) (bits) $01 W C-BUS RESET 0 $A7 W AuxADC Cnfiguratin 16 $A8 W AuxDAC Data and Cntrl 16 $A9 R AuxADC1 Data and Status/Checksum 2 hi 16 $AA R AuxADC2 Data and Status/Checksum 2 l 16 $AB W SYSCLK 1 PLL Data 16 $AC W SYSCLK 1 Ref 16 $AD W SYSCLK 2 PLL Data 16 $AE W SYSCLK 2 Ref 16 $AF reserved $B0 W Analgue Output Gain 16 $B1 W Input Gain and Signal Ruting 16 $B2 reserved $B3 reserved $B4 reserved $B5 W TxData 0 16 $B6 W TxData 1 16 $B7 W TxData 2 16 $B8 R RxData 0/Checksum 1 hi 16 $B9 R RxData 1/Checksum 1 l 16 $BA R RxData 2 16 $BB R RxData 3 16 $BC reserved $BD reserved $BE reserved $BF reserved $C0 W Pwer Dwn Cntrl 16 $C1 W Mdem Cntrl 16 $C2 W AuxData/Sub-audi Write 16 $C3 W Vcder Sectin Analgue Gain 16 $C4 reserved $C5 R Rx Data 4 16 $C6 R IRQ Status 16 $C7 W Mdem Cnfiguratin 16 $C8 W Prgramming Register 16 $C9 R Mdem Status 16 $CA W Tx Data 3 16 $CB W Tx Data 4 16 $CC R AuxData/Sub-audi Read 16 $CD W AuxADC Threshld Data 16 $CE W Interrupt Mask 16 $CF reserved All ther C-BUS addresses (including thse nt listed abve) are either reserved fr future use r allcated fr prductin testing and must nt be accessed in nrmal peratin CML Micrsystems Plc 58 D/8341/7

59 9 Perfrmance Specificatin 9.1 Electrical Perfrmance Abslute Maximum Ratings Exceeding these maximum ratings can result in damage t the device. Min. Max. Units Supply (AV DD - AV SS, DV DD - DV SS ) V Supply (DV CORE - DV SS ) V Vltage n any pin t V SS -0.3 V DD V Current int r ut f any V DD r V SS pins ma Current int r ut f any ther pin ma L8 Package Min. Max. Units Ttal Allwable Pwer Dissipatin at Tamb = 25ºC 2190 mw... Derating 21.9 mw/ºc Strage Temperature ºC Operating Temperature ºC Operating Limits Crrect peratin f the device utside these limits is nt implied. Ntes Min. Max. Units Supply (AV DD - AV SS, DV DD - DV SS ) V Supply (DV CORE - DV SS ) V Operating Temperature ºC Xtal/External Clck Frequency MHz Nte: 1. Crrect peratin f the device requires the fllwing specific frequencies t be applied: A reference clck t XTAL/CLK (pin 55) = 19.2MHz ± 100ppm 2014 CML Micrsystems Plc 59 D/8341/7

60 9.1.3 Operating Characteristics Details in this sectin represent design target values and are nt currently guaranteed. Fr the fllwing cnditins unless therwise specified: External cmpnents as recmmended in Figure 2 and Table 2. Reference clck frequency = 19.2MHz 0.01% (100ppm); Tamb = 40 C t +85 C. AV DD = DV DD = 3.0V t 3.6V; DV CORE = 1.7V t 1.9V; V DEC = 2.5V; V BIAS = AV DD /2. Reference Signal Level = 308mVrms at 1kHz with AV DD = 3.3V. Signal levels track with supply vltage, s scale accrdingly. Signal t Nise Rati (SNR) in bit rate bandwidth. Input stage gain = 0dB. Output stage attenuatin = 0dB. Maximum lad n digital utputs = 30pF. Current cnsumptin figures quted in this sectin apply t the device when laded with 8341 FI-1.x nly. The use f ther Functin Images can mdify the current cnsumptin f the device. DC Parameters Ntes Min. Typ. Max. Units Supply Current 11 All Pwersaved DI CORE 50 µa DI DD µa AI DD 4 20 µa Idle Mde 12 DI CORE 14.0 ma DI DD 1.9 ma AI DD ma Rx Mde (excluding Vcder Sectin) 12 DI DD (4800bps search fr FS) 4.7 ma DI DD (9600bps search fr FS) 7.5 ma DI DD (4800bps FS fund) 2.8 ma DI DD (9600bps FS fund) 3.7 ma AI DD (AV DD = 3.3V) 1.6 ma Tx Mde (excluding Vcder Sectin) 12 DI DD (4800bps 2-pint) 4.3 ma DI DD (9600bps 2-pint) 5.2 ma DI DD (4800bps I/Q) 5.4 ma DI DD (9600bps I/Q) 7.3 ma AI DD (AV DD = 3.3V) 1.5 ma Vcder Sectin DI CORE 38.0 ma DI DD 0.6 ma AI DD (AV DD = 3.3V) ma Additinal current fr each Auxiliary System Clck (utput running at 4MHz) DI DD (DV DD = 3.3V, V DEC = 2.5V) 250 µa Additinal current fr each Auxiliary ADC DI DD (DV DD = 3.3V, V DEC = 2.5V) 50 µa Additinal current fr each Auxiliary DAC AI DD (AV DD = 3.3V) 200 µa Ntes: 11 Tamb=25 C: nt including any current drawn frm the device pins by external circuitry. 12 System Clcks: auxiliary circuits disabled, but all ther digital circuits (including the Main Clck PLL) enabled. 13 May be further reduced by pwer-saving unused sectins. 14 ADC r DAC enabled in Vcder Sectin CML Micrsystems Plc 60 D/8341/7

61 DC Parameters (cntinued) Ntes Min. Typ. Max. Unit Reference Clck Input Input Lgic 1 70% DV DD Input Lgic 0 30% DV DD Input Current (Vin = DV DD ) 40 µa Input Current (Vin = DV SS ) 40 µa C-BUS Interface and Lgic Inputs Input Lgic 1 80% DV DD Input Lgic 0 20% DV DD Input Leakage Current (Lgic 1 r 0) µa Input Capacitance 7.5 pf C-BUS Interface and Lgic Outputs Output Lgic 1 (I OH = 2mA) 90% DV DD Output Lgic 0 (I OL = -5mA) 10% DV DD Off State Leakage Current 10 µa IRQN (Vut = DV DD ) µa REPLY_DATA (utput HiZ) µa V BIAS 21 Output Vltage Offset wrt AV DD /2 (I OL < 1A) ±2% AV DD Output Impedance 22 k Ntes: 21 Applies when utilising V BIAS t prvide a reference vltage t ther parts f the system. When using V BIAS as a reference, V BIAS must be buffered. V BIAS must always be decupled with a capacitr as shwn in Figure 2 and Table CML Micrsystems Plc 61 D/8341/7

62 AC Parameters Ntes Min. Typ. Max. Unit Reference Clck Input 'High' Pulse Width 15 ns 'Lw' Pulse Width 15 ns Input Impedance 31 Pwered-up Resistance 150 k Capacitance 20 pf Pwered-dwn Resistance 300 k Capacitance 20 pf Xtal Start-up Time (frm pwersave) 20 ms System Clk 1/2 Outputs Ref. Clck input t CLOCK_OUT timing: (in high t ut high) ns (in lw t ut lw) ns 'High' Pulse Width ns 'Lw' Pulse Width ns V BIAS Start-up Time (frm pwersave) 100 ms Micrphne, Alternative and Discriminatr Inputs (MIC, ALT, DISC) Input Impedance 34 >10 M Maximum Input Level (pk-pk) 35 80% AV DD Lad Resistance (feedback pins) 80 k Amplifier Open Lp Vltage Gain (I/P = 1mVrms at 100Hz) 80 db Unity Gain Bandwidth 1.0 MHz Prgrammable Input Gain Stage 36 Gain (at 0dB) db Cumulative Gain Errr (wrt attenuatin at 0dB) db Ntes: 31 Characterised and specified at 6.144MHz nly. 32 Characteristics when driving the Reference Clck input with an external clck surce MHz Reference Clck selected (scale fr 19.2MHz). 34 With n external cmpnents cnnected, measured at DC. 35 Centred abut AV DD /2; after multiplying by the gain f input circuit (with external cmpnents cnnected). 36 Gain applied t signal at utput f buffer amplifier: DISCFB, ALTFB r MICFB 37 Design Value. Overall attenuatin input t utput has a tlerance f 0dB ±1.0dB 2014 CML Micrsystems Plc 62 D/8341/7

63 AC Parameters Ntes Min. Typ. Max. Unit Mdulatr Outputs 1/2 and Audi Output (MOD1, MOD2, AUDIO) Pwer-up t Output Stable µs Mdulatr Attenuatrs Attenuatin (at 0dB) db Cumulative Attenuatin Errr (wrt attenuatin at 0dB) db Output Impedance Enabled Disabled k Output Current Range (AV DD = 3.3V) ±125 µa Output Vltage Range AV DD 0.5 V Lad Resistance 20 k Audi Attenuatr Attenuatin (at 0dB) db Cumulative Attenuatin Errr (wrt attenuatin at 0dB) db Output Impedance Enabled Disabled k Output Current Range (AV DD = 3.3V) ±125 µa Output Vltage Range AV DD 0.5 V Lad Resistance 20 k Ntes: 41 Pwer-up refers t issuing a C-BUS cmmand t turn n an utput. These limits apply nly if V BIAS is n and stable. At pwer supply switch-n, the default state is fr all blcks, except the Reference Clck and C-BUS interface, t be in placed in pwersave mde. 42 Small signal impedance, at AV DD = 3.3V and Tamb = 25 C. 43 With respect t the signal at the feedback pin f the selected input prt. 44 Centred abut AV DD /2; with respect t the utput driving a 20k lad t AV DD / CML Micrsystems Plc 63 D/8341/7

64 AC Parameters (cnt.) Ntes Min. Typ. Max. Unit Auxiliary Signal Inputs (Aux ADC 1 t 4) Surce Output Impedance k Auxiliary 10 Bit ADCs Reslutin 10 Bits Maximum Input Level (pk-pk) 54 80% AV DD Cnversin Time µs Input Impedance Resistance 57 >10 M Capacitance 5 pf Offset Errr 55, 56 0 ±10 mv Integral Nn-linearity 55, 56 ±3 LSBs Differential Nn-linearity 53, 55 ±1 LSBs Auxiliary 10 Bit DACs Reslutin 10 Bits Maximum Output Level (pk-pk), n lad 54 80% AV DD Offset Errr 55, 56 0 ±10 mv Resistive Lad 5 k Integral Nn-linearity 55, 56 ±4 LSBs Differential Nn-linearity 53, 55 ±1 LSBs Ntes: 51 Dentes utput impedance f the driver f the auxiliary input signal, t ensure < 1 bit additinal errr under nminal cnditins. 52 With an auxiliary clck frequency f 6.144MHz. 53 Guaranteed mntnic with n missing cdes. 54 Centred abut AV DD /2. 55 Specified between 2.5% and 97.5% f the full-scale range. 56 Calculated frm the line f best fit f all the measured cdes. 57 Measured at dc CML Micrsystems Plc 64 D/8341/7

65 AC Parameters (cnt.) Ntes Min. Typ. Max. Unit Vcder Sectin Perfrmance Sample Rate 8 ks/s Data Rate (with FEC) 3600 bps Data Rate (withut FEC) 2400 bps Lwer Frequency Limit (internally bandlimited) 60 Hz Upper Frequency Limit (internally bandlimited) 3900 Hz Encder Algrithmic Delay ms Decder Algrithmic Delay ms Output Lad Impedance (OUTP) 32 Output Vltage Range (OUTP) t 90 % AV DD ADC SINAD 69, db DAC SINAD 69, db Ntes: 69 Internal gain settings are 0dB n input gain fr the ptimum vcded level and +6dB n utput gain fr the ptimum vcded level, subject t further characterisatin. 70 The internal ADC is a sigma-delta type which samples at 2.4MHz. It is imprtant that there is n significant energy clse t this frequency r at any f its harmnics, thus aviding the need fr an external lw-pass anti-alias filter. 71 The internal DAC is a sigma-delta type which samples at 2.4MHz. It will utput energy at this frequency and its harmnics. Shuld this present a prblem, it is suggested that sme external filtering be used at the audi utputs. 72 Excludes the 20/40/60/80 ms sample cllectin perid. 73 Measured whilst driving a 600 resistive lad t AV SS CML Micrsystems Plc 65 D/8341/7

66 9.1.4 Parametric Perfrmance Details in this sectin represent design target values and are nt currently guaranteed. Fr the fllwing cnditins unless therwise specified: External cmpnents as recmmended in Figure 2 and Table 2. Reference clck frequency = 19.2MHz 0.01% (100ppm); Tamb = 40 C t +85 C. AV DD = DV DD = 3.0V t 3.6V; DVCORE = 1.7V t 1.9V; V DEC = 2.5V; V BIAS = AV DD /2. Reference Signal Level = 308mVrms at 1kHz with AV DD = 3.3V. Signal levels track with supply vltage, s scale accrdingly. Signal t Nise Rati (SNR) in bit rate bandwidth. Input stage gain = 0dB. Output stage attenuatin = 0dB. Maximum lad n digital utputs = 30pF. All figures quted in this sectin apply t the device when laded with 8341 FI-1.x nly. The use f ther Functin Images, can mdify the parametric perfrmance f the device. dpmr Mdem Ntes Min. Typ. Max. Unit Mdem Symbl Rate symbls /sec Mdulatin 4FSK Filter (RC) Alpha 0.2 Tx Output Level (MOD1, MOD2, 2-pint) Vpk-pk Tx Output Level (MOD1, MOD2, I/Q) Vpk-pk Tx Adjacent Channel Pwer (MOD1, MOD2, prbs) 76, db Rx Sensitivity (BER 4800 symbls/sec) 77 TBD dbm Rx C-channel Rejectin 76, db Rx Input Level mvrms Rx Input DC Offset 0.5 AV DD V Ntes: 75 Transmitting cntinuus default preamble. 76 See data sheet sectin Measured at baseband radi design will affect ultimate prduct perfrmance. 78 Fr a 6.25kHz/4800bps channel. 79 Measured at DISCFB pin fr cntinuus preamble. Audi Perfrmance Ntes Min. Typ. Max. Unit Audi Cmpandr Attack Time 4.0 ms Decay Time 13 ms 0dB-pint mvrms Cmpressin/Expansin Rati 2:1 Inband Tne Encder Frequency Range Hz Tne Frequency Accuracy ±0.3 % Tne Amplitude Tlerance db Ttal Harmnic Distrtin % Analgue Channel Audi Filtering Pass-band (nminal bandwidth): 12.5kHz Channel Hz 25kHz Channel Hz 2014 CML Micrsystems Plc 66 D/8341/7

67 Audi Perfrmance Ntes Min. Typ. Max. Unit Pass-band Gain (at 1.0kHz) 0 db Pass-band Ripple (wrt gain at 1.0kHz) db Stp-band Attenuatin 33.0 db Residual Hum and Nise Tx dbm Residual Hum and Nise Rx dbm Pre-emphasis db/ct De-emphasis 83 6 db/ct Audi Scrambler Inversin Frequency 3300 Hz Pass-band Hz Audi Expandr Input Signal Range Vrms Ntes: 80 Measured at MOD 1 r MOD 2 utput. 81 AV DD = 3.3V and Tx Audi Level set t 871mV p-p (308mVrms). 82 AV DD = 3.3V. 83 See Figure 12 and Figure Psphmetrically weighted. Pre/de-emphasis, Cmpandr and 25kHz channel filter selected. 85 AV DD = 3.3V CML Micrsystems Plc 67 D/8341/7

68 9.2 Operating Characteristics Timing Diagrams C-BUS Timing Figure 27 C-BUS Timing C-BUS Timing Ntes Min. Typ. Max. Unit t CSE CSN Enable t SCLK high time 100 ns t CSH Last SCLK high t CSN high time 100 ns t LOZ SCLK lw t RDATA Output Enable Time 0.0 ns t HIZ CSN high t RDATA high impedance 1.0 µs t CSOFF CSN high time between transactins 1.0 µs t NXT Inter-byte time 200 ns t CK SCLK cycle time 200 ns t CH SCLK high time 100 ns t CL SCLK lw time 100 ns t CDS CDATA setup time 75 ns t CDH CDATA hld time 25 ns t RDS RDATA setup time 50 ns t RDH RDATA hld time 0 ns C-BUS Latency 250 µs Ntes: 1. Depending n the cmmand, 1 r 2 bytes f CDATA are transmitted t the peripheral MSB (bit 7) first, LSB (bit 0) last. RDATA is read frm the peripheral MSB (bit 7) first, LSB (bit 0) last. 2. Data is clcked int the peripheral n the rising SCLK edge. 3. Cmmands are acted upn between the last rising edge f SCLK f each cmmand and the rising edge f the CSN signal. 4. T allw fr differing µc serial interface frmats C-BUS cmpatible ICs are able t wrk with SCLK pulses starting and ending at either plarity. 5. Maximum 30pF lad n IRQN pin and each C-BUS interface line. These timings are fr the latest versin f C-BUS and allw faster transfers than the riginal C-BUS timing specificatin. The can be used in cnjunctin with devices that cmply with the slwer timings, subject t system thrughput cnstraints CML Micrsystems Plc 68 D/8341/7

69 9.3 Packaging Figure 28 L8 Mechanical Outline: Order as part n. L CML Micrsystems Plc 69 D/8341/7

70 Abut FirmASIC CML s prprietary FirmASIC cmpnent technlgy reduces cst, time t market and develpment risk, with increased flexibility fr the designer and end applicatin. FirmASIC cmbines Analgue, Digital, Firmware and Memry technlgies in a single silicn platfrm that can be fcused t deliver the right feature mix, perfrmance and price fr a target applicatin family. Specific functins f a FirmASIC device are determined by uplading its Functin Image during device initializatin. New Functin Images may be later prvided t supplement and enhance device functins, expanding r mdifying end-prduct features withut the need fr expensive and time-cnsuming design changes. FirmASIC devices prvide significant time t market and cmmercial benefits ver Custm ASIC, Structured ASIC, FPGA and DSP slutins. They may als be exclusively custmised where security r intellectual prperty issues prevent the use f Applicatin Specific Standard Prducts (ASSP s). Handling precautins: This prduct includes input prtectin, hwever, precautins shuld be taken t prevent device damage frm electr-static discharge. CML des nt assume any respnsibility fr the use f any circuitry described. N IPR r circuit patent licences are implied. CML reserves the right at any time withut ntice t change the said circuitry and this prduct specificatin. CML has a plicy f testing every prduct shipped using calibrated test equipment t ensure cmpliance with this prduct specificatin. Specific testing f all circuit parameters is nt necessarily perfrmed.