Basic I/O Interface Dr. Mohammed Morsy

Transcription

1 Basic I/O Interface Dr. Mhammed Mrsy

2 Basic I/O Interface This chapter will discuss: I/O instructins. Handshaking. I/O Decding. 82C55 prgrammable parallel interface prgrammable interval timer.

3 Basic I/O Instructins IN and OUT transfer data between an I/O device and the micrprcessr's accumulatr (AL, AX r EAX). The I/O address is stred in: Register DX as a 16-bit I/O address (variable addressing). The byte, p8, immediately fllwing the pcde (fixed address). Only 16-bits (A 0 t A 15 ) are decded. Address cnnectins abve A 15 are undefined fr I/O instructins. INS and OUTS transfer t I/O devices using ES:DI and DS:SI, respectively.

4 Islated and Memry- Mapped I/O In the Islated scheme, IN, OUT, INS and OUTS are required. In the Memry-mapped scheme, any instructin that references memry can be used

5 Basic I/O Interface The basic input device (t the micrprcessr) is a set f tri-state buffers.

6 Basic I/O Interface The basic utput device (frm the micrprcessr) is a set f latches.

7 Handshaking I/O devices are typically slwer than the micrprcessr. Handshaking is used t synchrnize I/O with the micrprcessr. A device indicates that it is ready fr a cmmand r data (thrugh sme I/O pin r prt). The prcessr issues a cmmand t the device, and the device indicates it is busy (nt ready). The I/O device finishes its task and indicates a ready cnditin, and the cycle cntinues. There are tw basic mechanisms fr the prcessr t service a device. Plling (Prcessr initiated): Device indicates it is ready by setting sme status bit and the prcessr peridically checks it. Interrupts (Device initiated): The act f setting a status bit causes an interrupt, and the prcessr calls an ISR t serve the device.

8 I/O Prt Decding Fr memry-mapped I/O, decding is identical t memry decding. Fr islated I/O, IORCand IOWC are develped using M/ IO and W/ R pins f the micrprcessr. The 8-bit and 16-bit I/O prt address decding are similar t the memry decding. The I/O banks n the 8086 thrugh the 80386SX are als set up like the memry with bank enbable BEx signals.

9 8086 I/O Prt Decding Example Write the PAL equatins fr this I/O interface?

10 Prgrammable Peripheral Interface (82C55) The 82C55 is a ppular interfacing cmpnent, that can interface any TTL-cmpatible I/O device t the micrprcessr. It is used t interface the keybard and parallel printer prt in PCs (usually as part f an integrated chipset). Requires insertin f wait states if used with a micrprcessr using higher that an 8 MHz clck.

11 82C55 PPI PPI has 24 pins fr I/O that are prgrammable in grups f 12 pins. It has three distinct mdes f peratin. Mde 0: is the basic input/utput mde. Mde 1: is the strbed peratins Mde 2: is a bidirectinal mde f peratin In the PC, an 82C55 r its equivalent is decded at I/O prts 60H-63H.

12 82C55 PPI Pinut

13 Interfacing the 82C55 PPI

14 Prgramming the 82C55

15 82C55: Mde 0 Operatin - Seven Segment LED Display Example

16 82C55: Mde 0 Operatin - Seven Segment LED Display Mde 0 peratin causes the 82C55 t functin as a buffered input device r as a latched utput device. In previus example, bth prts A and B are prgrammed as (mde 0) simple latched utput prts. Prt A prvides the segment data inputs t display and prt B prvides a means f selecting ne display psitin at a time. Different values are displayed in each digit via fast time multiplexing. The values fr the resistrs and the type f transistrs used are determined using the current requirements.

17 Seven Segment LED Display Sftware ;Sftware t initialize the 8255 MOV AL, B OUT COMMAND,AL ;Prcedure t display the data DISPLAY PROC NEAR MOV BX,8 MOV AH,7FH MOV SI, OFFSET DISPLAY_RAM1 Display1: MOV AL, AH OUT PORTB,AL MOV AL, [BX+SI] OUT PORTA, AL CALL DELAY RAR AH DEC BX JNZ DISPLAY1 RET DISPLAY ENDP

18 82C55: Mde 1 Strbed Input Prt A and/r prt B functin as latching input devices. External data is stred in the prts until the micrprcessr is ready. Prt C used fr cntrl r handshaking signals (cannt be used fr data).

19 82C55: Mde 1 Strbed Input Signal definitins fr Mde 1 Strbed Input STB: The strbe input lads data int the prt latch. IBF: Input buffer full is an utput indicating that the input latch cntains infrmatin INTR: Interrupt request is an utput that requests an interrupt INTE: The interrupt enable signal is neither an input nr an utput; it is an internal bit prgrammed via the PC4 (prt A) r PC2 (prt B) bits. PC7, PC6 The prt C pins 7 and 6 are general-purpse I/O pins that are available fr any purpse.

20 Mde 1 Strbed Input Timing

21 Mde 1 Strbed Input Mde 1 Strbed Input Example Keybard encder debunces the key-switches, and prvides a strbe whenever a key is depressed. DAV is activated n a key press strbing the ASCIIcded key cde int Prt A.

22 Mde 1 Strbed Input Prcedure that read an ASCII character frm the keybard via prt A. BIT5EQU 20H READ_KEYPROC NEAR IN AL, PORTC TEST AL, BIT5 JZ READ_KEY IN AL, PORTA RET READ_KEYENDP

23 Mde 1 Strbed Output Similar t Mde 0 utput peratin, except that handshaking signals are prvided using prt C. Signal Definitins fr Mde 1 Strbed Output OBF: Output buffer full is an utput that ges lw when data is latched in either prt A r prt B. Ges high n ACK. ACK: The acknwledge signal causes the OBF pin t return t 1. This is a respnse frm an external device. INTR: Interrupt request is an utput that requests an interrupt. INTE: The interrupt enable signal is neither an input nr an utput; it is an internal bit prgrammed via the PC6 (prt A) r PC2 (prt B) bits. PC5, PC4 The prt C pins 5 and 4 are general-purpse I/O pins that are available fr any purpse.

24 Mde 1 Strbed Output Timing

25 Mde 1 Strbed Output Mde 1 Strbed Output Example:

26 Mde 1 Strbed Output Prcedure that write an ASCII character t the printer. BIT1 EQU 2 PRINT PROC NEAR ;Check printer ready IN AL, PORTC TEST AL, BIT1 JZ PRINT ;Send character MOV AL,AH OUT PORTB,AL ;Send DS MOV AL, B OUT COMMAND, AL MOV AL, B OUT COMMAND,AL RET PRINT ENDP

27 Mde 2 Bi-directinal Operatin Only allwed with prt A. Bi-directinal bused data used fr interfacing tw cmputers. Timing diagram is a cmbinatin f the Mde 1 Strbed Input and Mde 1 Strbed Output Timing diagrams.

28 Mde 2 Bi-directinal Operatin INTR: Interrupt request is an utput that requests an interrupt. OBF: Output buffer full is an utput indicating that the utput buffer cntains data fr the bi-directinal bus. IFB: Input buffer full is an utput indicating that the input latch cntains infrmatin fr the external bi-directinal bus ACK: Acknwledge is an input that enables tri-state buffers which are therwise in their high-impedance state. STB: The strbe input lads data int the prt A latch INTE: Interrupt enable are internal bits that enable the INTR pin. Bit PC6(INTE1) and PC4(INTE2) PC2, PC1, and PC0: These pins f prt C are generalpurpse I/O pins that are available fr any purpse.

29 Prgrammable Interval Timer: 8254 Three independent 16-bit prgrammable cunters (timers). Each capable f cunting in binary r BCD with a maximum frequency f 10MHz. Used fr cntrlling real-time events such as realtime clck, event cunter, and mtr speed and directin cntrl. Usually decded at prt address 40H-43H and has the fllwing functins: Generates a basic timer interrupt that ccurs at apprximately 18.2Hz. Interrupts the micr at interrupt vectr 8 fr a clck tick. Causes DRAM memry system t be refreshed. Prgrammed with 15us n the PC/XT. Prvides a timing surce t the internal speaker and ther devices.

30 8254 Functinal Descriptin

31 8254 Pin Definitins A 1, A 0 : The address inputs select ne f the fur internal registers with the 8254 as fllws: CLK: The clck input is the timing surce fr each f the internal cunters. CS: Chip Select enables the 8254 fr prgramming, and reading and writing. G: The gate input cntrls the peratin f the cunter in sme mdes. OUT: A cunter utput is where the wave-frm generated by the timer is available. RD/WR: Read/Write causes data t be read/written frm the 8254 and ften cnnects t the IORC/IOWC.

32 8254 Prgramming Each cunter may be prgrammed with a cunt f 1 t FFFFH. Minimum cunt is 1 all mdes except 2 and 3 with minimum cunt f 2. Each cunter has a prgram cntrl wrd used t select the way the cunter perates. If tw bytes are prgrammed, then the first byte (LSB) stps the cunt, and the secnd byte (MSB) starts the cunter with the new cunt.

33 8254 Prgramming Each cunter is individually prgrammed by writing a cntrl wrd, fllwed by the initial cunt. The cntrl wrd allws the prgrammer t select the cunter, mdel f peratin, binary r BCD cunt and type f peratin (read/write).

34 8254 Mdes f Operatin There are 6 mdes f peratin fr each cunter: Mde 0: An events cunter enabled with G. The utput becmes a lgic 0 when the cntrl wrd is written and remains there until N plus the number f prgrammed cunts.

35 8254 Mdes f Operatin Mde 1: One-sht mde. The G input triggers the cunter t utput a 0 pulse fr a predetermined number f clck cycles. Cunter reladed if G is pulsed again.

36 8254 Mdes f Operatin Mde 2: Cunter generates a series f pulses 1 clck pulse wide. The separatin between pulses is determined by the cunt. The cycle is repeated until reprgrammed r G pin set t 0.

37 8254 Mdes f Operatin Mde 3: Generates a cntinuus square-wave with G set t 1. If cunt is even, 50% duty cycle therwise OUT is high 1 cycle lnger.

38 8254 Mdes f Operatin Mde 4: Sftware triggered ne-sht (G must be 1). Mde 5: Hardware triggered ne-sht. G cntrls similar t Mde 1 (G is active-high).

39 Example: Generating a Wavefrm with the 8254 Write an assembly prgram t generate a 100KHz square-wave using the fllwing circuit. (A bk example)

40 Reading a Cunter Each cunter has an internal latch read with the read cunter prt peratin. the latches will nrmally fllw the cunt If cunter cntents are needed, the latch can remember the cunt by prgramming the cunter latch cntrl wrd. cunter cntents are held in a latch until read

41 Reading a Cunter When a read frm the latch r cunter is prgrammed, the latch tracks the cntents. When necessary fr cntents f mre than ne cunter t be read at the same time, the readback cntrl wrd is used

42 Reading a Cunter With the read-back cntrl wrd, the CNT bit is lgic 0 t cause the cunters selected by CNT0, CNT1, and CNT2 t be latched. If the status register is t be latched, then the ST bit is placed at lgic 0. The status register shws: the state f the utput pin whether the cunter is at its null state (0) hw the cunter is prgrammed

43 Prgrammable Cmmunicatin Interface: A universal asynchrnus receiver/transmitter (UART). Operatin speed: 0-1.5M Baud (Baud is # f bits transmitted/sec, including start, stp, data and parity). UART cntains: A prgrammable Baud rate generatr. Separate FIFO buffers fr input and utput data(16 bytes each).

44 Prgrammable Cmmunicatins Interface: Asynchrnus serial data: Transmitted and received withut a clck r timing signal. Tw 10-bit frames f asynchrnus data. 7- r 8- bit ASCII, e.g. w r w/ parity, is pssible.

45 Prgrammable Cmmunicatins Interface: Tw separate sectins are respnsible fr data cmmunicatins: Receiver Transmitter Can functin in: simplex: transmit nly half-duplex: transmit and receive but nt simultaneusly full-duplex: transmit and receive simultaneusly

46 Pinut f the A 0, A 1 and A 2 : Select an internal register fr prgramming and data transfer.

47 Pinut f the ADS: Address strbe used t latch the address and chip select. Nt needed n Intel systems -- cnnected t grund. BAUDOUT: Clck signal frm Baud rate generatr in the transmitter. CS 0, CS 1, CS 2 : Chip selects. CTS: Clear t send -- indicates that the mdem r data set is ready t exchange infrmatin (Used in half-duplex t turn the line arund). D 7 -D 0 : The data bus pins are cnnected t the micrprcessr data bus. DCD: The data carrier detect -- used by the mdem t signal the that a carrier is present.

48 Pinut f the DDIS: Disable driver utput -- set t 0 t indicate that the micrprcessr is reading data frm the UART. Used t change directin f data flw thrugh a buffer. DSR: Data set ready is an input t indicates that the mdem (data set) is ready t perate. DTR: Data terminal ready is an utput -- indicates that the data terminal (16550) is ready t functin. INTR: Interrupt request is an utput t the micr -- used t request an interrupt. Receiver errr, Data received, Transmit buffer empty MR: Master reset -- cnnect t system RESET OUT 1, OUT 2 : User defined utput pins fr mdem r ther device. RCLK: Receiver clck -- clck input t the receiver sectin f the UART. Always 16X the desired receiver Baud rate.

49 Pinut f the RD, RD: Read inputs (either can be used) -- cause data t be read frm the register given by the address inputs. RI: Ring indicatr input -- set t 0 by mdem t indicate telephne is ringing. RTS: Request-t-send -- signal t mdem, indicating UART wishes t send data. SIN, SOUT: Serial data pins, in and ut. RXRDY: Receiver ready -- used t transfer received data via DMA techniques. TXRDY: Transmitter ready -- used t transfer transmitter data via DMA. WR, WR: Write (either can be used) -- cnnects t micr write signal t transfer cmmands and data t XIN, XOUT: Main clck cnnectins --a crystal scillatr can be used.

50 Prgramming the Tw phases: Initializatin, peratin. Initializatin: After RESET, the line cntrl register and baud rate generatr need t be prgrammed. Line cntrl register sets the # f data bits, # f stp bits and the parity. Addressed at lcatin 011.

51 Prgramming the Initializatin (cnt.): ST, P and PE used t send even r dd parity, t send n parity r t send a 1 r a 0 in the parity bit psitin fr all data. SB = 1 causes a break t be transmitted n SOUT. A break is at least tw frame f 0 data. DL = 1 enables prgramming f the baud rate divisr.

52 Prgramming the Initializatin (cnt.): Baud rate generatr is prgrammed with a divisr that sets baud rate f the transmitter. Baud rate generatr is prgrammed at 000 and 001. Prt 000 used t hld least significant byte, 001 mst significant. Value used depends n external clck/crystal frequency. Fr MHz crystal, 10,473 gives 110 baud rate, 30 gives 38,400 baud. Nte, number prgrammed generates a clck 16X the desired Baud rate. Last, the FIFO cntrl register must be prgrammed at 010.

53 Prgramming the Operatin: Status line register gives infrmatin abut errr cnditins and state f the transmitter and receiver. This register needs t be tested in sftware rutines designed t use the t transmit/receive data. Fr example, suppse a prgram wants t send data ut SOUT. It needs t pl the TH bit t determine if the transmitter is ready t receive data. T receive infrmatin, the DR bit is tested.

54 Prgramming the Operatin (Cnt.): It is als a gd idea t check fr errrs. Parity errr: Received data has a wrng bit-- transmissin bit flip due t nise. Framing errr: Start and stp bits nt in their prper places. This usually results if the receiver is receiving data at the incrrect baud rate. Overrun errr: Data has verrun the internal receiver FIFO buffer. Sftware is failing t read the data frm the FIFO. Break indicatr bit: Sftware shuld check fr this as well, i.e. tw cnsecutive frames f 0s.

55 Example f Write an assembly prgram t initialize, transmit, and receive data frm the shwn UART. (Bk examples)