III. Product Specification Preliminary. Z8(j~SIO. Structure. Features MARCH 1978

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1 Z8(j~SO Prduct Specificatin Preliminary MARCH 1978 The Zilg Z80 prduct line is a cmplete set f micrcmputer cmpnents, develpment systems and supprt sftware. The Z80 micrcmputer cmpnent set includes all f the circuits necessary t build high-perfrmance micrcmputer systems with virtually n ther lgic and a minimum number f lw cst standard memry ejements. The Z80-SO (Serial nput/output) circuit is a prgrammable, dual-channel device which prvides frmatting f data fr serial data cmmunicatin. t is capable f handling asynchrnus, synchrnus and synchrnus bit riented prtcls such as BM BiSync, HOLC, SOLC and virtually any ther serial prtcl. t can genera te CRC cdes in any synchrnus mde and can be prgrammed by the CPU fr any traditinal asynchrnus frmat. Structure N-channel Silicn Gate Depletin Lad Technlgy Frty Pin DP Single 5 vlt pwer supply Single phase 5 vlt clck Tw Full Duplex channels Features Tw independent full duplex channels Oata rates - 0 t 550K bits/secnd Receiver data registers quadruply buffered; transmitter dubly buffered. Asynchrnus peratin 5,6,7 r 8 bits/character, l\hr 2 stp bits Even, dd r n parity x, x 16, x32 and x 64 clck mdes Break generatin and detectin Parity, Overrun and Framing errr detectin Binary Synchrnus peratin nternal r external character synchrnzatin One r tw Sync characters in separate registers Autmatic Sync Character nsertin CRC generatin and checking HOLC r BM SDLC peratin Autmatic Zer insertin and deletin Autmatic Flag insertin Address field recgnitin -field residue handling Valid receive messages prtected frm verrun CRC generatin and checking Eight mdem cntrl inputs and utputs Bth CRC-16 and CRe-CCTT (-0 and -) are implemented Daisy chain pririty interrupt lgic included t prvide fr autmatic interrupt vectring withut external lgic. All inputs and utputs fully TTL cmpatible. NTERNAL +5V GND () CONTROL LOGC SERAL OATA CHANNEL CLOCK SYNC WATROY OATA CONTROL CPU MOOEM OR BUS OTHER 1/0 CONTROLS NTERRUPT CONTROL LOGC SERAL OATA CHANNEL CLOCK SYNC WATlROY NTERRUPT CONTROL LNES FGURE 1 SO BLOCK DAGRAM TM 280 is a trademark f Zilg, nc.

2 SO Architecture A blck diagram f the SO is shwn in Figure 1. The internal structure includes a l80-cpu bus interface, internal cntrl and interrupt lgic and tw full duplex channels. The interrupt cntrl lgic determines which channel and which device within the channel is the highest pririty fr purpses f the autmatic interrupt vectring. Pririty is fxed with Channel A assigned higher pririty than Channel B and the Receiver, Transmitter and External/Status assigned pririty in that rder within each channel. The channel lgic is shwn in blck frm in Figure 2. Each channel has five 8-bit cntrl registers, tw 8-bit status registers and tw 8-bit sync character registers. The interrupt vectr is written int an additinal 8-bit register in Channel B and may als be read thru that channel. The receiver has three 8-bit buffer registers in FFO arrangement in additin t the 8-bit input shift register. The transmitter has ne 8-bit buffer register in additin t the 8-bit utput shift register. The CRC generatr/checkers are 16 bit shift registers with apprpriate internal feedback (prgrammable) fr tw different CRC cdes. Z80-SO Pin Descriptin ,.. 39 D2 cpu OATA 4 38 BUS D D ,"0 CONTROL { FROM CPU CE RESET M1 10RO RD +5V GNO <> DASY { NT CHAN NTERRUPT le CONTROL leo Z80-S ~ " c/ B/A / / / CRC GENERATOR / TxD TxC SHFT XMT& BT Lh XMT ki """' ~"" LB;Y j REGSTERS ~/y... SYNC CHANNEL (l NTERNAL BUS CONTROL.4 ~ / /1 REC CRC CHECKER '---- & STATUS V <V' ~ /./ / FFO REC SHFT & BT STRP SYNC OETECT WAT/ ROY B/A CD CE M le leo System Data Bus (bidirectinal, tristate) Channel B r A select (input high is Channel B) Cntrl r Data select (input high is cntrl) Chip Enable (input, active lw) Machine Cycle One Signal frm l80 CPU (input, active lw) nput/output request frm l80-cpu (input, active lw) Read Cycle Status frm the l80-cpu (input, active lw) System Clck (input) Reset (input, active lw) disables bth receivers and transmitters. TxDA and TxDB are frced marking. Mdem cntrls are frced high. Cntrl registers must be rewritten after SO is reset and befre any data is transmitted r received. All interrupts are disabled. nterrupt Enable n (input, active high) nterrupt Enable Out (utput, active high) le and leo frm a daisy-chain cnnectin fr pririty interrupt cntrl. nterrupt Request (utput, pen drain, active lw). RxD RxC FGURE 2 CHANNEL BLOCK DAGRAM 2

3 Z80-SO Pin Descriptin ) *See nte belw n bnding ptin. WAT/READY A WAT/READY B RxDA,RxDB TxDA,TxDB S0/0* RxDA RxCA TxDA TxCA SYNCA W!RDYA RTSA} CTSA MODEM DTRA CONTROL DCDA RxDB RxTxCB TxDB SYNCB W!RDYB RTSB} CTSB MODEM DTRB CONTROL DCDB CH-A CH-B Tw pins, ne fr each channel. They may be prgrammed t serve as ready lines fr use with a DMA Cntrller r they may serve as wait lines t synchrnize the Z80-CPU t the SO data rate. Clear t Send (2 pins, inputs, active lw). When prgrammed as "aut enables," these inputs inhibit the transmitters f their respective channels. f these pins are nt prgrammed as transmitter enables, they may be prgrammed as general-purpse input pins. These inputs are Schmitt-trigger buffered t allw slw-risetime inputs. Data Carrier Detect (2 pins, inputs, active lw.) These pins are similar t the CTS inputs, except that they are usable as receiver inhibits rather than transmitter inhibits. Receive Data. (2 pins, inputs, active high.) Transmit Data. (2 pins, utputs, active high.) Receiver Clcks (inputs, active lw.) (Tw pads, ne per channel. See nte n Bnding Optin.) Clck may be x, x16, x32 r x64 the data rate in asynchrnus mdes. Transmitter Clcks (inputs, active high.) (Tw pads, ne per channel. See nte n Bnding Optin.) May be xl, x16, x32 r x64 baud rate, but same multiplier must be bserved as fr receiver. The TxC and RxC inputs are Schmitttrigger buffered, fr relaxed rise and fall time requirements. *These clcks can be directly driven by the Z80-CTC (Cunter Timer Circuit) fr fully prgrammable baud rate generatin. 3 sl/a Request t Send (2 pins, utputs, active lw.) When the RTS bit is set, the RTS pin ges lw. When the bit is reset in asynchrnus mde, the pin ges high, but nly after the transmitter is empty. n synchrnus mdes, RTS is a simple utput which strictly fllws the state f the RTS bit. Data Terminal Ready (2 pins, utput, active lw.) Pin fllws state prgrammed with DTR bit. (Tw pads, ne per channel. See nte n Bnding Optin.) External Character Synchrnizatin (2 pins, input/utput, active lw.) f the External Synchrnizatin mde is selected, assembly f characters will begin n the next rising edge f RxC. f internal character sync mdes are selected, the pins are utputs that are active during part f the clck cycles that a sync character is recgnized. The sync cnditin is nt latched, s this pin will be active every time a sync pattern is recgnized, regardless f character bundaries. n asynchrnus mdes, these pins are simple inputs t the Hunt/Sync bits in Status Register 0 and may be used fr any input functin desired. NOTE: When used as an external synchrnizatin pin, it must nt becme active fr three system clck cycles after the previus rising edge f RxC. This requirement nrmally can be met by allwing SYNC t change nly n the falling edge f RxC. Nte n Bnding Optin: Due t package cnstraints, there are nly tw pins available fr the three signals, TxCB, RxCB and DTRB. They are nrmally bnded s that TxCB and RxCB are ne pin, and RxTxCB and DTRB is an available utput. f there is a requirement fr different clck rates r phases fr RxCB and TxCB, they may be bnded independently by sacrificing DTRB. SO TxDB DTRB SO/1 27 RxTxCB RxCB TxCB -TxDB \ OPTONAL~ BONDNG

4 SO Timing Wavefrms T 2 T W T 3 T, READ CYCLE The timing assciated with reading data r a status register within the SO is illustrated here. Z80 nput instructins satisfy this timing. X CHANNEL ADDRESS X \ / \ / DATA ( OUT ) T 2 T w T 3 T, "> WRTE CYCLE llustrated here is the timing assciated with a data r cntrl byte being written int the SO. Z80 Output nstructins satisfy this timing. X CHANNEL ADDRESS X \ / DATA -JX'- 'N_~x== NTERRUPT ACKNOWLEDGE CYCLE Sme time after an interrupt is requested by the SO, the CPU will send ut an interrupt acknwledge (Ml and ORQ.) During this time, the interrupt lgic f the SO will determine the highest pririty functin which is requesting an interrupt. T insure that the daisy chain enable lines stabilize, channels are inhibited frm changing their interrupt request status when M1 is active (lw). f the SO is the highest pririty device requesting an interrupt, the SO will place the apprpriate interrupt vectr n the data bus when ORQ ges active. '' 'ORO \ / 'E ======= -.1 \.. _ DATA ( VECTOR ) RETURN FROM NTERRUPT CYCLE f a Z80 peripheral device has n interrupt pending and is nt under service, then its leo =le. f it has an interrupt under service (i.e. it has already interrupted and received an interrupt acknwledge) then its leo is always lw, inhibiting lwer pririty chips frm interrupting. fit has an interrupt pending which has nt yet been acknwledged, leo will be lw unless an "ED" is decded as the first byte f a tw byte pcde. n this case, leo will g high until the next pcde byte is decded, whereupn it will again g lw. f the secnd byte f the pcde was a "4D" then the pcde was an RET instructin. After an "ED" pcde is decded, nly the peripheral device which has interrupted and is currently under service will have its le high and its leo lw. This device is the highest pririty device in the daisy chain which has received an interrupt acknwledge. All ther peripherals have 4 'le led ,, J '1 le = leo. f the next pcde byte decded is "4D", this peripheral device will reset its "interrupt under service" cnditin. Wait cycles are allwed in the M cycles, but cannt be used t extend high t lw daisy chain ripple time. Wait cycles hwever, may be used fr lw t high daisy chain ripple during 4D.

5 Timing Wavefrms (cntinued) Daisy Chain nterrupt Servicing The fllwing illustratin is a typical nested interrupt sequence which may ccur in the SO. n a system with several peripheral chips, the ther chips may be included in the daisy chain with either higher r lwer pririty than the SO channels. n this sequence, the transmitter f Channel B interrupts and is granted service. While it is being serviced, an external/ status interrupt frm Channel A ccurs and is granted service. The service rutine fr the Channel A interrupt is cmpleted and either the RET instructin is executed r the RET! cmmand is written int the SO t indicate t Channel A that the external/status interrupt rutine is cmplete. At this time, the service rutine fr the Channel B transmitter is resumed. When this rutine is cmpleted, anther RET! instructin is executed t cmplete the service. CHANNEL A RECEVER CHANNEL A TRANSMTTER CHANNEL A EXTERNAL! STATUS CHANNEL B RECEVER CHANNEL B TRANSMTTER CHANNEL B EXTERNAL! STATUS + ~E Hi Hi Hi Hi Hi Hi leo...-- le leo le leo-- le leo le leo-- le leo-- 1. Pririty nterrupt Daisy Chain befre any interrupt ccurs. + UNDER SERVCE Hi Hi Hi Hi Hi L L le leo-- le leo le leo le leo - le leo-- le leo- 2. Channel B's transmitter interrupts and is acknwledged. + UNDER SERVCE SERVCE SUSPENDED Hi Hi Hi L L L L le leo ~ le leo le leo - le leo - le leo - le leo - 3. External/Status f Channel A interrupts suspending service f Channel B transmitter + SERVCE COMPLETE SERVCE RESUMED Hi Hi Hi Hi Hi L L le leo le leo le leo le leo le leole leo-- 4. Channel A External/Status rutine cmplete. RET issued, Channel B transmitter service resumed. + SERVCE COMPLETE Hi Hi Hi Hi Hi Hi Hi le leo...-- le leo le leo-- le leo le leo ~ le leo-- 5. Channel B transmitter's service rutine cmplete, secnd RET issued. 5

6 Operatin Of SO (cntinued) Operatin f the SO is determined by the cntents f the cntrl registers. These must be prgrammed befre any peratins can be perfrmed by the SO. Sme cmmands and mdes may be changed during peratin. The device status registers can be read at any time. ASYNCHRONOUS MODES The receiver prts are quadruply buffered, i.e. there are three strage registers in additin t the input shift register. This allws additinal time fr the CPU t service an interrupt at the beginning f a blck f high-speed da ta transfer. The errr flags are als quadruply buffered and are laded at the same time as the character. The Receiver Overrun and Parity Errr flags are nt reset unless an Errr Reset, (latches) Cmmand (Cmmand 6) is issued. End f Frame and CRC/ Framing errr reflects the state f the character currently in the buffer unless reset by errr reset. Thus, when the errr status is read, it will reflect an errr in the current wrd in the receive buffer in additin t any parity r verrun errrs received since the last Errr Reset, (latches) Cmmand. n rder t keep crrespndence between the state f the errr buffer and the cntents f the receive registers, the status register shuld be read befre the data (see exceptin). This is easily accmplished if the vectred interrupts are used since a special interrupt vectr is generated fr errrs r end f frame. f the status is read after the data is read, the errr data fr the next data wrd will als be included if it has been stacked in the buffer. f peratins are being perfrmed rapidly enugh s that the next character will nt yet be received, then the status register will remain valid. The exceptin ccurs when the "Receive nterrupt n First Character Only" mde is selected. A special interrupt in this mde will hld errr data and the character itself (even if read frm the buffer) until the Errr Reset, (latches) Cmmand is issued. This prevents further data frm becming available in the receiver until the Reset is issued. f the nterrupt n Every Character mde is selected, the interrupt vectr will be different if errr states exist in the status register. f receiver verrun shuld ccur, despite the quadruple buffering, the mst recent character received will be laded. The character preceding it will be lst. When the character whch has been written ver ther characters is read, the Overflw bit will be set and the "Special Receive Cnditin" vectr returned if "Status Affects Vectr" is enabled. t is pssible t use the SO in a plled envirnment. This requires mnitring f the "Receive Character Available" bit t knw when t read a character. This bit is reset autmatically when the receive buffers are all empty. The "Transmit Buffer Empty" bit is high whenever the transmit buffer is empty. n plled peratin, it shuld be checked befre writing data int the transmitter t prevent verwriting f data. MARKNG LNE 'J TRANSTONS OCCUR ON A FALLNG EDGE OF TxC. ASYNCHRONOUS FORMAT START D D, D C MAY BE PRESENT OR NOT, EVEN OR ODD N PARTY STOP MARKNG LNE / \ 1, 1% OR 2 BTS TRANSMSSO A data character sent by the SO will be assembled as fllws in asynchrnus mdes: dle state (n characters being sent) is a marking line (high) unless a break has been prgrammed in the cntrl register, in which case, the line will remain spacing until the "send break" cmmand has been remved r the chip is reset. Transmissin cannt begin unless the Transmit Enable bit is set. f the Aut Enables ptin is selected, then CTS must be lw as well. f the 5 bits/character mde is selected, then unused bits (D s, D 6 and D 7 ) must be zer in each data byte written int the SO. RECEVNG Asynchrnus receptin will begin when the Receiver Enable bit is set. f the Aut Enables ptin is selected, the DCD must be lw as well. A lw (spacing) cnditin n RxD indicates a start bit. f the lw persists fr ~ bit time, the start bit is assumed t be valid and the data input is then sampled at mid-bit time until the entire character is assembled. This methd f detecting a start bit imprves errr rejectin when nise spikes exist n an therwise marking line. f the X clck mde is selected, bit synchrnizatin must be accmplished externally. 6

7 Synchrnus Mdes The varius synchrnus mdes all require a xl clck fr transmissin and receptin. Data is sampled n the rising edge f RxC. Transmitter data transitins ccur n the falling edge f TxC. n all cases, the receiver is in a hunt mde after a reset (internal r external). The hunt can begin nly when the receiver is enabled. Only when character synchrnizatin has been achieved can data transfer begin. f there is a lss f character synchrnizatin, the hunt mde can be reentered by writing a cntrl wrd with the "Enter Hunt Mde" bit set. The differences in peratin f the mnsync, bisync and external sync mdes are nly in the manner in which initial synchrnizatin is achieved. Nte: The mde f peratin must be selected befre the sync characters are laded, since the registers are used differently in the varius mdes. MONOSYNC; (8-BT SYNC MODE) Matching f a single sync character, prgrammed int Write register 7, implies character synchrnizatin, which enables data transfer. BSYNC: (l6-bt SYNC MODE) Matching f tw adjacent sync characters prgrammed in Write Registers 6 and 7 implies character synchrnizatin. n bth mnsync and bisync mdes, the SY C pin will be active (lw) any time the sync character sequence is detected and will remain lw fr the clck cycle in which it is detected. EXTERNAL SYNC MODE n this mde, character assembly begins n the first rising edge f RxC after the SYNC pin becmes active (lw). t shuld be held active fr at least three cmplete clck cycles. n Mnsync, Bisync and External sync mdes, assembly will cntinue until the SO is reset (either internally r with the Reset pin) r until the receiver is disabled (by cmmand r with the DCD pin in the Aut Enables Mde) r until the CPU sets the "Enter Hunt Mde" bit. After initial synchrnizatin has been achieved, the Mnsync, Bisync, and External Sync mdes are very similar. Any differences will be nted in the fllwing, which is meant t apply t all three mdes. SYNCHRONOUS FORMATS MONOSYNC MESSAGE FORMAT (nternal Sync Detect), r \,'r , , SYNC CHARACTER DATA )) FELD CRC CRC CHARACTER CHARACTER #1 #2...,;,..._ '" '\ )) BSYNC MESSAGE FORMAT (nternal Sync Detect), r------_------\( '\ , ,~----_ SYNC SYNC J J CRC CRC CHARACTER CHARACTER DATA FELD CHARACTER CHARACTER #1 ~ #1 ~ '" \('r ~ }} EXTERNAL SYNC DETECT FORMAT, ~(r , ,r ----~ CRC CRC DATA FELD CHARACTER CHARACTER #1 #2 L \ (~ ' _-... ) 7

8 Synchrnus Mde (cntinued) C"...1. c'c L 'c r+ SOLe Tr"nsmissin, A, Default state (after a Reset r transmitter nt enabled) is a marking line. Break may be prgrammed t generate a spacing line, which begins as sn as prgrammed, regardless f the cntents f the send register. With the transmitter enabled, and after mdes have been selected, default is cntinuus transmissin f the 8 r 16 bit sync character depending n which mde is selected. B. Several nterrupt mdes are pssible: 1. Transmit interrupts enabled - every time that the transmit buffer becmes empty, an interrupt will be generated if the "Transmit nterrupt Enable" bit is set. The interrupt may be satisfied by either writing anther character int the transmitter r by resetting the Transmitter nterrupt pending latch with the "Reset Transmitter nterrupt Pending" cmmand (Cmmand 5). f the interrupt is satisfied with this cmmand and nthing mre is written int the transmitter, there will be n further transmitter interrupts, as it is the buffer becming empty that causes the interrupt. When anther character is written, the transmitter can again becme empty and interrupt again. 2. External/Status interrupts enabled - f the External! Sta tus nterrupt Enable bit is set, Transmitter cnditins such as starting t send CRC characters, starting t send Sync characters, and CTS changing state cause interrupts, which have a unique vectr if "Status Affects Vectr" is set. 3. All interrupts may be disabled fr peratin in a plled mde r t prevent interrupts at inapprpriate times in a prgram's executin. The CRC generatr shuld be reset by issuing the "RESET TRANSMT CRC GENERATOR" Cmmand, befre any data is laded. After CRC and the entire transmitter is enabled, data may be laded. Befre CRC is t be sent (but after the first data has been laded), the CRC/SYNC SENT/SENDNG flag must be reset with the "RESET CRC/SYNC SENT SENDNG" Cmmand. Because sending f the CRC is inhibited when the CRC/ SYNCS SENT/SENDNG flag is set, the SO can be used t autmatically insert fill characters within messages instead f autmatically sending the CRC. CRC is nt calculated n syncs autmatically inserted and when the end f the message is reached, the flag can be reset, thus allwing the CRC t be sent. D. f the transmitter is disabled while a character is being sent, that character (whether Data r SYNC) will be sent as nrmal but will be fllwed by a marking line rather than CRC r sync characters. A character in the buffer when the transmitter is disabled will remain in the buffer. Hwever, a prgrammed break will be effective as sn as it is written int the cntrl register. Characters being transmitted, if any, will be lst. E. n all mdes, characters are sent lw-rder bits first,ie., D befre D], etc. fr as many bits as are prgrammed. This requires right-hand justificatin f data t be transmitted if wrd length is less than 8 bits. f wrd length is 5 bits r less, the special technique described in the "Transmit Bits/Char" sectin must be used fr the data frmat. C. f CRC is nlenabled, sync characters will autmatically be inserted when the transmitter has n data t send. An interrupt is generated nly after the first autmatically inserted sync character has been laded. f CRC is enabled, the first time the transmitter has n data t send, the 16 bit CRC is autmatically sent, fllwed by sync characters. While sending CRC, the "Sending CRC/SYNCS" bit is set and the "Transmit Buffer Empty" bit indicates full. CRC is nt calculated n the autmatically inserted sync characters, but it will be calculated n any sync character sent as data unless the CRe generatr is disabled when that character is la.ded t the transmit shift register frm the transmit buffer. When the CRC has been sent, the "Transmit Buffer Empty" bit ges high again, and an interrupt is generated t indicate that anther message can begin. Cntrl f the CRC generatr may prcede as fllws: 8

9 Synchrnus Mde (cntinued) Synchrnus Mdes (Except SOLe) Receptin: A. After prgramming the mde and sync characters (in that rder), the receiver may be enabled. t will then be in the Hunt Mde and will stay in that mde until: 1. A match is made with a single sync character (mnsync mde) r 2. A match is made with a dual sync character (BiSync mde) r 3. The external SYNC pin is frced lw. n cases (1) and (2) the external SYNC pin is an utput which indicates that character synchrnizatin has been achieved. n case (3) it is an input. B. Character assembly begins after sync has been achieved. Fur interrupt mdes are pssible. 1. N interrupts enabled - fr a purely plled peratin r fr "ff line" cnditins. 2. nterrupt n first character nly. This mde wuld nrmally be used t start a sftware plling lp r a blck transfer instructin using the WAT/READY utput t synchrnize the CPU t the incming data rate. t culd als be used with a OMA device. n this mde, the SO will interrupt n the first character and thereafter will nly interrupt if errrs are detected. The mde is reset with the "Reset Receive nterrupt n First Character" cmmand (Cmmand 4). The first character received after this cmmand is issued will als cause an interrupt. f External/Status interrupts are enabled, they may interrupt at any time. Parity errrs d nt cause interrupts in this mde, but End-f-Frame (SDLC Mde) and receiver verrun d cause interrupts. 3. nterrupt n every character - whenever the receiver buffer has a character an interrupt is generated. Errr and special cnditins generate a special vectr if the "Status Affects Vectr" mde is selected. A parity errr may ptinally nt generate the special vectr. C. CRC checking generatin may be used in the synchrnus mdes. 1. Calculatin f the CRC n a particular character begins 8 bit times after the wrd has been transferred t the receive buffer. f CRC is enabled befre the next character is transferred t the receive buffer, CRC will be calculated n the character. f CRC is disabled befre the time f the next transfer, calculatin will prceed n the wrd in prgress, but the wrd just transferred t the buffer will nt be included. This allws starting and stpping CRC checking n the varius characters emplyed in BiSync. 2. The CRC may be enabled and disabled as many times as necessary fr a given calculatin. 3. CRC Cdes are selected during the mde selectin prcess. Either the CRC-16 plynmial Xl 6 + XS + X2 + 1 r the SDLC plynmial X16 + X12 + XS + 1 may be used. n all except SOLC mde, the CRC calculatr and checker are reset t all O's. Transmitter and receiver must use the same plynmial. 4. n Mnsync, Bisync and External Sync mdes, the CRC/FRAMNG ERROR bit cntains the result f the cmparisn f the CRC checker t "all zers" 16 bit times after the character has been laded frm the receive shift register t the buffer. The cmparisn is made with each lad and is valid nly as lng as the character remains in the buffer. f time increases dwn the page, then the fllwing hlds: Character "A" laded int the buffer Character "B" laded int the buffer... f CRC is disabled befre "C" is in the buffer it will nt be calculated n "B". Character "C" laded int buffer... After "C" is laded the "CRC FRAMNG ERROR" bit shws the result f the cmparisn thru Character "A". Character "0" laded int buffer... After "0" is in buffer, the CRC ERROR bit shws the result f the cmparisn thru Character "B". Because f the serial peratin f the CRC calculatin, the receiver clck (RxC) must g thrugh 16 cycles after the CRC character has been laded int the receive buffer (20 cycles after the last bit is at the SO RxO pin) befre the CRC calculatin is cmplete. 9

10 Synchrnus Mde (cntinued) FLAG ADDRESS 8 BTS DATA " TRANSMSSON SDLC/HDLC Message Frmat ( ) (, ( ) ( ) FELD CRC CRC FLAG #1 # SDLC MODE TRANSMSSON: A. Nrmally, the CRC generatr shuld be reset (with the "Reset Transmit CRC Generatr" cmmand) befre a data blck is transmitted. Reset may ccur any time after the CRC f the previus message has been sent. During the time that CRC is being sent, the CRC/SYNC SENT/SENDNG bit will be set, but the TRANS BUFFER EMPTY bit will nt be set. After the CRC has been sent, the TRANS BUFFER EMPTY bit is set again, which will cause an interrupt signifying that the CRC has been sent, if transmit interrupts are enabled. B. The idle device state (if the transmitter is enabled) is cntinuus flags being transmitted. f the transmitter is nt enabled, a marking line is sent (idle line state). C. An abrt sequence may be sent by issuing the "Send Abrt" cmmand (Cmmand ). This causes at least 8 but less than 14 ne's t be sent befre the line reverts t cntinuus flags. Any data being transmitted and any data in the transmit buffer will be lst. D. One t 8 bits per character may be sent. See the Register Descriptin f Write Register 5, Transmit Bits Char. fr an explanatin f hw this is accmplished. Since the number f bits/character may be changed "n the fly", this feature may be used t fill a data field with any number f bits. When used in cnjunctin with the Receiver Residue Cdes, the SO may receive a message f any number f bits length and retransmit it exactly as received with n previus infrmatin abut the character structure f the -field (if any). A change in the number f bits/character will nt affect the character in the prcess f being shifted ut. Characters will be sent with the number f bits prgrammed at the time that the character is laded frm the buffer t the transmitter. E. As in ther synchrnus mdes, the tw byte CRC sequence will be sent autmatically when the transmhter has n mre data t send, i.e. when there is n character in the transmit buffer and the transmit shift register is empty. When the CRC sending begins, the CRC/SYNCS SENT/SENDNG bit is set and a status change interrupt is generated if external/status interrupts are enabled. This may be used as a transmitter underrun indicatin. After the CRC has been sent, the line reverts t cntinuus flags, withut shared zers, i.e Cntrl f the CRC generatr may prceed as fllws: O. Set up necessary mde (nly at initial pwer n), enable transmitter 1. Reset CRC generatr 2. Write first byte f data (i.e. address) 3. Reset CRC/SYNCS SENT/SENDNG bit 4. Write rest f data 5. After data is cmplete, CRC & flags will be sent autmatically, and this sequence can repeat frm 1. F. Extra zers are autmatically inserted in the data stream where required t fulfll the requirement f 5 nes maximum in a rw, except fr flags r abrts. G. When SDLC mde is selected, Reset f the CRC generatr is actually a preset t all 1's The SDLC CRC cde must be selected. 10

11 Synchrnus Mde (cntinued) FLAG ADDRESS 8 BTS RECEPTON SDLC/HDLC Message Frmat DATA " } } } } FELD CRC CRC FLAG #1 # SDLC OPERATON, RECEVER A. Data transfer beings with the first nn-flag character received after at least ne flag ( ) has been received if Address Search Mde has nt been enabled. f Address Search Mde is enabled, then a flag rllwed by either the prgrammed address r the glbal address ( ) is required befre data transfer will begin. 1. f interrupts are disabled, the presence f characters in the receive buffer can be detected by bserving the Receive Character Available bit in Read Register O. 2. f the "nterrupt n First Character Only" mde has been selected, this wuld nrmally be used t initiate a blck transfer. f the length f the message is unknwn, the "special cnditin" (End f Frame) interrupt may be used t exit the instructin r sftware lp. The "Reset nterrupt n first character" cmmand (Cmmand 4) must be issued befre an interrupt fr a fllwing blck's first character can be generated. 3. Flags are nt transferred. The extra zers inserted in transmissin are autmatically deleted. 4. Abrts are detected as 7 r mre ne's and cause a status interrupt (if enabled) with the Break/Abrt bit set in Read Register O. After the "Reset External/ Sta tus nterrupts" cmmand (Cmmand 2) has been issued, a secnd interrupt will ccur when the cntinuus ne's cnditin has been cleared. B. n SCLC mde, cntrl f the receive CRC checker is autmatic. t is reset by the leading flag and CRC is calculated up t the final flag. The byte which has the "End-f-Frame" bit set is the byte which cntains the result f the CRC check. f the CRC/Framing Errr bit is nt set, then the CRC indicates a valid message. A special check sequence is used fr the SDLC check because f the preset t all ne's. The final check must be C. Character length may be changed "n the fly." f address and cntrl bytes are prcessed as 8-bit characters, the receiver may be switched t a smaller character length during the time that the first infrmatin character is being assembled. This change must be made quickly enugh s that it is effective befre the number f bits specified have been assembled, i.e., if the change is t be frm the 8-bit cntrl t a 7-bit infrmatin field character length, the change must be made befre the first 7 bits f the -field have been assembled. D. f address search mde is nt used, r if messages have multi-byte addresses, an unwanted message need nt be cmpletely read by the CPU. Once the determinatin has been made that the message is nt needed, writing the "Enter Hunt Mde" bit will suspend receiptin until anther message headed by a flag has been received. E. When the trailing flag is received, an interrupt with a special vectr is generated (if enabled). This signals that the byte with the "End f Frame" bit set has been received. n additin t the results f the CRC check, Read Register 1 has 3 bits f Residue Cde valid at this time. Fr thse cases in which the number f bits in the -field is nt an integral multiple f the character length used, these bits indicate the bundary between the CRC check bits and the -field bits. Fr a detailed descriptin f the meaning f these bits, see the descriptin f the Residue Cdes in Read Register 1. F. Parity checking may be used n data in the infrmatin field nly if 5-7 bit characters are used and nly if a halfduplex prtcl is being used. (There are n separate cntrls fr parity n the receiver and transmitter s parity cannt, fr example, be simultaneusly disabled fr transmitting an 8-bit address and enabled fr receiving a 5-bit -field character). 11

12 SO Prgramming General The Z80-S10 is a multi-functin peripheral cmpnent specifically designed t satisfy a wide variety f serial data cmmunicatins requirements in micrcmputer systems. ts basic rle is that f a serial t parallel, parallel t serial cnverter/cntrller but within that rle it is cnfigured by systems sftware prgramming s that its functin r "persnality" can be ptimized fr a given serial data cmmunicatins applicatin. T prgram the Z80-S10 the systems sftware issues a series f cmmands that initialize the basic mde f peratin desired and ther cmmands t qualify cnditins within the mde selected i.e. Stp Bits, Bits/Char, Sync Char etc. The cmmand structure f the Z80-S10 is designed t take advantage f the pwerful Z80 BLOCK /O instruc- tins t simplify prgramming, minimize verhead and ptimize CPU interactin activities. Each f the tw channels f the Z80-S10 cntain cmmand registers that must be prgrammed via system sftware prir t functinal peratin. The channel select input (B/A) and the cntrl/data input (CD) are the cmmand structure addressing cntrls, nrmally cntrlled by the address bus f the Z80 CPU. C/D B/A Functin 0 0 Channel A Data 0 Channel B Data 0 Channel A Cmmands/Status Channel B Cmmands/Status Write Registers The Z80-SO cntains eight (8) registers in each channel that are prgrammed (written int) by the system sftware t cnfigure the functinal persnality f each channel. All Write Registers, with the exceptin f Write Register 0, require tw bytes t be prperly prgrammed. The first byte cntains 3 bits which pint t the selected register (DO-D2) the secnd byte is the actual cntrl wrd that is being written that register t cnfigure the SO. Write Register 0 is a special case. RESET (either internal cmmand r external input) will initialize the SO t Write Register O. All basic cmmands (CMD2-CMDO) and CRC cntrls (CRCO, CRC) can be accessed with a single byte using Write Register O. Cntained in the first byte f any Write Register access are the basic cmmands (CMD2-CMDO) and the CRC cntrls (CRCO,CRC) s that maximum system cntrl and flexibility is maintained. WRTE REGSTER 0 WRTE REGSTER 1 1 D7 D6 1 D5 D4 D3 D2 1 D1 DO REGSTER REGSTER REGSTER REGSTER REGSTER REGSTER REGSTER REGSTER 7 NULL CODE SEND ABORT (SDLC) RESET EXT. STATUS NTERRUPTS CHANNEL RESET RESET RxlNT ON FRST CHARACTER RESET TxlNT PENDNG ERROR RESET RETURN FROM NT (CH-A ONLY) D71D61D51D DO L... '---WAT/READY ON R/T WAT FN/READY FN WAT/READY ENABLE EXT. NT ENABLE '---- Tx NT ENABLE ' STATUS AFFECTS VECTOR (CHB ONLY) Rx NT DSABLE Rx NT ON FRST CHARACTER ONLY OR ERROR NT ON ALL Rx CHARACTERS (PARTY AFFECTS VECTOR) NT ON ALL Rx CHARACTERS (PARTY DOES NOT AFFECT VECTOR) NULLCODE RESET Rx CAC CHECKER RESET Tx CRG GENERATOR RESET CRC/SYNCS SENT/SENDNG LATCH 12

13 SO Prgramming (cntinued) Write Registers (cntinued) WRTE REGSTER 2 WRTE REGSTER 3 D7 D6 D5 D4 D3 D2 D1 DO V1 VOl V2 V3 V4 V5 V6 V7 NTERRUPT VECTOR D7 1 D6 D51 D4 1 D31 D2 1 Dl 1 DO 1 L L L ~~~~~~~~ACTER LOAD NHBT L ADDRESS SEARCH MODE (SDLC Rx CRC ENABLE L- ENTER HUNT MODE AUTO ENABLES Rx 5 BlrS/CHARACTER Rx 7 BTS/CHARACTER Rx 6 BTS/CHARACTER Rx 8 BTS/CHARACTER WRTE REGSTER 4 WRTE REGSTER 5 D7 D6 D5 D4 D3 D2 D1 DO PARTY ENABLE L- PARTY EVEN/ODD 0 SYNC MODES ENABLE 1 STOP BT/CHARACTER 11,12 STOP BTS/CHARACTER 2 STOP BTS/CHARACTER B BT SYNC CHARACTER 16 BT SYNC CHARACTER SDLC MODE ( SYNC FLAG EXTERNAL SYNC MODE DTR Tx CRG ENABLE L-----RTS L SDLC/CRC-16 L- Tx ENABLE L- SEND BREAK Tx 5 BTS (OR LESS/CHARACTER Tx 7 BTS/CHARACTER Tx 6 BTS/CHARACTER Tx 8 BTS/CHARACTER Xl CLOCK MODE X16 CLOCK MODE X32 CLOCK MODE X64 CLOCK MODE WRTE REGSTER 6 WRTE REGSTER 7 D7 D6 D5 D4 D3 D2 D1 DO SYNC BTO ) SYNC BT 1 SYNC BT 2 SYNC BT 3 SYNC BT 4 SYNC BT 5 SYNC BT 6 SYNC BT 7 D7 D6 D5 D4 D3 D2 D1 DO SYNC BT 8 ) SYNC BT 9 SYNC BT 10 SYNC BT 11 SYNC BT 12 SYNC BT 13 SYNC BT 14 SYNC BT 15 "ALSO SDLC ADDRESS FELD -FOR SOLe T MUST BE PROGRAMMED TO " " FOR FLAG RECOGNTON 13

14 SO Prgramming (cntinued) Read Registers The Z80-S10 cntains three (3) registers that can be read t btain the status feach channel. Status infrmatin includes errr cnditins, interrupt vectr, and standard cmmunicatin interface prtcl signals. T read the cntents f a selected Read Register the system sftware must first write ut t the SO the byte cntaining pinter infrmatin (DO-D2) in exactly the same manner as a Write Register peratin. Then by issuing a READ peratin the cntents f the addressed Read/Status Register can be read by the Z80-CPU. The real pwer in this type f cmmand structure is that the prgrammer has cmplete freedm after pinting t the selected register f either Reading r Writing t initialize r test that register. By designing sftware t initialize the Z80-S10 in a mdular, structured fashin, the prgrammer can use the pwerful Z80 BLOCK /O instructins t significantly simplify and speed his sftware develpment and debug. READ REGSTER 0 READ REGSTER 1 D7 D6 D5 D4 D3 D2 D1 DO READ REGSTER D5 0' 03 D2 D1 DO (Channel B Only) Rx CHARACTER AVALABLE NT PENDNG CHA ONLY) Tx BUFFER EMPTY DCD SYNC/HUNT CTS SENDNG CRC/SYNCS BREAK/ABORT V1 v2 VO) V3 NTERRUPT V4 VECTOR V5 V6 V7 D7 D6 D5 D4 D3 D2 D1 DO -FELD B TS N PREVOUS BYTE '--- PARTY ERROR Rx OVERRUN ERROR CRC/FRAMNG ERROR END OF FRAME (SDLC J ALL SENT -FELD BTS N SECOND PREVOUS BYTE "RESDUE DATA FOR 8 Rx BTS/CHAR PROGRAMMED SPECAL Rx CONDiTON NTERRUPTS 14

15 Register Descriptin Each channel cntains the fllwing cntrl registers, addressed as cmmands (nt data): WRTE REGSTER 0, a cmmand register: 0, 0, CRC Reset Cde CRC Reset Cde a OJ CMO CMO CMO PNT PNT PNT 2 OJ a 0, 2 0, D These are pinter bits which tell the SO int which register the fllwing byte is t be written. The first byte written int each channel after a reset (either by cmmand r with the external reset pin) will g t write register O. The byte fllwing a read r write t any register (nt register 0) will be t register O. a COMMAND 4 (Reset Receive nterrupt n First Receive Character.) f the "interrupt nly n first receive character" mde f peratin is prgrammed, it needs t be reactivated after each cmplete message is received, in preparatin fr the next message. COMMAND 5 (Reset Transmitter nterrupt Pending.) The transmitter will interrupt when it becmes empty if the "interrupt every character" mde is selected. n thse cases when there are n additinal characters t be sent, issuing this cmmand will prevent further transmitter interrupts (i.e. until after the next character has been laded int the transmitter.) These are cmmands: Cmmand CMO, CMO, CMO a a a a Null Cmmand (n affect) a a Send Abrt (SOLC Mde) 2 a a Reset External/Status nterrupts 3 a Channel Reset 4 a a Reset Receive nterrupt n First Character 5 a Reset Transmitter nterrupt Pending 6 a Errr Reset (latches) 7 Return frm nterrupt (Channel A nly) COMMAND 6 (Errr Reset, Latches.) Parity and verrun errrs are latched in Read Register until reset with this cmmand. This allws errrs ccuring in blck transfers t be examined nly at the end f the blck. COMMAND 0 (The null cmmand) has n affect. t's nrmal use is t d nthing while setting the pinters fr a fllwing byte. COMMAND 1 (Send Abrt) is used nly with the SDLC mde t generate a sequence f 8 t 13 nes. COMMAND 2 (Reset External/Status nterrupts). After an external r status interrupt (indicating a change n a mdem line r a break cnditin, fr example) the status bits f Read Register 0 are latched. This cmmand reenables them and and allws interrupts t ccur. The latching allws capture f shrt pulses n the inputs until such time as the CPU can read the change. COMMAND 7 (Return frm nterrupt.) This cmmand (which must be issued in Channel A) is interpreted by the SO in exactly the same way as it wuld interpret an RET Cmmand n the data bus, i.e. it wuld reset the nterrupt Under Service latch f the internal device (receiver, transmitter, etc.) under service and thus, by means f the daisy chain, allw lwer pririty devices t interrupt. The internal daisy chain may be used even in systems with n external daisy chain and n RET Cmmand by use f this cmmand. COMMAND 3 (Channel Reset.) This cmmand perfrms the same peratin as an external reset, but nly n a single channel. The Channel A Reset als resets the interrupt priritizatin lgic. All cntrl registers must be rewritten after this cmmand. After this cmmand is written, fur extra system (c» clck cycles shuld be allwed fr the SO reset time befre any additinal cmmands r cntrls are written int that channel f the SO. 15 CRC RESET CODE 0 (D 6 ) and CRC RESET CODE 1 (D 7 ) Tgether, these bits specify three reset mdes. CRC Reset Cde CRC Reset Cde a a a a a Null Cde (n affect) Reset Receive CRC Checker Reset Transmit CRC Generatr Reset CRe;SYNCS Sent Sending latch

16 Register Descriptin (cntinued) WRTE REGSTER 1 cntains the cntrl bits fr the vanus interrupt and WAT/ READY mdes. D, D. D, D. D J D J D, D Wait/ W/Ready Receive Receive Status Trans Ext Ready ReadyFN/ On interrupt nterrupt Affects nterrupt nterrupts Enable WaitFN R/T Mde Mde 0 Vectr Enable Enable W/READY n R/r (D s ) When the W/Ready line is enabled, this bit selects whether it will be active when the receiver is empty (bit=l) r when the transmit buffer is full (bit=o).,' EXT NT ENABLE (D) External nterrupt Enable, allws interru~ccur as a result f transitins n the DCD, CTS r SYNC lines r as a result f a Break Cnditin r the beginning f sending CRC r sync characters. TRANS NT ENABLE (0 1) Transmitter nterrupt Enable. f enabled, interrupts will ccur whenever the transmitter buffer becmes empty. READY FN/WAT FN (D 6 ) When used with the CPU as a Wait line, this bit shuld be prgrammed "0". When used with a DMA as a Ready line, it must be prgrammed"1". The Ready functin can ccur any time, regardless f whether the SO is addressed r nt. The Wait functin is active nly if the CPU attempts t read SO data that has nt yet been received, as wuld frequently ccur if blck transfer instructins are used with the SO, r tries t write data while the transmit buffer is still full. Als, as a Wait functin, the utput is pen drain and ccurs frm the negative edge f <P. As a Ready functin, it is actively driven high and ccurs frm the psitive edge f <!- STATUS AFFECTS VECTOR (0 2) (Channel B Only) f this mde is selected, the vectr returned frm an interrupt acknwledge cycle will be variable accrding t the fllwing: Ch B Ch A V, v, v, [l 0 i! *Special Receive Cnditins----i~~ 0 Ch B Transmit Buffer Empty 0 Ch B External/Status Change 0 Ch B Receive Character Available Ch B Special Receive Cnditin* 0 0 Ch A Transmit Buffer Empty 0 Ch A External/Status Change 0 Ch A Receive Character Available Ch A Special Receive Cnditin* PARTY ERROR Rx OVERRUN ERROR CRC/FRAMNG ERROR END OF FRAME (SDLC) f this bit is 0, the fixed vectr prgrammed in the vectr register is returned. WAT/READY ENABL (0 7 ) The Wait/Ready pin will remain high (Ready mde) r flating (Wait mde) until this bit is prgrammed t ne. WRTE REGSTER 2 Write Register 2 is the interrupt vectr register and it exists nly in Channel B. V4-V7 and V are always returned exactly as written. V t-v 3 are returned as written if the "Status Affects Vectr", Cntrl bit is "0". WRTE REGSTER 3 Write register receiver lgic. 3 cntains cntrl bits fr sme f the DJ D. D, D, D J D J D, D RCVR RCVR Enter RECVR Address Sync Char Bits/ Bits/ Aut Hunt CRC Search Lad Receiver Char 0 Char J Enables Mde Enabl Mde nhibit Enabl REC NT MODE 0 (0 3 ), REC NT MODE 1 (04 ) Receive nterrupt Mde and Receive nterrupt Mde tgether specify the varius character available cnditins: MODE D, REC NT MODE D, REC NT MODE 0 Receiver interrupts disabled 1 Receive interrupt n first character nly errr nterrupt n all Receive Characters Parity/ affects Vectr nterrupt n all Receive Characters Parity errr des nt affect Vectr. RECEVER ENABLE (D) A "" prgrammed here allws recever peratins t begin. SYNC CHAR LOAD NHmT (0 1) )1 Sync characters preceding a message will nt be laded int the receiver buffers if this ptin is selected. The CRC calculatin is nt stpped by the sync character being stripped. 16

17 Register Descriptin (cntinued) ADDRESS SEARCH MODE (02) f the SOLC mde is selected, this mde will cause messages with addresses nt matching the prgrammed address r the glbal ( ) address t be rejected, i.e., n interrupts ccur unless an address match ccurs if this mde is selected. PARTY (D) f this bit is set, an additinal bit psitin (in additin t thse specified in the bits/character cntrl) is added t transmitted data and is expected in receive data. RECVR CRC ENABLE (03) Receiver CRC Enable. f this bit is set, a calculatin f CRC begins (r restarts) at the start f the last character transferred frm the receive register t the buffer stack regardless f the number f characters in the stack. PARTY EVEN/ODD (0 1) f parity is specified, this bit determines whether it is sent r checked as even r dd parity. (1 =Even Parity) ENTER HU T MODE (0 4) f character synchrnizatin is lst fr any reasn, r if in SOLC mde, it is determined that the cntents fan incming message are nt needed, Hunt mde may be reentered by writing a "" t this bit. AUTO ENABLES (0 5) STOP BTS 0 (02), STOP BTS 1 (0 3) These bits determine the number f stp bits added t each asynchrnus character sent. The receiver always checks fr ne stp bit. The special (00) mde is used t signify that a synchrnus mde is t be selected. D 3 Dz Stp Bits Stp Bits 0 Sync Mdes Stp Bit Per Character ~ Stp Bits Per Character 2 Stp Bits Per Character f this mde is selected, the OCO and CTS inputs are receiver and transmitter enables, respectively. f the mde is nt selected, OCO and CTS are nly inputs t their crrespnding bits in Read Register O. SYNC MODES 0 (04), SYNC MODES (05) These select the varius ptins fr character synchrnizatin: RCVR BTS/CHAR 1 (0 6), RCVR BTS/CHAR 0 (0 7 ) These bits tgether determine the number f serial receive bits that will be assembled t frm a character. These bits may be changed during the time that a character is being assembled, if it is dne befre the number f bits currently prgrammed is reached. Sync Mde Sync Mde 0 8-bit prgrammed sync l6-bit prgrammed sync SDLC Mde ( sync pattern) External Sync Mde D6 Receiver Bits/Character D 7 Receiver Bits/character 0 Bits/Character CLOCK RATE 0 (0 6 ), CLOCK RATE 1 (0 7 ) Specifies the multiplier between clck and data rates. Fr synchrnus mdes X must be specified. Any rate may be specified fr the asynchrnus mdes. The same multiplier is used fr bth the receiver and transmitter. WRTE REGSTER 4 Write Register 4 cntains cntrl bits affecting bth the receiver and transmitter. 0, D 0, 0, 0, 0, 0, 0" Clck Clck Sync Sync Stp Stp Parity Rate Rate Mdes Mdes Bits Bits Evenj Parity Odd n all mdes, the system clck (<» must be at least 4.5 X the data rate. f the X clck rate is selected, bit synchrnizatin must be accmplished externally. Clck Rate Clck Rate 0 Data Rate X = Clck Rate Data Rate X 16 = Clck Rate Data Rate X32 = Clck Rate Data Rate X64 = Clck Rate 17

18 Register Descriptin (cntinued) WRTE REGSTER 5 Write Register 5 cntains mstly cntrl bits affecting the transmitter. 0, 0, D Transmit Transmit Bits Bits Send Transmit SOLC OTR Char 0 Char Break Enable CRC6 TRANSMT CRC ENABLE (D) RTS Transmit CRC Enable This bit determines whether CRC is t be calculated n any particular send character. f set at the time f lading the character frm the transmit buffer t the transmit shift register, CRC will be calculated n the character. CRC will nt be autmatically sent unless this bit is set when the transmitter is cmpletely empty. RTS (Dd TRANSMT BTS/CHAR 0 (D6), TRANSMT BTS/ CHAR 1 (Ds), These bits tgether cntrl the number f bits that will be sent frm each byte transferred t the transmit buffer. DS Transmit Bits/Character Transmit Bits/Character 0 Bits/Character 5 r less Bits t be sent are assumed t be right justified. Lw rder bits (D) are sent first. The "5 r less" mde allws transmissin f t 5 bits in a character. 0, 0 6 0, 0, 0, 0, 0, Ou Sends ne bit Sends tw bits Sends three bits Sends fur bits Sends five bits Request t Send is the cntrl bit fr the RTS pin. When the RTS bit is set, the RTS ges active (lw). When the bit is reset (t 0), the RTS pin will g inactive (high) nly after the transmitter is empty. DTR (D?) SDLC/CRC/16 (D 2 ) This bit selects the CRC cde used by bth the transmitter and the receiver. When reset, the SDLC plynmial X l6 + X 12 + X 5 + is used. (n SDLC mde, the registers are preset t "all 's" and a special check sequence is used.) When set, the CRC-16 plynmial X 6 + XiS + X is used. Data Terminal Ready is the cntrl bit fr the DTR pin. When set, DTR is active (lw). When reset (0) DTR is inactive (high). WRTE REGSTER 6 TRA SMT ENABLE (D 3 ) Data will nt be transmitted and the TxD pin will be held marking (high) until this bit is set. Data r Sync characters in the prcess f being transmitted will be cmpletely sent if the transmit enable bit is reset after transmissin has started. CRC characters will nt be cmpletely sent if the transmitter is disabled during the sending f a CRC character. SEND BREAK (D 4 ) When set, this bit directly frces the TxD pin spacing, regardless f any data being transmitted. When reset, the TxD pin is released. 18 This register cntains the first 8 bits f a BiSync sequence. t must be prgrammed with the check address (if used) in SDLC mde, and must cntain the sync character in the 8-bit sync mde. t cntains the transmit sync character in the external sync mde. WRTE REGSTER 7 This register cntains the secnd byte f a l6-bit synchrnizatin sequence, r the 8-bit sync character. Fr SDLC mde, it must be prgrammed t t is nt used in the external sync mde. 07 SYN5 SYN4 0, SYN3 SYN2 SYN 0, SYNO SYN9 Ou SYN8

19 Register Descriptin (cntinued) READ REGSTER 0 This is the register read if the register pinters are (000). 0, Break/ Abrt 0, Sending CRC/ Syncs CTS Sync Hunt C RECEVE CHARACTER AVALABLE (D) 0, Transmit Buffer Empty 0, D Receive nterrupt Character Pending Available This bit is set when at least ne character is available in the receive buffers. NTERRUPT PENDNG (D l ) (Channel A Only) Any interrupt cnditin present in the entire SO will cause this bit t be set, but it is present nly in Channel A and is always 0 in Channel B. TRANSMT BUFFER EMPTY (D 2 ) The Transmit Buffer Empty bit is set whenever the transmit buffer is empty, except when a CRC character is being sent in a synchrnus mde. BREAK/ABORT (D?) n asynchrnus mdes, this bit is set when a "break" is detected. After the inputs have been re-enabled (by the "Reset External/Status nterrupts" cmmand, Cmmand 2), the bit will be reset when the break stps. f "External/ Status" interrupts are enabled, these changes f state cause interrupts. n SDLC mde, this bit is set by the detectin f an abrt sequence (7 r mre 's). t is nt used in ther synchrnus mdes. READ REGSTER 1 This register is read when the register pinters are (001). The pinters autmatically reset t (000) after a read frm this register. 0, 0, 0, D End r CRC Receiver Frame Framing Overrun Parity Residue Residue Residue (SLC) Errr Errr Errr Cde 2 Cde Cde 0 All Sent DCD (D 3 ) Shws the state f the DCD pin inverted at the time f the last change fany f the five "external/status" bits. (DCD, CTS, SYNC/HUNT, BREAK/ABORT r SENDNG CRC/SYNCS.) T get the current state f the DCD pin, this bit must be read immediately fllwing a "Reset External/Status nterrupts" cmmand. (Cmmand 2.) ALL SENT (D) n asynchrnus mdes, this bit is set when all characters have cmpletely cleared the transmitter. Transitins f this bit d nt cause interrupts. t is always set in synchrnus mdes. n asynchrnus mdes, this bit is similar t the DCD and the CTS bits, except that it shws the state f the SYNC pin. n synchrnus mdes, this bit is reset when character synchrnizatin is achieved and is set by writing the "Enter Hunt Mde" bit. Unlike the external pin, the bit remains reset until set by the "Enter Hunt Mde" bit. Hwever, in the external sync mde, the bit gives the state f the external pin nt hunt status. RESDUE CODE 0 (D1)-RESDUE CODE 2 (D) These three bits indicate the length f the -field in the SDLC mde in thse cases where the -field is nt an integral multiple f the character length used. Only n the transfer n which the E D OF FRAME (SDLC) bit is set d these cdes have meaning. Fr a receiver setting f eight bits per character, the cdes signify the fllwing: This bit is similar t the DCD bit, except that it shws the state f the CTS pin inverted. SENDNG CRC/SYNCS (D 6 ) n synchrnus mdes, CRC is autmatically sent when the transmitter is empty fr the first time in a message. nterrupts are generated (if enabled) when this bit is set, but nt when reset. f this bit is set and the TRANSMT BUFFER EMPTY bit is nt set, then the CRC character is being sent. TRANSMT BUFFER EMPTY and SEND NG CRC/SYNCS bth set imply that SYNC characters are being sent. 19 -Field Bits -Field Bits n Previus n Secnd Residue Cde 2 Residue Cde Residue Cde 0 Byte Previus Byte Field bits are right-justified in all cases.

20 Register Descriptin (cntinued) f a receive character length different frm eight bits is used fr the -field, a table similar t the abve may be cnstructed fr each different character length. Fr n residue, i.e., the last character bundary cincides with the bundary f the -Field and CRC Field, the Residue Cde will always be: Residue Cde 2 Residue Cde Residue Cde 0 CRC/FRAMNG ERROR (06) f a framing errr ccurs (in asynchrnus mdes), this bit is set (and nt latched) nly fr the character n which it ccurred. Detectin f a framing errr adds an additinal i;2 bit time t the character time s that the framing errr will nt als be interpreted as a new start bit. n synchrnus mdes, this bit indicates the result f cmparing the CRC checker t the apprpriate check value. END OF FRAME (SOLC) (D 7 ) PARTY ERROR (04 ) When parity is enabled, this bit is set fr thse characters whse parity des nt match the sense prgrammed. The bit is latched s that nce an errr ccurs, the bit remains set until the Errr Reset cmmand, Cmmand 6, is given. RECEVER OVERRUN ERROR (0 5) This indicates that mre than fur characters have been received withut a read frm the CPU. Only the character that has been written ver is flagged with this errr, but when this character is read, the errr cnditin is latched until reset by the Errr Reset Cmmand, Cmmand 6. f "Status Affects Vectr" is enabled, the character that has been verrun will interrupt with the "Special Receive Cnditin" vectr. n SDLC mde, this bit indicates that a valid ending flag has been received and that the CRC errr and residue cdes are valid. READ REGSTER 2 This register cntains the interrupt vectr as written int Write Register 2 if the "Status Affects Vectr" cntrl bit is nt set. f that cntrl bit is set, it cntains the interrupt vectr as it wuld be returned were an interrupt frm the SO t be prcessed exactly at the time f the read. f n interrupts are pending, V3 = 0, V2 =, V = 1 and ther bits are as prgrammed. The register may be read nly thrugh Channel B. D, V, D, v, Variable if "Status Affects Vectr" is enabled D" V" 20

21 Register Descriptin (cntinued) Z80-SO COMMAND STRUCTURE Reg. Cntrl DATA BTS 07 D6 D5 D4 D3 D2 Dl DO CRC 1 CRC 0 CMD2 CMD 1 CMDO CRC 1 CRC 0 CMD2 CMD CMDO Break!Abrt Sendg CRC/SYNC CTS SYNC/HUNT DCD TxBuffer EMPTY NT Pending (CH A Onlyl RxChar Avail CRC 1 CRCO CMD 2 CMD 1 CMDO Wait/RDY EN WaitFN/RDYFN Wait/ROVn RfT RxlNT Mde 1 RxlNT Mde 0 Status Affects V (CH B Onlyl TxlNT EN EXT NT EN End FrameSDLC CRe Frame Errr RxOVRN Errr Parity Errr Res. Cde 2 Res.Cde 1 Res. Cde 0 All Sent CRC 1 CRC 0 CMD 2 CMD 1 CMDO CH B ONLY V7 V6 V5 V4 V3 V2 V VO V7 V6 V5 V4 V3 V2 V VO CRC 1 CRC 0 CMD 2 CMD CMDO RxBits/Char 0 RxBits/Char 1 Aut Enables Enter HuntMde RxCRC EN AddrssSearch Md SyncChar LD NH RxEN CRC 1 CRC 0 CMD2 CMD 1 CMDO Clck Rate 1 Clck Rate 0 Sync Mde 1 Sync Mde 0 Stp Bits 1 Stp Bits 0 Parity Even/Odd Parity CRC 1 CRC 0 CMD2 CMD 1 CMDO DTR TxBits/Char 0 TxBits/Char 1 Send BREAK TxEN SDLqCRC.16 RTS TxCRC EN CRC 1 CRC 0 CMD2 CMD 1 CMDO SYNC/SDLC 7 SYNC/SDLC 6 SYNC/SDLC 5 SYNC/SDLC 4 SYNC/SDLC 3 SYNC/SDLC 2 SYNC/SDLC 1 SYNC/SDLC CRC 1 CRC 0 CMD2 CMD CMDO SYNC/SDLC 15 SYNC/SDLC 14 SYNC/SDLC 13 SYNC/SDLC 12 SYNC/SDLC 11 SYNC/SDLC 10 SYNC/SDLC 9 SYNC/SDLC 8 21

22 PROGRAMMNG EXAMPLE A typical start-up rutine fllwing an internal r external reset, wuld be as fllws: B/ A C/O RD D 7 D 6 Ds D4 D) D2 D D COMMENTS Pinter set t Register 2B V 7 V 6 Vs V 4 V J V2 V V nterrupt Vectr laded Pinter set t Write Register 4B 0 X X 0 Even parity, stp bit, X 16 clck, asynchrnus mde selected Pinter set t Write Register 5B bits/transmit character, transmitter enabled Pinter set t Write Register 3B bits/receive character, DCD and CTS enable Receiver and Transmitter, Receiver enabled Pinter set t Register B nterrupt n every character, status affects Vectr external/ status interrupts enabled Channel B is nw setup t send and receive asynchrnus data. Setup fr Channel A fllws: Pinter set t Write Register 4A SDLC mde and X clck selected, n parity Prgramming Example B/A C/D RD D 7 D 6 Ds D4 D) D 2 D D COMME TS Pinter set t Write Register Receive CRC Checker 6A, Reset 0 AD 7 AD 6 ADs AD 4 AD) AD 2 AD AD SDLC message address entered Pinter set t Write Register 7A, Reset Transmit CRC generatr SDLC Flag entered Pinter set t Register A nterrupt every character, status affects vectr, external/ status interrupts enabled Pinter set t Write Register 5A, Reset External/ Status nterrupts SDLC CRC Cde selected, 8 bits/transmit character, CRC and transmitter enabled Pinter set t Write Register 3A bits/receive character, DCD and CTS enable receiver and transmitter, receiver is enabled, SO searches fr prgrammed address Channel A is nw prgrammed fr SOLC transfers. 0 0 D D D D D D D D Address byte t be sent by Ch. A Reset CRC/SY CS SENT/SE D G, pinter t register 0, s CRC can be autmatically sent at end f message 22

23 Abslute Maximum Ratings Temperature Under Bias Strage Temperature Vltage On Any Pin with Respect t Grund Pwer Dissipatin Specified perating range. -65 C t +150 C ~.3V t +7V 1.5W *Cmment Stresses abve thse listed under "Abslute Maximum Rating" may cause permanent damage t the device. This is a stress rating nly and functinal peratin f the device at these r any ther cnditin abve thse indicated in the peratinal sectins f this specificatin is nt implied. Expsure t abslute maximum rating cnditins fr extended perids may affect device reliability. D.C. Characteristics T A = DC t 70 C, Vee = 5V ±5% unless therwise specified Symbl Parameter Min. Typ. Max. Unit Test Cnditin ViLe Clck nput Lw Vltage -{).3.40 V VHe Clck nput High Vltage Vee-.2(11 Vee V VL nput Lw Vltage -{) V VH nput High Vltage 2.0 Vee V VOL Output Lw Vltage 0.4 V OL = 1.8 rna VO H Output High Vltage 2.4 V OH = -250/LA Vee Pwer Supply Current 100 rna te = 400 nsec Ll nput Leakage Current 10 /LA AiN = 0 t Vee lloh Tri-State Output Leakage Current in Flat 10 /LA VOUT = 2.4 t Vee LOL Tri-State Output Leakage Current in Flat -10 /LA VOUT = O.4V w Data Bus Leakage Current in nput Mde ±O /LA ~ VN ~ Vee An external clck pull-up resistr f (33011) will meet bth the AC and DC clck requirements. Capacitance TA = 25 C, f = 1 MHz Symbl Parameter Max. Unit Test Cnditin C<t> Clck Capacitance 40 pf Unmeasured Pins C N nput Capacitance 5 pf Returned t Grund COUT Output Capa,itan,e 10 pf Lad Circuit fr Output TEST PONT FROM ~~~~~T---"",--"",----iC TEST f---~. 250$lA 23

24 A.C. Timing Diagram Timing measurements are made at the fllwing vltages, unless therwise specified: HGH LOW CLOCK 4.2V.8V Only fr timing OUTPUT 2.0V.8V measurements NPUT 2.0V.8V FLOAT tn ±O.5V _----' \' '/ \'------'/ \' l ~ ' [gR~A, C/D_, ----'llr ,x _ ~t tfmo) -, ts-,les) ~ th",cs----.j l,lo)----.~ le leo j - """"t_::-tfro) r ''-_.l--.. \'----- _ '' tsw>(ml) tsw",ro)---k---j~ NT \,', \ \ / r / \ f \ ORO, CE WAT/READ'" \ / ~. -.,,,w'"'_{ -. -thw/r) -. tlow/r)...- }- \ ) 24

25 A.C. Timing Diagram (cntinued)... tw(ph)..... tw(pl)....., tc(txc).. ~tw(tcl)~... twtch).. \ TxO )< "'" ~ t(tx O)~... tc(rxc).. ~tw(rcl)-" ~tw(rch)~ tsl(sy)~ ~ tw(sy) ~ 25

26 A.C. Characteristics T A = O C t 70 C, Vcc = +5V ±5%, unless therwise nted Signal Symbl Parameter Min Max Unit Cmments <P tc(<p) Clck Perid nsec tw(<ph) Clck Pulse Width, Clck High nsec tw(<pl) Clck Pulse Width, Clck Lw nsec tr,tr Clck Rise and Fall Times nsec CE,B/A" th(cs) Cntrl Signal hld time frm Rising Edge f <P -0- nsec NOTE CjD,ORQ ts(cs) Cntrl Signal setup time frm Rising Edge f <P 160 tdr(d) Data Output Delay frm Rising Edge f <P during Read Cycle 480 nsec ts<p(d) Data Setup Time t Rising Edge f <P during Write Cycle r M 50 nsec Cycle th<p(d) Data Hld Time frm Rising Edge f <P during Write Cycle r -0- nsec M Cycle D-D, tdl(d) Data Output Delay frm Falling Edge f 10RQ during NTA Cycle 340 nsec tfm(d) Delay t Flating Bus frm Rising Edge f 10RQ during!nta Cycle 230 nsec tfr(d) Delay t Flating Bus frm Rising Edge f RD during Read Cycle 230 nsec tf(d) Delay t Flating Bus frm Falling Edge f le during NTA Cycle 230 nsec leo tdl(lo) leo Delay Time frm Falling Edge f le 150 nsec tdh(o) leo Delay Time frm Rising Edge f le 250 nsec td<p(lo) leo Delay Time frm Falling Edge f M (when interrupt ccurs 300 nsec just prir t M ) tsw<p(m ) M Setup Time t Rising Edge f <P during Read r Write Cycle 210 nsec Ml tsr<p(m ) M Setup Time t Rising Edge f <P during NTA r M Cycle 210 nsec th<p(m) M Hld Time frm Rising Edge f <P -0- nsec RD tsw<p(rd) RD Setup Time t Rising Edge f <P during Write r TA Cycle 240 nsec th<p(rd) RD Hld Time frm Rising Edge f <P during NTA Cycle -0- nsec tsr<p(rd) RD Setup Time t Rising Edge f <P during Read r M Cycle 240 nsec JW<P(RD) RD Hld Time frm Rising Edge f <P during Write Cycle -0- nsec thm<p(rd) RD Hld Time frm Rising Edge f <P during M Cycle -0- nsec NT tdr,(lt) NT Delay Time frm center f Receive Data Bit <PPerids tdt,(lt) NT Delay Time frm center f Transmit Data Bit 5 9 <PPerids td<p(t) NT Delay Time frm Rising Edge f <P 200 nsec WAT/READY tdc(w/r) WAT/READY Delay Time frm 10RQ r CE in WAT Mde 180 nsec tdh<p(w/r) WAlT/READY Delay Time frm Falling Edge f <P, WAT/READY 150 nsec HGH, WAT Mde tdrx(w/r) WAT/ READY Delay Time frm center f Receive Data Bit, <PPerids Ready Mde tdtx(w/r) WAT/READY Delay Time frm center f Transmit Data bit, 5 9 <P Perids Ready Mde tdl<p(w/r) WAT/READY Delay frm Rising Edge f <P, WAT/READY, 120 nsec Lw, Ready Mde CTSA,CTSB DCDA,DCDB, tw(ph) Minimum High Pulse Width fr latching states int register and 200 nsec SYNCA,SYNCB generating interrupt tw(pl) Minimum Lw Pulse Width fr latching state int register and 200 nsec generating interrupt SYNCA,SYNCB tdl(s Y) Sync Pulse Delay Time frm Center f Receive Data Bit, Output Mdes 4 7 <P Perids tsl(sy) Sync Pulse Setup Time t Rising Edge f RxC, External Sync Mde 100 nsec tw(sy) Sync Pulse Width t Start Character Assembly 3 <P Perids te(txc) Transmit Clck Perid nsec TxCA,TxCB tw(tch) Transmit Clck Pulse Width, Clck High nsec NOTE 2 tw(tcl) Transmit Clck Pulse Width, Clck Lw TxDA,TxDB td(txd) TxD Output Delay frm Falling Edge f TxC (xl Clck Mde) 400 nsec RxCA,RxCB tc(rxc) Receive Clck Perid nsec tw(rch) Receive Clck Pulse Width, Clck High nsec OTE 3 tw(rcl) Receive Clck Pulse Width, Clck Lw nsec NOTE : f WAT is t be used, CE, 10RQ, C/f5 and M must be valid fr as lng as WAT cnditin is t persist. NOTE 2: n all mdes, maximum data rate must be less than Zs f system clck (<P) rate. NOTE 3: The RESET signal must be active a minimum f ne cmplete <P cycle. 26

27 Package Cnfiguratin Package Outline 0, , NT le leo M V WiROYA SYNCA RXDA RXCA TXCA TXDA OTRA RTSA CTSA OCOA (CLOCK) , ORO CE B/A C/O AD GNO OV WiROYB SYNCB OPTONAL BONDNG " MAX. " (5.334 em).230 MAX. (,5842) ~ t O.D2!MN. ~ lo.0508j ) 11_ )- -Dimensins fr metric system are in parentheses ~ ~ ~ ' ( r (.254).710 (1.8034) TYP Ordering nfrmatin C - Ceramic P - Plastic S - Standard SV±S%, 0 t 70 C E - Extended SV±S%, _40 t 8SC M - Military SV±lO%, -SS t 12SC Example: Z80-SO/l CS (Ceramic-Standard Range) Z80-S0/0 PS (Plastic-Standard Range) ZLOG Z80 MCROCOMPUTER SYSTEM COMPONENT FAMLY Z80, Z80A-CPU Z80, Z80A-PO Z80, Z80A-CTC Z80, Z80A-DMA Z80, Z80A-SO Z6104 Z6116 CENTRAL PROCESSOR UNT PARALLEL /O COUNTER/TMER CRCUT DRECT MEMORY ACCESS SERAL /O 4K x 1 STATC RAM 16K x 1 DYNAMC RAM 27

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