COM-1827SOFT CPM Modulator VHDL source code overview / IP core

Transcription

1 COM-1827SOFT CPM Mdulatr VHDL surce cde verview / IP cre Overview The COM-1827SOFT CPM MOD is a Cntinuus Phase Mdulatr written in generic VHDL. The entire VHDL surce cde is deliverable. It is prtable t a variety f FPGA targets. Key features and perfrmance: CPM is a set f cnstant amplitude phase mdulatins well suited fr peratin thrugh pwer amplifiers near saturatin. Flexible prgrammable features: Symbl rate up t f clk/4, where f clk is the prcessing clck frequency. FSK, MSK, GFSK, GMSK, PCM/FM, SOQPSK-MIL and SOQPSK-TG Prvided with IP cre: VHDL surce cde Matlab.m file fr generating stimulus files fr cmparisn purpses. VHDL testbenches (back-t-back mdem r stimulus file input) PRBS11 test sequence generatr, AWGN nise generatr Cnfiguratin Run-time cnfiguratin parameters The user can set and mdify the fllwing cntrls at run-time thrugh the tp level cmpnent interface: Mdulatr Parameters SYMBOL_RATE_NDIV Cnfiguratin symbl rate expressed as (mdulatr prcessing clck)/2^ndiv Range 0 t 15 fr divisin ratis ranging frm 1 t MODULATION_INDEX mdulatin index h. unsigned fixed-pint frmat Typical values fr h are 0.5 (0x0800), 0.7 (0x0B33) GAIN CENTER_FREQ CENTER_FREQ BURST_LENGTH CONTROL utput amplitude scaling factr. 15-bit unsigned mdulated signal center frequency. Expressed as fc/mdulatr prcessing clck * 2^32 mdulated signal center frequency. Expressed as fc/mdulatr prcessing clck * 2^32 A synchrnizatin wrd is inserted peridically between frames (t reslve any phase ambiguity at the receiver). This just includes the data field, nt the 32-bit preamble. Cnstraint: BURST_LENGTH is a multiple f 8 bits. cmpsite limit: preamble+sync+burst_ LENGTH < 8191 bits 2:0 mdulatin rder M = 3 fr SOQPSK, 0 1

2 I/Os therwise bits 7:4 frequency shaping filter selectin 0 = FSK 1 = PCM/FM 2 = GMSK/GFSK BT=0.7 3 = GMSK/GFSK BT=0.5 4 = GMSK/GFSK BT=0.3 5 = SOQPSK-MIL 6 = SOQPSK-TG 8 = GMSK/GFSK BT=0.25 bits 9:8 test mde: 00 n test, 01 = PRBS11, 11 = unmdulated carrier bit 10: always '1' t enable sync wrd insertin bit 11: spectrum inversin. invert Q. n (1) r ff (0) General CLK: input The synchrnus clck. The user must prvide a glbal clck (use BUFG). The CLK timing perid must be cnstrained in the.xdc file assciated with the prject. SYNC_RESET: input Synchrnus reset. The reset MUST be exercised at least nce t initialize the internal variables. It must be exercised whenever a cntrl parameter is changed. Mdulatr CLK SYNC_RESET COM1827_TX CPM MODULATOR TX_DATA(7:0) TX_DATA_SAMPLE_CLK TX_SOF INPUT TX_CTS BITS SYMBOL_RATE_NDIV(3:0) MODULATION_INDEX(15:0) GAIN(15:0) CENTER_FREQUENCY(31:0) BURST_LENGTH(12:0) CONTROL(15:0) CONTROLS DATA_I_OUT(15:0) DATA_Q_OUT(15:0) TX_EN_OUT MODULATED BASEBAND WAVEFORM SATURATION SYMBOL_CLKx4_OUT MONITORING TX_DATA(7:0): Input data byte. The MSb is sent first. TX_DATA_SAMPLE_CLK: input. 1 CLK-wide pulse indicating that TX_DATA is valid. TX_SOF: ptinal input Start Of Frame. 1 CLKwide pulse. The SOF is aligned with TX_DATA_SAMPLE_CLK. TX_CTS: utput. Clear-T-Send flw cntrl. '1' indicates that the mdulatr is ready t accept anther input byte. Thanks t an input elastic buffer, the data surce is allwed t send a few mre bytes after TX_CTS ges lw Mdulatr input flw cntrl example DATA_I/Q_OUT(15:0): Mdulated baseband utput samples (I = in-phase, Q = quadrature). One utput sample every clck. Frmat: 2's cmplement (signed) 2

3 TX_EN_OUT: ges lw t turn ff an external pwer amplifier when the mdulatr is nt receiving any input data. 3

4 Design cnsideratins input bit stream NRZ-L/M/S Rate M=2,3 NRZ cnditining FEC encding (Cnvlutinal r Turb-cde) Symbl Mapping + Precding PCM/FM, FSK, GFSK, SOQPSK Frequency pulses generatin h Phase mdulatr mdulated I/Q Mdulatr blck diagram Frequency pulse generatin An FIR filter shapes the frequency pulses. The FIR cefficients are stred in a lkup table, sampled at 4 samples/symbl. See CPM_FILTERSx4.vhd. The table is large enugh t stre multiple frequency pulse shapes: rectangular pulse fr MSK, Gaussian pulse fr GMSK, raised csine fr PCM/FM, etc. The Matlab prgram /matlab/siggen_fsk1.m is used t generate the FIR cefficients. 4

5 Perfrmance Transmitted spectrum All spectrum captured fr 1 Mbits/s. MSK (blue) vs GMSK BT=0.3 (red) GMSK BT=0.25 PCM/FM h=0.7 5

6 SOQPSK-MIL SOQPSK-TG 6

7 Sftware Licensing This sftware is supplied under the fllwing key licensing terms: /bin BER perfrmance analysis at varius signal t nise ratis.bit cnfiguratin files (fr use with CmBlck COM-1800 FPGA develpment platfrm) 1. A nnexclusive, nntransferable license t use the VHDL surce cde internally, and 2. An unlimited, ryalty-free, nnexclusive transferable license t make and use prducts incrprating the licensed materials, slely in bit stream frmat, n a wrldwide basis. The cmplete VHDL/IP Sftware License Agreement can be dwnladed frm Prtability The VHDL surce cde is written in generic VHDL and thus can be prted FPGAs frm varius vendrs. See the limitatin belw. Limitatin 1. The mdulatr requires a prcessing and DAC clck in the frm (symbl rate * 2 N ), where N is an integer in the range The COM1827SOFT includes a Xilinx primitive t prgram the clck frequency, allwing any target symbl rate with a precisin f 1% r better. This Xilinx primitive is restricted t the Xilinx 7-series FPGAs (Artix, Kintex, Virtex, Zynq). Fr ther target platfrms, the user is respnsible fr generating the prcessing/dac clck. Cnfiguratin Management The current sftware revisin is 1c. Prject files: Xilinx ISE 14 prject file: cm-1827.xise Xilinx Vivad v prject file: prject_1.xpr VHDL develpment envirnment The VHDL sftware was develped using the fllwing develpment envirnment: (a) Xilinx ISE 14.7 fr synthesis, place and rute (b) Xilinx Vivad fr synthesis, place and rute and VHDL simulatin The entire prject fits easily within a Xilinx Artix7-100T. Therefre, the ISE prject can be prcessed using the free Xilinx WebPack tls. Device Utilizatin Summary The mdulatr size is fixed (nt parameterized). Device: Xilinx Artix7-100T Mdulatr Registers % LUTs % Blck RAM/FIFO 10 7% DSP % GCLKs 1 3.1% % f Xilinx Artix7-100T Directry /dc /src /sim /matlab Cntents Specificatins, user manual, implementatin dcuments.vhd surce cde,.pkg packages,.xdc cnstraint files (Xilinx) One cmpnent per file. VHDL test benches Matlab.m file fr generating stimulus files fr VHDL simulatin and fr end-t-end Clck and decding speed The entire design uses a single glbal clck CLK. Typical maximum clck frequencies fr varius FPGA families are listed belw: Device family Xilinx Artix 7-1 speed grade Mdulatr 160 MHz 7

8 Xilinx Kintex-7-2 speed grade Ready-t-use Hardware The COM-1827SOFT was develped n, and therefre ready t use n the fllwing cmmercial ff-the-shelf hardware platfrm: FPGA develpment platfrm COM-1800 FPGA (XC7A100T) + ARM + DDR3 SODIMM scket + GbE LAN develpment platfrm VHDL cmpnents verview Mdulatr tp level SIGNED_SIN_COS_TBL3.vhd stres sine and csine functins in ROM. It is used t cnvert phase t cmplex I/Q baseband utput samples. COM1827_TOP.vhd: is mstly a use example when the CPM mdem is implemented n a CmBlck COM-1800 FPGA develpment platfrm. Please nte that this tp cmpnent can't be simulated as it makes many references t ther cmpnents utside the scpe f the mdem prper (TCP stack, turb cdec, etc) Nte fr Xilinx Vivad: when creating the prject, the file pririty rder is unimprtant, except fr the three packages belw which must be placed with a higher pririty rder: Ancillary cmpnents COM1827_TX.vhd generates cmplex baseband cntinuus phase-mdulated samples frm bytesize input data. The BURST_TX.vhd cmpnent stres input data in an elastic input buffer, then packs input bits int symbls (1,2,3 bits/symbl) at the specified symbl rate. It als stps the transmitter when the input elastic buffer is empty. BRAM_DP2.vhd is a generic dual-prt memry, used as input and utput elastic buffers. Memry is inferred (n Xilinx primitive is used). ROM_FIL1.vhd implements an FIR filter t shape the frequency pulses. The FIR filter cefficients fr varius mdulatin schemes (Gaussian, raised csine, etc) are stred in the CPM_FILTERSx4.vhd ROM. LFSR11P.vhd is a pseud-randm sequence generatr used fr test purpses. It generates a PRBS11 test sequence cmmnly used fr bit errr rate testing at the receiving end f a transmissin channel. AWGN.vhd generates a precise Additive White Gaussian Nise. The nise bandwidth is 2*symbl rate. INFILE2SIM.vhd reads an input file. This cmpnent is used by the testbench t read a mdulated samples file generated by the siggen_fsk1.m Matlab prgram fr varius Eb/N and frequency ffset cases. SIM2OUTFILE.vhd writes three 12-bit data variables t a tab delimited file which can be subsequently read by Matlab (lad cmmand) fr pltting r analysis. 8

9 VHDL simulatin VHDL testbenches are lcated in the /sim directry. The tbcm1827_mdemnly.vhd cnnects the mdulatr and a demdulatr back t back. End-t-end BER tests can be perfrmed as the cm1827_tx.vhd transmitter includes a built-in pseud-randm sequence generatr and the cm1827_rx.vhd receiver includes a built-in Bit Errr Rate Tester. Matlab simulatin Matlab prgrams are lcated in the /matlab directry. The siggen_fsk1.m prgram generates a stimulus file input.txt fr use as input t a demdulatr VHDL simulatin (tbcm1827_demdnly.vhd). The stimulus file includes a cntinuus stream f pseud-randm (PRBS11) data bits, cnvlutinal cde encding, cntinuus phase mdulatin, additive white Gaussian nise, channel filtering, frequency translatin and quantizatin. Specificatins [1] IRIG-106 Telemetry Standard RCC Dcument , Chapter 2, fr SOQPSK TG [2] MIL-STD B fr SOQPSK-MIL CmBlck Ordering Infrmatin COM-1827SOFT CPM mdulatr, VHDL surce cde / IP cre Cntact Infrmatin MSS 845-N Quince Orchard Bulevard Gaithersburg, Maryland U.S.A. Telephne: (240) Facsimile: (240) inf@cmblck.cm 9