COM-1827SOFT GMSK DEMODULATOR VHDL source code overview / IP core

Transcription

1 COM-1827SOFT GMSK DEMODULATOR VHDL surce cde verview / IP cre Overview The COM-1827SOFT GMSK DEMOD is a cntinuus phase demdulatr written in generic VHDL. The entire VHDL surce cde is deliverable. It is prtable t a variety f FPGA targets. demdulatr and fr end-t-end BER perfrmance analysis at varius signal t nise ratis VHDL testbench (stimulus file input, r back-t-back mdem when used in cnjunctin with the CPM mdulatr IP cre) BER tester Key features and perfrmance: Supprts FSK, MSK, GFSK, GMSK mdulatins. These are cnstant amplitude mdulatin well suited fr peratin thrugh pwer amplifiers near saturatin. Flexible prgrammable features: Mdulatin index h. (0.5 fr MSK and GMSK). Multiple BT prducts fr Gaussian filters: 0.7, 0.5, 0.3, 0.25 Symbl rate up t f clk/4, where f clk is the prcessing clck frequency. MSK, GMSK: cherent demdulatin with excellent BER perfrmance using trellis decding (SOVA). FSK, GFSK: nn-cherent demdulatin with excellent BER perfrmance using multi-symbl detectin and trellis decding (SOVA). 4-bit sft-decisin demdulatr utput fr best FEC decder perfrmance. Perfrmance: BER < 10-5 at 9.2dB Eb/N ±50ppm symbl timing tracking Carrier frequency acquisitin f 10% f symbl rate Acquisitin threshld < 2dB Eb/N Prvided with IP cre: VHDL surce cde Cnfiguratin Run-time cnfiguratin parameters The user can set and mdify the fllwing cntrls at run-time thrugh the tp level cmpnent interface: Receiver Parameters AGC_RESPONSE RECEIVER_CENTER_ FREQ CIC_R Cnfiguratin Matlab.m file fr generating stimulus files fr VHDL simulatin f the MSS 845-N Quince Orchard Bulevard Gaithersburg, Maryland U.S.A. Telephne: (240) Facsimile: (240) MSS 2017 Issued 11/14/2017 Adjust the AGC respnse time. apprximately lg2(nsymbls). nminal (i.e. expected) center frequency. Expressed as fc/demdulatr prcessing clck * 2^32 -- This frequency is subtracted frm the input signal center frequency. Add -fclk/4 when used in cnjunctin with IF undersampling. CIC Decimatin rati. The utput sampling rate is thus fclk/r -- 1 t bypass. 0 is illegal, therwise, nminal range is 1 t Usage: be careful nt t decimate t much as the CIC decimatin filter is nt very sharp and thus can distrt the mdulated signal. -- Rule f thumb: the CIC

2 NOMINAL_SYMBOL_ RATE M_SEL filter utput sampling rate shuld be > 4 samples per symbl. fsymbl rate / fclk * 2^32 = nminal symbl rate mdulatin rder M selectin. Always 0 fr FSK/MSK/GFSK/GMSK Synchrnus reset. The reset MUST be exercised at least nce t initialize the internal variables. It must be exercised whenever a cntrl parameter is changed. FILT_SEL Filter selectin: -- 0: M=2 0 = FSK 2 = GMSK/GFSK BT=0.7 3 = GMSK/GFSK BT=0.5 4 = GMSK/GFSK BT=0.3 8 = GMSK/GFSK BT=0.25 MODULATION_INDEX mdulatin index h. unsigned fixed-pint frmat h must be 0.5 (0x0800) fr MSK and GMSK. FRAME_LENGTH DEMOD_CONTROL Optinal frame length, including paylad + 32-bit sync wrd bit 0: spectrum inversin enabled(1)/disabled(0) bit 1: AFC enabled(1)/disabled(0). Use nly fr FKS and GPSK. bit 2: freeze AGC bit 3: ptinal sync wrd detectin enabled (1)/disabled(0) bit 4: FFT : enabled (1) fr MSK and GMSK, disabled (0) therwise I/Os General CLK: input The synchrnus clck. The user must prvide a glbal clck (use BUFG). The CLK timing perid must be cnstrained in the.xdc file assciated with the prject. SYNC_RESET: input 2

3 Receiver COM1827_RX CPM RECEIVER CLK SYNC_RESET ADC_DATA_I_IN(13:0) ADC_DATA_Q_IN(13:0) ADC_SAMPLE_CLK_IN AGC_DAC(11:0) AGC DAC AGC_DAC_SAMPLE_CLK AGC_RESPONSE(4:0) RECEIVER_CENTER_FREQ(31:0) CIC_R(15:0) NOMINAL_SYMBOL_RATE(31:0) FILT_SEL(3:)) MODULATION_INDEX(15:0) FRAME_LENGTH(12:0) DEMOD_CONTROL(15:0) CONTROLS INPUT COMPLEX SAMPLES DATA_OUT(3:0) SAMPLE_CLK_OUT DEMOD DATA CARRIER_LOCK_OUT SIGNAL_PRESENT_OUT CARRIER_FREQUENCY_ERROR BER_SYNC BER_BYTE_ERROR BER_ERROR_COUNT(31:0) MONITORING ADC_DATA_I/Q_IN(13:0): input samples frm ne r tw external ADCs. (ne in the case f IF undersampling, tw fr near-zer frequency cmplex inputs). If the ADCs have fewer than 14- bit precisin, align the mst significant bit with ADC_DATA_IN(13). Frmat: 2's cmplement (signed). AGC_DAC(11:0): utput t an external DAC t cntrl an external AGC. Read when AGC_DAC_SAMPLE_CLK is '1' DATA_OUT(3:0): sft-decisin utput. The demdulated bit is bit 3. The three lwer bits indicate the level f cnfidence: "0000" fr a slid '0', "1111" fr a slid '1', "1000" fr a '1' barely abve the thresld. 3

4 Design cnsideratins COM-1827SOFT PCM/FM DEMODULATOR VHDL surce cde verview / IP cre baseband cmplex samples AGC Digital frequency translatin LPF + decimatin Symbl timing lp NCO Resampling 4/symbl Matched filters Carrier tracking lp SOVA 4-bit sft-decisin demdulated data NCO FFT* (*)initial frequency acquisitin Cherent demdulatr blck diagram Symbl timing lp NCO Matched filters Multisymbl detectr SOVA baseband cmplex samples AGC Digital frequency translatin LPF + decimatin Resampling 4/symbl AFC 4-bit sft-decisin demdulated data NCO Nn-cherent demdulatr blck diagram MSS 845-N Quince Orchard Bulevard Gaithersburg, Maryland U.S.A. Telephne: (240) Facsimile: (240) MSS 2017 Issued 11/14/2017

5 Perfrmance BER vs Eb/N The plt belw shws near-theretical perfrmance fr the GMSK (BT = 0.5) demdulatr withut errr crrectin B i t e r r r r a t e p e r f r m a n c e f r G M S K G M S K B T = B i t E r r r R a t e E b / N, d B 5

6 Sftware Licensing This sftware is supplied under the fllwing key licensing terms: 1. A nnexclusive, nntransferable license t use the VHDL surce cde internally, and 2. An unlimited, ryalty-free, nnexclusive transferable license t make and use prducts incrprating the licensed materials, slely in bit stream frmat, n a wrldwide basis. VHDL develpment envirnment The VHDL sftware was develped using the fllwing develpment envirnment: (a) Xilinx ISE 14.7 fr synthesis, place and rute (b) Xilinx Vivad fr synthesis, place and rute and VHDL simulatin The entire prject fits easily within a Xilinx Artix7-100T. Therefre, the ISE prject can be prcessed using the free Xilinx WebPack tls. The cmplete VHDL/IP Sftware License Agreement can be dwnladed frm Prtability The VHDL surce cde is written in generic VHDL and thus can be prted FPGAs frm varius vendrs. Cnfiguratin Management The current sftware revisin is 1c. Directry /dc /src /sim /matlab /bin Cntents Specificatins, user manual, implementatin dcuments.vhd surce cde,.pkg packages,.xdc cnstraint files (Xilinx) One cmpnent per file. VHDL test benches Matlab.m file fr generating stimulus files fr VHDL simulatin and fr end-t-end BER perfrmance analysis at varius signal t nise ratis.bit cnfiguratin files (fr use with CmBlck COM-1800 FPGA develpment platfrm) Prject files: Xilinx ISE 14 prject file: cm-1827.xise Xilinx Vivad v prject file: prject_1.xpr Device Utilizatin Summary The encder size is fixed (nt parameterized). Device: Xilinx Artix7-100T Receiver 4-bit sft-quantizatin Registers % LUTs % Blck RAM/FIFO 9 6% DSP % % f Xilinx Artix7-100T GCLKs 3 9% Clck and decding speed The entire design uses a single glbal clck CLK. Typical maximum clck frequencies fr varius FPGA families are listed belw: Device family Xilinx Artix 7-1 speed grade Xilinx Kintex-7-2 speed grade Demdulatr 160 MHz Ready-t-use Hardware The COM-1827SOFT was develped n, and therefre ready t use n the fllwing cmmercial ff-the-shelf hardware platfrm: FPGA develpment platfrm COM-1800 FPGA (XC7A100T) + ARM + DDR3 SODIMM scket + GbE LAN develpment platfrm 6

7 VHDL cmpnents verview Receiver tp level The receiver is cmprised f tw high-level cmpnents: RECEIVER1.vhd perfrms nn mdulatinspecific tasks such as AGC, DC bias remval, frequency translatin t baseband, anti-aliasing filtering and decimatin. Ancillary cmpnents LFSR11P.vhd is a pseud-randm sequence generatr used fr test purpses. It generates a PRBS11 test sequence cmmnly used fr bit errr rate testing at the receiving end f a transmissin channel. CPM_DEMOD.vhd perfrms the cntinuus phase demdulatin, including symbl timing tracking, AGC, matched filtering, multi-symbl detectin and trellis decding. BER2.vhd is a bit errr rate tester expecting t receive a PRBS11 test sequence. It synchrnizes with the received bit stream and cunt errrs ver a 80,000 bit windw. AWGN.vhd generates a precise Additive White Gaussian Nise. The nise bandwidth is 2*symbl rate. INFILE2SIM.vhd reads an input file. This cmpnent is used by the testbench t read a mdulated samples file generated by the siggen_fsk1.m Matlab prgram fr varius Eb/N and frequency ffset cases. SIM2OUTFILE.vhd writes three 12-bit data variables t a tab delimited file which can be subsequently read by Matlab (lad cmmand) fr pltting r analysis. 7

8 VHDL simulatin VHDL testbenches are lcated in the /sim directry. cm1827_rx.vhd receiver includes a built-in Bit Errr Rate Tester. The tbcm1827_demdnly.vhd testbench reads a tab-delimited stimulus files f mdulated I/Q baseband cmplex input samples. Matlab simulatin Matlab prgrams are lcated in the /matlab directry. The siggen_fsk1.m prgram generates a stimulus file input.txt fr use as input t either the demdulatr VHDL simulatin (tbcm1827_demdnly.vhd) r the demd_gmsk.m Matlab prgram. The stimulus file includes a cntinuus stream f pseud-randm (PRBS11) data bits, cnvlutinal cde encding, FSK,MSK,GFSK,GMSK mdulatins, additive white Gaussian nise, channel filtering, frequency translatin and quantizatin. Care must be taken t match the mdulatr cnfiguratin in siggen_fsk1.m and the demdulatr cnfiguratin in tbcm1827_demdnly.vhd. This setup allws end-t-end BER testing, as the demdulatr cm1827_rx.vhd includes a builtin bit errr rate tester. The demd_gmsk.m prgram applies key demdulatin techniques t the stimulus file input.txt and cmputes the BER. It des nt include AFC, AGC and symbl timing tracking lps. Reference dcuments [1] 8

9 Implementatin Overview Symbl tracking lp (nn-cherent) The lp is designed t acquire and track symbl timing errrs f +/-50ppm fr SNR f 0dB r abve. The algrithm first cmputes the phase difference between tw successive cmplex samples at 4 x the sampling rate. The phase difference is analguus t a frequency. One sample is used t de-rtate the fllwing sample. The resulting I value (FREQ2 in the cde) is prprtinal t the phase difference between these tw cmplex samples. The symbl tracking lp is a first rder Gardner lp. It finds the center f the FREQ2 symbls, and by way f cnsequence the zer crssing pint as well x Blue trace = phase f received cmplex baseband samples (in radians). h=0.7, niseless. Y axis scale: 1 = pi Purple trace = FREQ2. There are several delays between the RESAMPLING3.vhd and the SYMBOL_TIMING_LOOP5.vhd cmpnents wrth nting: 1. the FREQ2 signal lags the actual received baseband signal by 1.5/4 symbl. This is clearly visible in the abve plt. 2. the FREQ3 signal seen by the symbl tracking lp lags the actual received baseband signal by 1/2 symbl. 3. the FIRHALFBAND3.vhd filters used t reduce the nise pwer prir t symbl tracking, intrduce a grup delay f 10 samples = 2.5 symbls. Bth delays are cmpensated fr in the cde. Verificatin: when the symbl timing lp is tracking prperly, the SYMBOL3_CLK is aligned with the peak phase f the cmplex DATA3_X baseband signal. 9

10 Blue trace: phase/pi f cmplex DATA3_I/DATA3_Q signal after frequency dwn-cnversin and resampling at 4x symbl rate. Red trace: SYMBOL3_CLK Matched filter A partial crrelatin ver ne symbl perid is cmputed: the received cmplex baseband signal is crrelated with the cnjugate f the expected (ideal) signal ver ne symbl perid. The phase f the expected signal ver ne symbl perid is stred in a lkup table CPM_PHASEx4.vhd. The stred phase is sampled at fur samples/symbl, just like the received signal. Tw different phase wavefrms are stred, ne fr each received symbl hypthesis. Multi-Symbl detectin (nn-cherent) A multi-symbl detectr extends the crrelatin ver multiple symbls. Over a perid f 3 symbls, there are 16 pssible symbl hypthesis. The partial crrelatins are rtated and summed accrdingly. The highest magnitude indicates the mst likely symbls sequence. The 16 magnitude values are used as branch metrics fr the subsequent 8-state trellis decding. Matched filter phases are stred in CPM_PHASEx4.vhd Partial matched filter is cmputed in CPM_MF.vhd The multi-symbl detectin: CPM_MSD3.vhd FFT (cherent) In the case f MSK and GMSK, an FFT is used t acquire the initial frequency errr ver a windw f at least +/- 10% f the symbl rate. Since the mdulatin index h is 0.5, the phase difference between successive symbls is 90 degrees. A pwer f 4 is applied t the cmplex input samples t remve the 90deg mdulatin. 10

11 The pwer-f-4 samples are then prcessed by a 2048-pint FFT. If an FFT peak exceeds a threshld, signal presence is declared and the frequency errr is crrected. The threshld is a functin f the average nise level. AFC (nn-cherent) The demdulatr cmprises an autmatic frequency cntrl (AFC) lp t acquire and track the residual frequency ffset f the mdulated signal. See afc2.vhd cmpnent. The algrithm fllws the ne described in dcument [1]. 1. take tw cmplex baseband samples separated by ne symbl. These samples are taken after frequency crrectin. 2. One sample is used t de-rtate the ther sample. The resulting I value (FREQ1 in the cde) is prprtinal t the phase difference between these tw samples. Mst f the changes are due t the actual mdulatin. Hwever, any frequency errr will generate a bias. 3. Average FREQ1 ver 1024 symbls, as a way t remve mst f the mdulatin since bits are expected t be randmly distributed between 0s and 1s. 4. The average is accumulated t create the NCO cntrl value, after apprpriate scaling. The AFC rate f cnvergence depends n the scaling. Sme ripple is expected in the NCO cntrl value because f imbalances in the data stream (shw is a PRBS11 test sequence with slightly unequal numbers f 0s and 1s.) CmBlck Ordering Infrmatin COM-1827SOFT GMSK DEMOD, VHDL surce cde / IP cre Cntact Infrmatin MSS 845-N Quince Orchard Bulevard Gaithersburg, Maryland U.S.A. Telephne: (240) Facsimile: (240) inf@cmblck.cm 11