Encoder/Decoder ASIC Design

Transcription

1 A Nvel High-Speed Trellis-Cded Mdulatin Encder/Decder ASIC Design A Thesis Submitted t the Cllege f Graduate Studies and Research in Partial Fulfillment f the Requirements fr the Degree f Master f Science in the Department f Electrical Engineering University f Saskatchewan Saskatn By Xia Hu Cpyright Xia Hu, July 3. All rights reserved.

2 PERMISSION TO USE In presenting this thesis in partial fulfillment f the requirements fr a Degree f Master f Science frm the University f Saskatchewan, the authr agrees that the libraries f this University may make it freely available fr inspectin. The authr further agrees that permissin fr cpying f this thesis in any manner, in whle r in part fr schlarly purpses may be granted by the prfessr wh supervised this thesis wrk r, in his absence, by the Head f the Department r the Dean f the Cllege f Graduate Studies and Research at the University f Saskatchewan. Any cpying, publicatin, r use f this thesis, r parts theref, fr financial gain withut the authr s written permissin is strictly prhibited. Prper recgnitin shall be given t the authr and the University f Saskatchewan in any schlarly use which may be made f any material in this thesis. Requests fr permissin t cpy r t make any ther use f material in this thesis in whle r part shuld be addressed t: Head f the Department f Electrical Engineering, 57 Campus Drive, University f Saskatchewan, Saskatn, Saskatchewan, Canada S7N 5A9 i

3 ABSTRACT Trellis-cded Mdulatin (TCM) is used in bandlimited cmmunicatin systems. TCM efficiency imprves cding gain by cmbining mdulatin and frward errr crrectin cding in ne prcess. In TCM, the bandwidth expansin is nt required because it uses the same symbl rate and pwer spectrum; the differences are the intrductin f a redundancy bit and the use f a cnstellatin with duble pints. In this thesis, a nvel TCM encder/decder ASIC chip implementatin is presented. This ASIC cdec nt nly increases decding speed but als reduces hardware cmplexity. The algrithm and technique are presented fr a 6-state cnvlutinal cde which is used in standard 56-QAM wireless systems. In the decder, a Hamming distance is used as a cst functin t determine utput in the maximum likelihd Viterbi decder. Using the relatinship between the delay states and the path state in the Trellis tree f the cde, a pre-calculated Hamming distances are stred in a lk-up table. In additin, an utput lk-up-table is generated t determine the decder utput. This table is established by the tw relative delay states in the cde. The thesis prvides details f the algrithm and the structure f TCM cdec chip. Besides using parallel prcessing, the ASIC implementatin als uses pipelining t further increase decding speed. ii

4 The cdec was implemented in ASIC using standard.8µm CMOS technlgy; the ASIC cre ccupied a silicn area f.mm. All register transfer level cde f the cdec was simulated and synthesized. The chip layut was generated and the final chip was fabricated by Taiwan Semicnductr Manufacturing Cmpany thrugh the Canadian Micrelectrnics Crpratin. The functinal testing f the fabricated cdec was perfrmed partially successful; the timing testing has nt been fully accmplished because the chip was nt always stable. iii

5 ACKNOWLEDGEMENTS I am deeply grateful t my supervisr, Dr. Anh Dinh, fr his guidance, supprt, and patience during my graduate prgram. He has been an invaluable surce f knwledge and has certainly helped inspire many f the ideas expressed in this thesis. The ther special thanks g t the Canadian Micrelectrnics Crpratin fr their sftware and hardware supprt. This thesis culd nt have been accmplished withut their supprt. Als, I wuld like t thank the Department f Electrical Engineering and Cllege f Graduate Studies and Research, University f Saskatchewan, fr prviding a graduate schlarship during this research. Special appreciatin ges t my husband, Tie Peng, fr his understanding, endless supprt and help; and my sn, Yuwei Peng, fr his smile, listening, smart talk and being a gd by. iv

6 INDEX OF CONTENTS Permissin t use.. i Abstract.. ii Acknwledgements. iv Index f Cntents. v List f Tables viii List f Figures ix List f Abbreviatins xi Chapter INTRODUCTION. Classic Cding. Trellis-Cded Mdulatin 3.3 FPGA Design 6.4 ASIC Design 7.5 Research Objectives, Cntributin and Methdlgy 8.6 Outline f the Thesis 9 Chapter TRELLIS-CODED MODULATION BACKGROUND. Errr-Crrecting Cding. Trellis-Cded Mdulatin 5.. Fundamentals and Cncept f TCM 7.. TCM Encder..3 Set Partitining 3 v

7 ..4 Mapping and Trellis Diagram 5..5 TCM Decder 9..6 Viterbi Algrithm 3.3 Multi- Dimensinal Trellis-Cded Mdulatin Intrductin t Multi-Dimensinal TCM Fur-Dimensinal TCM Encder TCM 4D 56-QAM Cnstellatin Mapping 36 Chapter 3 TCM CODEC IMPLEMENTATION ALGORITHM Encder Implementatin A -Dimensinal Encder Implementatin A 4-Dimensinal Encder Implementatin 4 3. Decder Implementatin Structure f the HDLUT and OLUT A Nvel TCM Decder Architecture Implementatin A Decder fr -Dimensinal TCM Scheme A Decder fr 4-Dimensinal TCM Scheme 57 Chapter 4 TCM CODEC ASIC IMPLEMENTATION 6 4. ASIC Design Intrductin 6 4. Tp Mdule Architecture f the TCM Cdec ASIC Chip I/O Signal Descriptin Individual Blck Descriptin The Multiplexers The Clck Divider 73 vi

8 4...3 The Built-In Self Test Register Transfer Level Cde in VHDL Pipelining System Synthesis 79 Chapter 5 RESULTS 8 5. MATLAB System Simulatin Results 8 5. FPGA Prttype Implementatin Results ASIC Implementatin Results Register Transfer Level Cde Simulatin Register Transfer Level Cde Synthesis Layut Generatin The Fabricated TCM Cdec Testing Results 99 Chapter 6 CONCLUSION AND FUTURE WORKS 6. Research Summary. 6. Cnclusins Future wrk 5 REFERENCES 7 vii

9 LIST OF TABLES Table 3. 4D subsets allcatin Table 3. Crrespndence between Z Z k k and fur D subsets 45 Table 3.3 4D blck encder Table 3.4 A Hamming Distance table 49 Table 3.5 HDLUT using in the TCM decder 5 Table 3.6 An OLUT using in the TCM decder 5 Table 3.7 The simplified OLUT using in TCM decder 5 Table 5. FPGA implementatin results 85 Table 5. RTL cde simulatin results... 9 Table 5.3 Physical results f the chip frm RTL synthesis 93 Table 5.4 The synthesis results f FPGA and ASIC TCM decder 94 viii

10 LIST OF FIGURES Figure. Blck diagram f a digital-cded system Figure. An illustratin f a (6, 3) blck cde 4 Figure.3 An illustratin f a cnvlutinal cde 4 Figure.4 The cnstellatin and tw-state trellis used in the example TCM scheme Figure.5 Result f cding gain versus the number f states Figure.6 General scheme f a D TCM encder Figure.7 Set partitin f a 6-QAM cnstellatin 5 Figure.8 Structure f the TCM encder used in V.3 mdem 6 Figure.9 A 3-signal cnstellatin fr the V.3 Mdem TCM scheme 8 Figure. Trellis diagram f the V.3 mdem TCM encder 9 Figure. Viterbi algrithm illustratin based n tw-state trellis 33 Figure. General scheme f a 4D TCM Encder 35 Figure.3 Partitining f a 4D rectangular lattice 37 Figure 3. A 6-state -dimensinal TCM encder... 4 Figure 3. Cnvlutinal cding in TCM encder 4 Figure 3.3 A 56-signal cnstellatin fr the D 6-state TCM scheme. 4 Figure 3.4 A 6-state 4-dimensinal TCM encder Figure 3.5 Trellis diagram f the 6-states TCM encder 48 Figure 3.6 A -dimensinal 6-state TCM decder ix

11 Figure 3.7 Architecture f the STAU blck 56 Figure 3.8 Schematic diagram f the bit cnverter Figure 3.9 Schematic diagram f the 4D-blck decder 59 Figure 3. A 6-state 4-dimensinal TCM decder 6 Figure 3. The 4-dimensinal TCM cding system 6 Figure 4. A flw chart f the ASIC design prcess.. 63 Figure 4. Overall ASIC chip architecture f the TCM cdec. 68 Figure 4.3 I/O signal illustratin f the TCM cdec Figure 4.4 Clck divider signals illustratin Figure 4.5 The wavefrm f clck divider 74 Figure 4.6 The structure f LFSR Figure 4.7 The architecture f the BIST blck n the TCM cdec chip 76 Figure 5. Input sequence f the cnvlutinal encder 83 Figure 5. Cdewrd sequence f the cnvlutinal cding 83 Figure 5.3 Output sequence f the cnvlutinal decder Figure 5.4 Final layut f the TCM cdec ASIC.. 97 Figure 5.5 Phtgraph f the TCM cdec chip with bnding pads 98 Figure CPGA pin bnding and pin ut diagram 99 Figure 5.7 Functinal testing set-ups.. Figure 5.8 Functinal testing fr D scheme.. Figure 5.9 Functinal testing fr 4D scheme.. x

12 LIST OF ABBREVIATIONS D. Tw-dimensinal 4D. Fur-dimensinal ARC. Antenna Rule Check ASIC... Applicatin-Specific Integrated Circuit AWGN... Additive White Gaussian Nise BER... Bit-Errr-Rate BIST. Built-In-Self-Test CATV Cable Televisin CMC.. Canadian Micrelectrnics Crpratin CMOS Cmplementary Metal Oxide Silicn CSU Cmpare-Selectin Unit DAVIC.. Digital Audi Visual Cuncil db Decibel DBS. Direct Bradcast Satellite DFF... D-Flip-Flp DFII.. Design Framewrk II (Cadence design tls) DFT Design-Fr-Test DRC. Design Rules Check DSP.. Digital Signal Prcessing ECC. Errr-Crrecting Cding xi

13 FEC. Frward Errr Crrectin FPGA Field Prgrammable Gate Array Gbps Giga-bit per secnd GDSII Graphical Design Stream II GHz... Gigahertz HDL.. Hardware Descriptin Language HDLUT Hamming Distance Lk-Up Table HDTV High Definitin Televisin IC Integrated Circuit I/O. Input/Output IP. Intellectual Prperty LFSR... Linear Feedback Shift Register LSB.. Least Significant Bit LUT.. Lk-Up Table LVS. Layut-Versus-Schematic MATLAB... Matrix Labratry (simulatin tls) Mbps Mega-bit per secnd MHz. Megahertz MMDS... Multi-channel Multipint Distributin Services MSB Mst Significant Bit MSED Minimum Squared Euclidean Distance MUX. Multiplexer NC-Sim. Cadence simulatr xii

14 OLUT Output Lk-Up Table PDP Physical Design Planner PROM. Prgrammable Read Only Memry PRPG. Pseud Randm Pattern Generatr PSK.. Phase Shift Keying QAM. Quadrature Amplitude Mdulatin QPSK. Quaternary Phase Shift Keying RTL. Register Transfer Level SE. Silicn Ensemble (Cadence layut tls) SNR. Signal-t-Nise Rati SOC. System-On-Chip STAU. State-Transitin and Add Unit TSMC. Taiwan Semicnductr Manufacturing Cmpany TCM. Trellis-Cded Mdulatin TTL Transistr-Transistr Lgic VHDL. VHSIC Hardware Descriptin Language VHSIC. Very High Speed Integrated Circuits VLSI. Very Large Scale Integratin xiii

15 CHAPTER INTRODUCTION This chapter intrduces the histry f cding thery and why Trellis-Cded Mdulatin is chsen t be the research tpic and implemented int an Applicatin Specific Integrated Circuit (ASIC). This chapter als presents the main research methdlgy, research achievement and the thesis utline.. Classic Cding In 948, Claude E. Shannn established the mathematical fundatin fr infrmatin transmissin. Shannn demnstrated that the effect f transmitted pwer, bandwidth, and additive nise can be assciated with a channel and incrprated int the channel capacity. In the case f additive white Gaussian nise interference with pwer spectral density N, an ideal band-limited channel f bandwidth W has a capacity C bits/s given by P C = W lg ( + ) (.) WN where P is the average transmitted pwer. The significant meaning f the channel capacity is that if the infrmatin rate R frm the surce is less than C, (R<C), then it is theretically pssible t achieve reliable

16 (i.e., errr-free) transmissin thrugh the channel by apprpriate cding. On the ther hand, if R>C, reliable transmissin is nt pssible regardless f the amunt f signal prcessing perfrmed at the transmitter and receiver. The infrmatin thery shws that fr ptimal cmmunicatins, system design shuld have lng sequences f signals, with maximum separatin amng them at the transmitter. At the receiver, the perfrming decisin shuld be made ver such lng signal sequence rather than individual bit. If the prcess is perfrmed prperly then the message errr prbability, P e, will decrease expnentially with sequence length n. The cnditin is that the rate R is less than R, which in turn is less than the channel capacity as stated in the infrmatin thery. The message errr prbability can be expressed as: P e ( R R) n < (.) where R is a quantity that carries dimensins f bits per channel symbl []. In rder t increase the sequence length n, errr-crrecting cding (ECC) is intrduced. Errrcrrecting cding methd intrduces redundant bits int each symbl, which directly increase the cdewrd length n and decrease errr prbability. In cnventinal ECC cding, the cding prcess is independent frm the mdulatin prcess. Cding ccurs at the digital symbl s and s befre mdulatin and generally invlves adding redundant bits int an input sequence. The resultant redundancy requires extra transmissin bandwidth. At the receiver, the inversin prcess f cding is the decding, which ccurs after the signal demdulatin. Since a digital bit (r symbl) stream that cmes int the decder is either in errr r nt, crrespnding with detectin methd, decding divides int hard decding and sft decding. The hard decding peratin is based n hard decisins f the digital signal,

17 which is r. The sft decding is based n sft decisin f the analg received samples, which culd be any quantized value between the lwest and the highest vltage instead f nly and. The theretical lss due t hard versus sft decding leads t a reductin f db in perfrmance. Trellis-cded mdulatin is different frm cnventinal cding; it treats cding and mdulatin tgether. The cding prcess invlves handling the mapping a cdewrd int a mdulatin scheme.. Trellis-Cded Mdulatin In a pwer-limited envirnment, the desired system perfrmance shuld be achieved with the smallest pssible transmitted pwer. The use f errr-crrecting cdes can increase pwer efficiency by adding extra bits t the transmitted symbl sequence. This prcedure requires the mdulatr t perate at a higher data rate, which requires a wider bandwidth. In a bandwidth-limited envirnment, the use f higherrder mdulatin schemes can increase efficiency in frequency utilizatin. In this case, a large signal pwer wuld be required t maintain the same system bit-errr-rate (BER). In rder t achieve imprved reliability f a digital transmissin system withut increasing transmitted pwer r required bandwidth, bth cding and mdulatin are cnsidered in TCM technlgy; therefre, TCM is a scheme cmbining errr-crrecting cding with mdulatin. TCM is used fr data cmmunicatin with the purpse f gaining nise immunity ver uncded transmissin withut changing the data rate. The use f TCM als imprves system reliability withut increasing transmitting pwer and required 3

18 channel bandwidth. Quadrature Amplitude mdulatin (QAM) and Quaternary Phase Shift Keying (QPSK) are used in TCM t increase data transmissin rate. Since channel bandwidth is a functin f the signal-t-nise rati (SNR), larger signal pwer wuld be necessary t maintain the same signal separatin and the same errr prbability if mre signals are required t be transmitted withut enlarging channel bandwidth. It seems that the Trellis cde statement vilates the basic pwer, bandwidth and errr prbability trade-ff principle. Actually this is nt true; the reasn fr this will be explained belw and as well as in the next chapter. Trellis cding intrduces dependency between every successive transmitting data symbl. The ptimum -dimensinal mdulatin utilizes the dependency between in-phase and quadrature symbls and the 4-dimensinal mdulatin emplys the dependency between symbls f tw successive time intervals. Trellis cdes and multidimensinal mdulatin are designed t maximize the Euclidean distance between pssible sequences f transmitted symbls. Euclidean distance is a straight-line distance between tw pints in signal cnstellatin. In N dimensins, the Euclidean distance between tw pints p and q is: N i= ( p i q i ) (.3) where p i and q i are the crdinate f p and q in the dimensin i. The minimum Euclidean distance (i.e., the distance between the clsest pssible sequences) f transmitted symbls in signal space determines the system perfrmance as: P e ~ e d min / σ (.4) where P e is message errr prbability, d min is the minimum Euclidean distance between 4

19 signal sequences and σ is the nise pwer. Equatin (.4) indicates that if d min increases, P e will decrease. This is ne f the reasns why TCM technique des nt vilate the basic trade-ff principle between pwer, bandwidth, and errr prbability. Since Ungerbeck invented TCM in 976 and had his papers published in the 98 s [-4], numerus researches have been wrking n TCM applicatins in numerus areas: vice band mdems, satellite cmmunicatins, wireless cmmunicatins trials, digital subscriber lp, HDTV (high definitin televisin), bradcast channels, CATV (cmmunity antenna televisin) and DBS (direct bradcast satellite) in the 98 s and 99 s. Many innvatins in TCM technlgy have been intrduced, such as multidimensinal TCM ( ), rtatinally invariant TCM with M-PSK (988), TCM with built-in time diversity (988-99), TCM with Tmlinsn Precder (99-99), TCM with unequal errr prtectin (99), multilevel cding with TCM (99-993), and cncatenated cding with TCM (993-present). Even a number f researches fcused n the Viterbi Algrithm t decde cnvlutinal cde ([5-]) and n trellis cding with multi-dimensinal mdulatin ([-5]), but nly a few was develped in the implementatin a TCM encder/decder n a single chip. This research fcuses n the ASIC implementatin f TCM encder/decder with -dimensinal and 4-dimensinal mdulatin mapping, and prvides an intellectual prperty (IP) cre t incrprate TCM in system-n-chip (SOC). The designed chip was fabricated by Taiwan Semicnductr Manufacturing Cmpany (TSMC) thrugh a grant frm Canadian Micrelectrnics Crpratin (CMC). In rder t shw the advantages f using CMOSP8 technlgy t implement 5

20 the ASIC TCM encder/decder chip, the ASIC hardware implementatin results are cmpared with the Field Prgrammable Gate Array (FPGA) implementatin frm different aspects such as lgic gates, chip area and speed. The fllwings intrduce sme backgrund f the FPGA and ASIC..3 FPGA Design An FPGA is a prgrammable device. Prgrammable devices are a class f general purpse integrated circuits that can be cnfigured in the field fr a wide variety f applicatins. FPGAs were invented in the mid-98s as devices that resemble ASICs but culd be prgrammed after the chip was manufactured. A FPGA cnsists f a matrix f prgrammable lgic cells with a grid f intercnnecting lines and switches between them. I/O cells exist arund the perimeter prviding an interface between the intercnnect lines and the chip external pins. Prgramming an FPGA cnsists f specifying the lgic functin f each cell and the switches in the intercnnecting lines. FPGA devices allw rapid design prttyping. They prvide sme benefits f custm CMOS VLSI design, while aviding the initial cst, fabricatin time delay, and inherent risk f a cnventinal masked gate array. The devices are custmized by lading cnfiguratin data int the internal lgic gates and memry cells. The FPGA can either actively read its cnfiguratin data frm external serial r byte-parallel PROM (i.e., master mde), r the cnfiguratin data can be written int the FPGA (i.e., slave and peripheral mde). They ffer mre dense lgic and less tedius wiring wrk than discrete cmpnent designs and faster turnarund than sea-f-gates, standard cells, r full-custm design. 6

21 FPGA designs can be prgrammed using ne f the varius hardware descriptin languages (HDL), such as Very high speed integrated circuit HDL (VHDL) and Verilg HDL, r directly prgrammed with lgic circuit diagrams and graphical schematic cmpnent layut..4 ASIC Design ASIC design is a prcess f integrating a specific cmplicated applicatin int a chip. A typical ASIC design prcess is generalized int three steps: HDL design capture, HDL design synthesis and design implementatin. HDL design capture is cmpleted with pre-synthesis simulatins t verify that the register transfer level (RTL) abstractin fully prvides the desired functinality. HDL design synthesis is cmpleted with pst-synthesis simulatins t verify that the gate-level circuit prvides the desired functinality and meets apprpriate timing requirements. Design implementatin is cmpleted with the physical verificatin t implement the chip layut under the Design Rules Check (DRC) errr free and ready fr micrelectrnic circuit fabricatin. ASIC generally runs faster than FPGA because f its specific place and rute during the layut prcess. ASIC csts less than FPGA and DSP implementatins under mass prductin; therefre it is widely used in industries. ASICs are nt ecnmical cmpared t FPGAs if they are used nly fr research purpses because ASIC implementatins require extra time t develp and the chip can nt be re-cnfigured if the design requires further mdificatins; a new develpment prcess has t be started. An ASIC design can be implemented in different ways depending n the 7

22 hardware descriptin languages (Verilg r VHDL), synthesis and/r layut tls t be used in the implementatin prcess. Details n ASIC design implementatin will be discussed in Chapter 4..5 Research Objectives, Cntributin and Methdlgy The bjective f this research is t design a high speed TCM encder/decder and t implement the cdec int an ASIC. The results f ASIC implementatin are then cmpared with FPGA implementatin in terms f the perating frequency (i.e., system thrughput r bit rate) and hardware requirement (i.e., chip cst). This thesis wrk fcuses n the cnstructing f a 6-state TCM cdec scheme based n DAVIC specificatin [6], and then implementing it n a single ASIC. The research is accmplished by creating a nvel architecture f the TCM decder and implementing a 6-state TCM cdec chip int an ASIC including mapping the signal t bth -dimensinal and 4-dimensinal cnstellatins. In the TCM decder part, the main difference frm the traditinal technique is the use f lk-up tables (LUTs). These tables are used t simplify the cst functin calculatin in the Viterbi algrithm. The use f these LUTs nt nly reduces hardware cmplexity but als increases the decding speed. Anther difference frm the traditinal decding technique is the efficient use f the shift registers t perfrm the tracing back prcess in the Viterbi algrithm. This technique avids using a large amunt f memry required t stre errr metrics fr all f the paths. The ASIC cnsists f tw parts: a TCM encder and a TCM decder. The TCM encder starts frm sampling digital surce data, and ends at the mapping signal 8

23 generatin. The TCM decder begins with the sampling f the cdewrd, and finishes with the restring f the riginal digital surce data. The VLSI implementatin f the TCM decder includes three parts: the de-mapping prcess, the cnvlutinal decding and the differential decding. The main and cmplicated part is the cnvlutinal decding prcess in which the Viterbi algrithm is used. High-speed peratin and lw cmplexity f the cdec are achieved by creating f the tw LUTs, simplifying the Viterbi algrithm fr VLSI implementatin, and adpting the parallel algrithm and the pipelining technlgy. RTL cdes were written in VHDL. Simulatin was run n the Cadence NC-Sim simulatr t verify the functinality f the ASIC. The RTL cdes are then synthesized int a gate-level netlist using Synpsys synthesis tls. The gate-level netlist was turned int layut fr fabricatin using varius Cadence tls: Physical Design Planner (PDP r DP), Silicn Ensemble (SE), and Design Framewrk II (DFII). The final layut was streamed ut t GDSII frmat file t be ready fr fabricatin. The ASIC was fabricated by TSMC and tested..6 Outline f the Thesis The rest f this thesis prvides detail descriptins n the backgrund, cncept and implementatin f the TCM cdec. Chapter intrduces the backgrund and key pint f the TCM and illustrates the related algrithm and technlgy. Chapter 3 prvides details f the TCM cdec structures, illustrates methdlgy and implementatin prcess including the mapping fr D and 4D cnstellatins; creates the architecture fr hardware implementatin. Chapter 4 prvides further descriptin n the 9

24 hardware implementatin, details f this ASIC design prcess and the structure f this TCM cdec chip. Chapter 5 prvides the results f the design TCM cdec in three parts: () the MATLAB simulatin n the TCM encder/decder algrithm, () the VHDL RTL cdes cmpilatin and simulatin results n FPGA APEX device, and (3) the ASIC implementatin results including the chip layut. Chapter 6 prvides cnclusin and recmmendatin fr future wrk.

25 CHAPTER TRELLIS-CODED MODULATION BACKGROUND This chapter intrduces general errr-crrecting cding, fundamental and cncepts f TCM, general encder structure, mapping methd, algrithm used in the TCM decding, and the multi-dimensinal TCM cdec.. Errr-Crrecting Cding Figure. shws a typical cmmunicatin system incrprating with channel cding. In this system, digital data generated by a surce encder are cded thrugh a channel encder, and the cded infrmatin data is used t mdulate a carrier fr transmissin ver a cmmunicatin channel. The channel always intrduces attenuatin, distrtin, interference and nise, which affect the receiver s ability t receive crrect infrmatin. The demdulatr recvers pssible values f the transmitted symbls, and the channel decder recvers the infrmatin data befre sending t its destinatin.

26 Infrmatin Surce Surce Encder digital data surce Channel Encder encder nise Mdulatr Channel Infrmatin Destinatin digital data sink Surce Decder Channel Decder decder Demdulatr channel Figure. Blck diagram f a digital-cded system A widely used channel encding methd is errr-crrecting cding (ECC). In an ECC system, a digital infrmatin surce sends a data sequence t an encder; the encder inserts redundant (r parity) bits, thereby utputting a lnger sequence f the cde bits. The sequence f the cde bits is called a cdewrd. The cdewrd is then transmitted t a receiver, which has a suitable decder t recver the riginal data sequence. Errr-crrecting cding is related t the methd f delivering infrmatin frm a surce t a destinatin with minimum errr. The research n ECC began in 948 with the publicatin f a landmark paper by Claude E. Shannn [7]. Shannn s wrk shwed that any cmmunicatin channel culd be characterized by a capacity at which infrmatin culd be reliably transmitted. At any rate f infrmatin transmissin up t the channel capacity, it shuld be pssible t transfer infrmatin at any desired level f errr rates. Intrducing redundancy int transmissins can prvide errr cntrl. This means mre symbls are included in the message than strictly needed just t cnvey the infrmatin, with the result that nly certain patterns at the receiver crrespnd t valid transmissins. Once an adequate degree f errr cntrl has been intrduced, the errr

27 rates can be made as lw as required by extending the length f the cde, thus averaging the effects f nise ver a lnger perid f time [8-9]. The research fr errr-crrecting cdes was primarily mtivated by the prblems arising in cmmunicatins systems, in particular, systems having limitatin in their transmitted pwers. Errr-crrecting cdes are an excellent means f reducing transmissin pwer requirements because reliable cmmunicatins can be achieved with the aid f cdes even when the infrmatin is weakly received at its destinatin. There are tw different types f cdes used in errr-crrecting cding: the blck cdes and the cnvlutinal cdes. The primary pint f bth cdes is t add redundant bits t achieve errr crrectin bjectives. These redundant bits are added int each symbl f infrmatin sequence frmulating the cdewrd. They will be used in the decder at the receiver t crrectly restre the riginal infrmatin sequence under specific decding algrithms. These redundant bits are als called parity-check bits; the bits prvide the cde with the capability f cmbating channel nise. The encder fr the blck cdes divides infrmatin sequences int infrmatin blcks f k-bit, represented by d = (d, d,, d k- ) infrmatin sequence. The encder transfrms each k-bit infrmatin blck d independently int a cdewrd, c = (c, c,, c n- ). This transfrmatin prvides a cding rate R= k/n (R < ). The cde is called a (n, k) blck cde. Decding algrithm f the blck cde is based n the methd f cnstructing the cdewrd in the encder. Figure. shws hw a cdewrd is generated thrugh a (6,3) blck encder. Each 6-bit utput cdewrd is cmprised f the riginal 3-bits message sequence and a 3-bits parity sequence. 3

28 Message sequence Cdewrd (6,3) Blck Encder Parity bits Message bits Figure. An illustratin f a (6,3) blck cde The encder fr cnvlutinal cdes generates cdewrd fr transmissin utilizing a sequential finite-state machine driven by the infrmatin sequence, r an arbitrarily lng sequence. The cnvlutinal encding prcess installs the prperties f memry and redundancy int the cdewrd stream, as fr blck cdes. Figure.3 shws a generic descriptin f a cnvlutinal encder. x() D D D y() y() x() D D D Mapping y() x(k-) D D D y(n-) m stage delay Figure.3 An illustratin f a cnvlutinal cde The k-bit infrmatin sequence as the input f the encder is cded t the n-bit cdewrd thrugh the m stage delay (represented by delay cell D). The cding rate is still R= k/n (R < ). The cde is called (n, k, m) cnvlutinal cde. Each f k parallel input lines can have different number f stage delay cells, which is smaller than r equal t m (m ). 4

29 The mst cmmn methd used in decding the cnvlutinal cdes is the prbabilistic methd. The prbabilistic decding methd includes sequential decding (Fan algrithm r stack algrithm) and maximum-likelihd decding (Viterbi algrithm). The sequential decding uses a systematic prcedure t search fr a gd estimatin f the message sequence; hwever, such prcedure requires a large memry and typically suffers frm buffer verflw prblems. Andrew Viterbi develped the Viterbi algrithm in 967 []. Since then, it has becme the standard algrithm t decde the cnvlutinal cdes. At each time interval, the Viterbi decding algrithm cmpares the actual received cdewrd with the cdewrd that might have been generated fr each pssible memry-state transitin. The algrithm chses the mst likely sequence within a specific time frame based n the metrics f similarity. The maximum-likelihd decding requires less memry than the sequential decding because unlikely sequences are dismissed early, leaving a relatively small number f candidate sequences that need t be stred. The additin f parity bits in the transmitted sequence eventually increases the transmissin bandwidth requirement. In 976, Ungerbeck invented Trellis-Cded Mdulatin technique t slve this prblem.. Trellis-Cded Mdulatin In cmmunicatin systems, errr-crrecting cding (ECC) reduces pwer utilizatin (i.e., the rati f the received energy per bit t the nise spectral density) by adding redundancy t the transmitted signal. The perfrmance imprvement f the ECC can be achieved by expanding the bandwidth f the transmitted signal t the cde rate in 5

30 the pwer-limited regin, which requires a high-rder mdulatin scheme. Fr bandwidth-efficient multilevel amplitude and phase mdulatin such as PSK r QAM, withut expanding the channel bandwidth required by ECC, increasing the number f signal phase r amplitude ver the crrespnding mdulatin cnstellatin perfrms the same data thrughput as uncded mdulatin. Hwever this increment requires an additinal signal pwer t maintain the same level f system bit-errr-rate [-3]. In cmmunicatins, Trellis-cded mdulatin is applied t slve the cnflict f utility efficiency between transmissin pwer and channel bandwidth. The TCM cding prcess utilizes signal mapping cmbining errr-crrecting cding with mdulatin. The mapping by the set partitining technique prvides a cmbinatin f digital signals used in the mdulatin. This technique increases the minimum Euclidean distance between the pairs f cded signals; hence the lss frm the expansin f the signal set is easily vercme and a significant cding gain is achieved with ECC. This is the reasn why TCM technique des nt vilate the basic trade-ff principle between pwer, bandwidth, and errr prbability. Therefre, in a bandwidth-limited cmmunicatin system, withut bandwidth enlargement, the redundancy bits are intrduced int the signal t achieve gd perfrmance f cding gain thrugh the TCM cdes. This gain can be as high as 5dB. The widely used ECC cde in the TCM encder is the cnvlutinal cde. As mentined in Sectin., the Viterbi decding algrithm is the standard methd t decde cnvlutinal cdes, and cmmnly used in cmmunicatin systems. In this TCM cdec implementatin, the TCM decder design chses the Viterbi algrithm as its decding algrithm. 6

31 The fllwing subsectins describe details f the TCM, such as fundamentals and cncepts, standard encder structures, mapping by set partitining methd and the Viterbi algrithm... Fundamentals and Cncept f TCM Assume there is a mdel fr the transmissin f data with discrete-time, cntinuus-amplitude ver the additive white Gaussian nise (AWGN) channel [4]. In this cmmunicatin mdel, messages t be delivered t the user are represented by pints, r vectrs, in an N-dimensinal Euclidean space R N, called a signal space. When a vectr x = x, x,..., x ] is transmitted, the received signal can be represented by the [ i vectr Z as: Z = x + v (.) where ν is a nise vectr [ v, v,..., vi ] whse cmpnents v, v,..., vi are independent Gaussian randm variables with zer mean and the same variance N /. N is nise pwer spectral density. The vectr x is chsen frm a set, the signal cnstellatin Ω, which cnsists the number f M signal vectrs. The average square length is referred t as the average signal energy and represented by: E = x (.) M x Ω If a sequence {x i } f K signals, i =,,, K- is transmitted, the receiver bserves received sequence y,, y k and then decides that X,, X k was transmitted if the squared Euclidean distance K-). d is minimized fr x = X (i =,,, i i 7

32 K d = y i x i (.3) i= That means if the sequence X, X,, X k is clser t the received sequence than t any ther allwable signal vectr sequence, then the resulting sequence errr prbability, as well as the symbl errr prbability, is upper bunded by M d min P( e) erfc( ) (.4) N in which the cmplementary errr functin erfc(x) is defined as erfc( x) = e x π t dt. The infrmatin rate and the nrmalized squared minimum distance are useful in cmparing different cnstellatins. Let R represents the infrmatin rate, and δ represents nrmalized squared minimum distance, these tw can be defined as: lg M R = N (.5) and d min δ = lg M (.6) E R is the rati between the number f infrmatin bits carried by a single signal in the cnstellatin and the number f dimensins N, M is the number f signal vectrs in cnstellatin Ω, and E is the average signal energy. If M, N, and E are given, the prblem f designing a gd cmmunicatin system is chsing a set f vectr signals such that the minimum distance between any tw signals is maximize. The infrmatin rate is als referred t as the bandwidth efficiency f that signal set, and the nrmalized squared minimum distance is its energy efficiency. Equatin (.4) can be rewritten in the frm 8

33 P( e) M δ erfc E N b (.7) where E E b = lg M represents the average energy per bit. In TCM system, signals are dependent. T avid a reductin f the transmissin rate, the cnstellatin shuld be expanded. The minimum free Euclidean distance d free between tw pssible sequences in a large cnstellatin is btained t be greater than the minimum Euclidean distance d min between tw signals in the riginal cnstellatin. This will be analyzed in Sectin..3. Hence using maximum-likelihd sequence detectin will yield a distance gain d free / d min. On the ther hand, expanding cnstellatin induces an increase in the average energy expenditure frm E t E (i.e., energy lss E/E ), where E and E are the average energy spent t transmit with uncded and cded transmissin, respectively. The asympttic cding gain γ f a TCM scheme is d free / E γ = (.8) d / E min The fllwing example shws the advantage f using TCM [4]. Assume the transmissin f quaternary surce symbls (i.e., bits per symbl) with uncded transmissin a channel alphabet with M =4 wuld be adequate, and PSK is used. Then d min = E In here, M=M =8 are used; M is the number f signal vectrs in the new TCM cnstellatin. Figure.4 shws the TCM scheme based n tw quaternary cnstellatins, {,, 4, 6} and {, 3, 5, 7}. This figure als shws a tw-state Trellis cnstructin. 9

34 E d 7 S S S S S Figure.4 The cnstellatin and tw-state trellis used in the example TCM scheme Frm Figure.4, the cding gain f PSK-based TCM can be calculated as: E = d 4sin ( π / 8) There are distances between signals assciated with the parallel transitins, and the distances assciated with a pair f paths in the trellis thse riginate frm a cmmn nde (i.e., state, S r S in Figure.4) and merge int a single nde at a later time. The free distance f this TCM scheme is calculated by chsing the smallest distances frm them. Then, d free E = [ d E (,) + d (,)] = + 4sin π = in which d(i, j) dentes the Euclidean distance between signals i and j, where i, j (, 7). The cding gain f this TCM scheme becmes: γ = d / E.586 free = =.93. db d / E min By increasing the number f states (i.e., memry bits) in TCM, the cding gain can be increased. Fr example, if the fur-state r eight-state trellis cding is used in this TCM scheme instead f tw-state, the cding gain will be 3.dB and 3.6dB,

35 respectively [5]. Figure.5 shws the cding gain tendency with different numbers f the trellis states. At each pint n the graph, the secnd number shws the cding gain can be achieved when the number f states (the first number) is used. 7 Cding gain (db) , 3.6 4, 3.,. 6, 4.8 3, 5. 64, 5.4 8, Number f states Figure.5 Result f cding gain versus the number f states Increasing the number f states in TCM is a simple way t imprve its perfrmance. Hwever, nce the number f states grws high enugh, the cding gain increases at much slwer rate as illustrated in Figure.5. In additin, the errr cefficient (i.e., the multiplicity f minimum-euclidean-distance errr events) f the cde starts t dminate the cde perfrmance []. In rder t slve this cnflict, a multi-dimensinal cnstellatins mdel is intrduced t the TCM system, which will be described in Sectin.3... TCM Encder Figure.6 shws a general -dimensinal TCM encder scheme n ne time interval. The input symbl cnsists f n bits data. While tw bits (I and I ) are cded thrugh bth differential and cnvlutinal encder, the ther n- bits remain uncded.

36 I n I 3 y n y 3 Uncded bits select signal frm subcnstellatin I I I Differential Encder I I Cnvlutinal Encder rate=/3 y y y Cded bits select subcnstellatin Q Figure.6 General scheme f a D TCM encder The differential encder prvides prtectin against the 8 phase ambiguity intrduced by the cmmunicatin channel. The cnvlutinal encder intrduces frward errr crrectin infrmatin fr the transmitted data. This cnvlutinal encder is als called a Trellis encder. This is a methd f achieving cding gain by increasing the density f the cnstellatin while keeping the minimum distance between each cnstellatin pints the same. It ensures that the transmitted sequence f pints cnfrms t a valid trellis sequence, which is essential fr prper decding in the receiver. The signal mapping is used t cnvert the cnvlutinal cded bits t an efficiency cmbinatin f Quadrature Amplitude Mdulatin (QAM) mde. QAM is a methd t mdulate the digital data in an analg signal in which each cmbinatin f phase and amplitude represents ne f the n n-bit patterns. As shwn in Figure.6, withut any errr crrectin infrmatin, each symbl has n bits, which requires a n -pint cnstellatin. After the /3 cnvlutinal encder, each symbl has n+ bits, which requires a n+ -pint cnstellatin. In general, fr the same average pwer, a mdulatin scheme using a n+ -pint cnstellatin has higher BER if cmpared with the n -pint cnstellatin scheme. The reasn fr this is that the

37 minimum Euclidean distance between any tw pints n a n+ -pint cnstellatin is smaller, which decreases the nise margin. Hwever, cnvlutinal encding intrduces cnstraints in transfrming an n-bit input symbl t a (n+)-bit utput symbl. Specifically, it des nt allw tw cnsecutive utput symbls t be in the eight neighbrhd psitins f each ther. This results in an increment f the minimum Euclidean distance between tw cnsecutive utput symbls, which is achieved thrugh mapping by the set partitining methd. This prcess prvides an verall perfrmance gain f 4dB. Set partitining is an imprtant prcess after cnvlutinal encde, which will be illustrated in Sectin..3. As differential encding is used in this TCM scheme; using this cding, errrs caused by the phase reversal in the channel are nt allwed t prpagate. The receiver will recnstruct the infrmatin sequence prperly except fr the errrs at the pints where phase reversal ccurs...3 Set Partitining In TCM, the mdulatin is an integral part f the encding prcess. It is designed in cnjunctin with the cde t increase the minimum Euclidean distance between the pairs f the cded signals. The lss frm the expansin f the signal set is easily vercme and a significant cding gain is achieved with relatively simple cdes. The key t this integrated mdulatin and cding apprach is t devise an effective methd fr mapping the cded bits int apprpriate signal pints s that the minimum Euclidean distance is maximized. In 98, Ungerbeck develped such methd, based n the principle f mapping by set partitining [-4]. 3

38 Based n the set partitining, the M-ary cnstellatin is successively partitined int, 4, 8,, ) (lg M subsets, with size M/, M/4, M/8,, with prgressively larger minimum distances. The set partitining methd fllws three Ungerbeck rules: U: T parallel transitins are assigned members f the same partitin; U: T adjacent transitins are assigned members f the next larger partitin; U3: T make all the signals are used equally ften. A set partitining methd is illustrated in the Figure.7. The figure shws a partitining f the 6-pints QAM cnstellatin. In Figure.7, the d min between pints in the subsets is increased by at least a factr f with each partitining. In the first partitining, the 6-pints cnstellatin is subdivided int tw 8-pint subsets. The square f the minimum Euclidean distance d min increases t d frm d. In the secnd partitining, each f the tw 8-pint subsets is subdivided int tw subsets f 4-pint, and the square f the minimum Euclidean distance d min is increased t 4d. This prcess cntinues n the subsets until each subset has nly tw pints, and the square f minimum Euclidean distance d min is nw increased t 8d. In QAM cnstellatin, each level f partitining increases the minimum Euclidean distance by. The level t which the signal is partitined depends n the characteristics f the cde. 4

39 5 First partitining Secnd partitining d d d d Figure.7 Set partitin f a 6-QAM cnstellatin In general, the TCM encding prcess is perfrmed as illustrated in Figure.6. A blck f the n infrmatin bits is separated int tw grups, ne will be cded and the ther remains uncded. The grup f cded bits will be used t select ne f the pssible subsets in the partitined signal set, while the uncded bits are used t select the pints in each subset. Sectin..4 will further explain the mapping based n the set partitining methd. Sectin.3.3 will illustrate the mapping fr the multi-dimensinal cnstellatin set partitining...4 Mapping and Trellis Diagram An 8-state, rate /3 cnvlutinal encder is used as an example t analyze the trellis diagram and mapping methd. Figure.8 illustrates a cnvlutinal encder used in the V.3 mdem n ne time interval [6-7]. Input f this TCM encder is a 4-bit symbl, and the utput is a 5-bit symbl. The utput includes a 3-bit cdewrd and a -

40 bit uncded wrd. This encder wrks at the full baud rate. The baud rate is a measure f the speed f a serial cmmunicatin using a mdem r null-mdem, rughly equivalents t bits per secnd. I 4 I 3 Y 4 Y 3 Uncded bits select signal frm sub-cnstellatin I + + I Y I I X + T I + X X Y Cded bits select subcnstellatin T + + T + + T S S Y Q Differential Encder S T Cnvlutinal Encder T DFF X AND + XOR Figure.8 Structure f the TCM encder used in V.3 mdem The encder perates as fllws, the redundant bit Y is functinally btained frm I, I which are differential cded bits btained frm I, I, and three memry bits, S, S, S which intercnnected by D-flip-flps (DFF), and a cmbinatin f AND and XOR lgic gates. The lgic functins are expressed by the fllwing ratinal equatins: I I I + D Y = I = (.3) + D I Y = I = (.4) + D Y = S (.5) S = S D (.6) 6

41 S S S D + I D + I D + SI D = (.7) + S D SD + I D = (.8) + I D The symbl D represents a delay thrugh a DFF which functins as a memry. There are three memry units S, S, S used in this cnvlutinal encder. The size f the encder memry is referred t as a cnstrained length (k) f the cde. The cnstraint length f the V.3 mdem encder shwn in Figure.8 is 3. As shwn in Figure.8, this cnvlutinal encder is eventually a finite-state machine. The number f states in the encder is k fr a given cnstraint length k. In this encder, the number f states is 3 =8, and represented by the three bits S, S, and S. The states S, S, S are als called delay states. The delay states at the last time interval and the utput f the encder at the current time interval Y, Y, Y cntrl the cnversin between each delay state. The utput Y Y Y is als called the path state f the cnvlutinal encder. The cnstraint cnditin f the cnvlutinal encder is that given a particular set f delay states (S, S and S ) in which nt all path states (Y, Y, and Y ) are pssible in that time interval. Fr example, based n the equatins (.5), (.6), (.7), (.8), if S n S n S n =, the states that can be reached (S (n+) S (n+) S (n+) ) are,, and. is fr Y Y =, since Y = S n, hence Y Y Y =, s that the subset f signals dented a in Figure.9 is assciated. is fr Y Y =, Y Y Y =, crrespnding with the subset f signals dented c. is fr Y Y =, Y Y Y =, crrespnding with the subset f signals dented d. is fr Y Y =, Y Y Y =, crrespnding with the subset f signals dented b. In this discussin, n and n+ represent tw cntinual time intervals. Figure.9 shws each subset frmed by 7

42 signals labeled a, b, h. Imaginary h g c b c e f e f a g d a d a h g h b c b c b e f e f d a d h g Real a b c d e f g h Y Y Y Figure.9 A 3-signal cnstellatin fr the V.3 Mdem TCM scheme The uncded bits Y 3 Y 4 in Figure.8 decide every single pint f each subset shwn in Figure.9. Each set f fur pints is symmetrically arranged and equally spaced n the cnstellatin as far apart as pssible. Eight different S n S n S n delay states crrespnding with Y Y Y path states is summarized in the trellis diagram shwn in Figure. Each current delay state in Figure. has fur pssible new delay state destinatins. In each new delay state, there are fur pssible inputs cming frm the last delay states, which are cntrlled by the path states. Each path state is als a part f the utput f the encder. This path state crrespnds t the delay states that traverse frm the left t the right side f the trellis diagram. This trellis diagram clearly shws the input bits (Y, Y ) and utput bits (Y, Y, Y ) relatinship f the system assciated with memry bits (S, S, S ). The decder algrithm is created based n the relatinship shwn in this trellis diagram. 8

43 Current Delay State (SSS) b d e h c c d c b a a g e a a f d b b d c f f h g Path States (YYY) Next Delay State (SSS) g e h f g e h Figure. Trellis diagram f the V.3 mdem TCM encder..5 TCM Decder The TCM encder is illustrated using a trellis whse branches are assciated with transitins between encder states and cdewrd transmitted ver the channel. The primary task f the TCM decder is t estimate the path that the cdewrd sequence traverses thrugh the trellis. In this manner, TCM decder is a reverse prcess f TCM encder. In additin t the cnvlutinal decding, the de-mapping algrithm is a reverse functin f the mapping lgic functin and the differential decder perfrms the reverse functin f the differential encder. Details f the TCM decder will be described in Chapter 3. The kernel f the TCM decder is the cnvlutinal decder, which cmpletes the path estimatin. The decder algrithm used in this thesis is based n the Viterbi algrithm. 9

44 ..6 Viterbi Algrithm Andrew Viterbi prpsed an algrithm in 967 t decde cnvlutinal cde and this became the Viterbi Algrithm []. This algrithm is an applicatin f dynamic prgramming that finds shrtest paths (maximum likelihd sequences) widely used in slving minimizatin prblems. A critical feature f this algrithm is the cmplexity f the decding prcess grws linearly with the number f symbls being transmitted, rather than expnentially with the number f the transmitted symbls. The Viterbi algrithm finds the sequence at a minimum Hamming distance (r Euclidean distance) frm the received signal with the minimized equivalent accumulated squared errr. The Trellis diagram in Figure. shws a relatinship between the delay states and the path states in each timing interval. The crrespnding relatins between delay states and path states cnstruct the basic database used in the Viterbi algrithm cst functin calculatin. Nrmally, the calculatin f cst functins uses tw different types f distance: the Hamming distance and the Euclidean distance. In this thesis, the Hamming distance is chsen t be the cst functin because the use f this distance is suitable in LUT methd t simplify hardware implementatin. The Viterbi algrithm finds the path with the minimum path metric cst by sequentially mving thrugh the trellis fr each time interval. In a time interval T, frm kt t (k+)t, the receiver bserves the sample received in that interval and cmputes the metric assciated with all the branches. This metric stres the cst value f all branches as shwn in the trellis diagram Figure.. Fr example, if the memry bits (m bits) is used in the cnvlutinal encder, the N = m is the number f the states in 3

45 the cnvlutinal encder. If each delay states have fur branches assciated with the new delay states, the ttal 4N branch csts will be calculated; but nly N path metrics are retained (i.e., stred in memry). The cst f each branch is defined as the Hamming distance (r Euclidean distance) between the received symbl and the pssible true symbl. The minimum branch cst will be the survivr branch fr the destinatin states. The cst f the path is a sum f the survivr branch cst at the current time interval and the accumulating path cst f the last time interval. Only ne path with minimum accumulate cst is kept as a tracing path. Since it is experimentally determined that the ptimal length f a cnvlutinal decder is fur r five times the cnstraint length f the cnvlutinal encder [6], after 4m r 5m time interval fr (n, k, m) cnvlutinal cde, the path with minimum accumulate cst f the N paths will be the survivr path. Using the survivr path, the decder will trace back t recreate the riginal signal data. Decding begins with cmparing received channel symbl pairs then building the accumulated errr metric fr each states branch and path. Based n these metrics, Viterbi decder will recver the riginal symbl (i.e., the input f the cnvlutinal encder). The Viterbi decding prcess is accmplished as fllws:. Selecting the Delay State having the smallest accumulated errr metric and saving the number f that delay state.. Iteratively perfrming the fllwing trace back steps until the beginning f the trellis is reached: Wrking backward thrugh the state histry table, fr the selected state; 3

46 Selecting a frmer state which is listed in the state histry table as being the predecessr t that state; Saving the state number f each selected state. 3. Wrking frward thrugh the list f selected states saved in the previus steps. Lk up what input bits crrespnd t the transitin frm each predecessr state t its successr state. That is, thse bits that must have been encded by the cnvlutinal encder. Figure. shws a simple example illustrating the Viterbi algrithm. The branch metrics, the survivr paths at each nde, and the partial path metric f each surviving path are illustrated in this figure. The tw-state (S, S) trellis with the branch metrics f the transitins is marked and the Viterbi algrithm is illustrated. The Viterbi algrithm finds iteratively the path with the minimum path metric f.5. In Figure., pattern () shws the branch metric values frm S t S, r frm S t S at every time interval k= t k=4. Pattern () assumes starting state is S at time interval k=, the frward states will be S and S. The cst fr S-S branch is., fr S-S is.8. Because.<.8, the survival branch is S-S, and the accumulate cst is. at k=. Pattern (3) shws starting state is S at k= and the frward states will be S and S. The cst fr S-S branch is.3, fr S-S is.. At k=, accumulate cst fr S is.3 (i.e.,. plus.3), fr S is. (i.e.,. plus.). Because.<.3, the survival branch is S-S. Same prcess wrks n patterns (4) and (5). Finally, at k=4, the minimum accumulate cst is.5 fr branch S-S. After tracing back, the survival path is S-S-S-S-S; this path is shwn in the bld line in Figure.. 3

47 k = k = k = k = 3 k = 4 S () S.9.6 Original trellis S.. S..3 min{.3,.9} ().8 (3). Branch metrics.8 Path metrics S min{.,.7} S.3. min{.5,.} (4).5 S S. min{.4,.6}.5. min{.5,.6} (5). S.4 the bld line is the survivr path Figure. Viterbi algrithm illustratin based n tw-state trellis.3 Multi-Dimensinal Trellis-Cded Mdulatin The perfrmance f TCM can be imprved by increasing the number f shift register (i.e., memry bits) used in the cnvlutinal cde. This is equivalent t the increment f the number f states in the trellis cding. This has been described in 33

48 Sectin... As mentined earlier, the cding gain saturates at the high number f states, the multi-dimensinal TCM cncept is intrduced in 98 s t vercme this deficiency [-5]..3. Intrductin t Multi-Dimensinal TCM In a -Dimensinal TCM encder, if the perfrmance f the trellis cde needs t be increased, mre states may be used. This implies that the number f cnvlutinal cding memry bits (i.e., cnstrained length) als increases. Hwever the returns f this manner diminishes as the cding gain increases at much slwer rate as shwn in Figure.5. An inherent cst f the cded schemes is that the size f the D cnstellatin is dubled ver uncded schemes. This is due t the fact that a redundant bit is added every signaling interval. Withut the cst, the cding gain f thse cded schemes wuld be 3 db t 6dB thrugh 4-states t 8-states. Using a multi-dimensinal cnstellatin with a trellis cde f rate n/n+ can reduce that cst because fewer redundant bits are added cmpared t the D cnstellatin. In the 4D TCM encder structure, the redundant bits generated thrugh cnvlutinal encder are added alternatively in each signaling interval. Cmpared t D cnstellatin, that cst is reduced t.5db in the 4D cnstellatin. In the fllwing sectins, the 4D cnstellatin TCM encder will be described and the difference between D and 4D cnstellatins can be viewed. Because the differential encder and cnvlutinal encder are still being used in the cding 34

49 prcess, the decder algrithm is the same in bth cases. The main differences between D and 4D are the mapping methd and the clck rate in the cnvlutinal cding..3. Fur-Dimensinal TCM Encder Figure. shws a general 4D TCM encder scheme. The differential encder prvides prtectin against 8 phase ambiguity in the channel as described earlier. The cnvlutinal encder prvides Frward Errr Crrectin infrmatin fr the transmitted data. I k ( n+) Z k ( n+) I I ( n+ ) I 3 ( n+ ) ( n+ ) I kn I 3n I n I n Differential Encder Cnvlutinal Encder rate=/3 I 3 n I n I n Y n 4D Blck Encder Bit Cnverter Z Z Z Z 3 ( n+ ) ( n+ ) Z 3n Z n Z kn ( n+ ) ( n+ ) Z n Z n Uncded digits select signal frm cnstellatin, and Cded digits select cnstellatin I Q Mapping Figure. General scheme f a 4D TCM encder The 4D blck encder generates tw pairs f selectin bits, which are used t select the inner grup r uter grup f the tw-selected D subset f the 4D cnstellatin pints. The bit cnverter generates anther tw pairs f the selectin bits, 35

50 which is used t select pair subsets in the 4D cnstellatin. Chapter 3 will prvide detail f these selectin pairs. As shwn in the Figure., the trellis cding part has a same structure as in Figure.6. The difference is n the input signals sequence, which is cntinual input int differential encder in Figure.6, but is alternatively input int differential encder in Figure.. The input signals are k-bit symbl sequence, and n and n+ represent tw cntinual time intervals. In this thesis, k is selected t be 7 based n the DAVIC specificatin f the TCM used in the MMDS system [6]. After TCM cding, the signal is mapped int a 56-QAM cnstellatin. Hw the 4D 56-QAM cnstellatin mapping is perfrmed is described in the next sectin..3.3 TCM 4D 56-QAM Cnstellatin Mapping TCM schemes using 4D cnstellatins have been reprted in the literatures [- 5]. The 4D cnstellatin is partitined int thirty-tw 4D subsets with eight times larger than the intra-subset minimum squared Euclidean distance (MSED) shwn in Figure.3. One partitining methd f the 4D cnstellatin is based n the partitining f each cnstituent D cnstellatin int fur D subsets; cncatenating a pair f D subsets frms each 4D subset []. The ther partitining methd accmplishes algebraically withut referring t the partitining f the cnstituent D cnstellatins [5]. Using the partitin f 4D rectangular lattice as an example, Figure.3 illustrates a gemetrical apprach t partitining multi-dimensinal lattices int 36

51 sublattices with enlarged intrasublattice MSED. The partitining f lattice is based n the partitining f its cnstituent D rectangular lattices. Furthermre, the partitining f a multi-dimensinal lattice is dne in an iterative manner. That is, the partitining f a N-dimensinal lattice is based n the partitining f the cnstituent N-dimensinal lattices, which is in turn based n the partitining f the cnstituent N/-dimensinal lattice []. As shwn in Figure.3, each time the intrasublattice MSED is dubled; the number f 4D sublattices increases furfld. 4D Rectangular Intra-Lattice MSED d d 4d 8d Figure.3 Partitining f a 4D rectangular lattice T transmit k infrmatin bits per signaling interval using a rate f n/n+ trellis cde with a 4D rectangular cnstellatin, the 4D cnstellatin f k+ pints is cnstructed as fllws. The first step is t btain a cnstituent 4D rectangular cnstellatin. The D cnstellatin is divided int tw grups, the inner grup and the uter grup []. The number f pints in the inner grup is k, the same as that in the crrespnding uncded scheme. The number f pints in the uter grup is / f that f the inner grup. The inner and uter grups must satisfy the fllwing tw requirements: ) Each subset has the same number f pints (inner and uter). ) Each grup is invariant under 9, 8, and 7 rtatins. 37

52 The first requirement is necessary t cnvert the 4D cnstellatin mapping int a pair f D cnstellatin mappings. The secnd requirement preserves the symmetries f the lattice in the cnstellatin. As shwn in Figure., n the 4D cnstellatin mapping, a bit cnverter cnverts the fur bits Y n, I n, I n, I 3n int tw pairs f selectin bits, Z n, Z n, Z n+, Z n+, which are used t select the pair f D subsets crrespnding t the 4D type. The 4D blck encder takes three f the remaining eleven uncded infrmatin bits, I n+, I n+, and I 3n+, and generates tw pairs f selectin bits, Z n, Z 3n, Z n+, Z 3n+, which are used t select the inner grup r uter grup f each selected D subset. The detail f this crrespnding relatinship will be illustrated in Chapter 3. 38

53 CHAPTER 3 TCM CODEC IMPLEMENTATION ALGORITHM This chapter fcuses n the implementatin algrithm and architecture f the TCM encder and decder. Illustratins f the encder and the decder will separate int tw parts based n the mapping prcess (i.e., mapping fr -dimensinal and 4- dimensinal). 3. Encder Implementatin The algrithm and hardware implementatins in this thesis fcus n the 6-state cdec recmmended in DAVIC. specificatins [6]. The cded bits are ready fr the 56-pint cnstellatin QAM mdulatin. There are tw implementatins n mapping: ne is mapping fr the -dimensinal (D) cnstellatin, and the ther is mapping fr the 4-dimensinal (4D) cnstellatin. The fllwing sectins illustrate details f bth prcesses. 3.. A -Dimensinal Encder Implementatin A 6-state D TCM scheme is cnstructed with reference t bth DAVIC [6] and V.3 TCM scheme [6]. The input signal symbl sequences are cntinually cming int the D TCM encder at every time interval (i.e., D TCM encder wrks at the full 39

54 baud rate). A cmbinatin f lgic gates and D-Flip-Flps (DFF) as memry devices is used t implement the differential encder and t generate the cnvlutinal encder states. Figure 3. shws a schematic diagram f the D TCM encder. I 7 I 6 I 5 I 4 Y 7 Y 6 Y 5 Y 4 uncded bits select signal frm each subcnstellatin I I I 3 Y 3 I x I + I I Y Y cded bits select subcnstellatin Q T T T + T + T + T S 3 S S S Y Differential Encder T DFF X Cnvlutinal Encder AND + XOR Mapping Figure 3. A 6-state -dimensinal TCM encder The differential encder functins as the fllwing Blean expressin: I n) = I ( n) I ( n ) (3.) ( [ I ( n) I ( n ) ] I ( n ) I ( ) I 3 ( n) = 3 3 n (3.) where n and n- represent the tw cntinual time interval. After differential encding, a rate f /3 cnvlutinal encder generates an extra redundant parity bit Y using tw bits I and I. The parity bit Y carries nly frward errr-crrectin infrmatin. Figure 3. shws the relatinship between I, I andy. Outputs f the memry elements S, S, S and S 3 are called delay states and values f the 3 bits Y, I and I are called path states. 4

55 Frm Differential Encder I I S S S S 3 4-bit Memry Y Redundant Bit Figure 3. Cnvlutinal cding in TCM encder The lgic functin f all symbl bits and memry bits fr the TCM scheme shwn in Figure 3. are btained frm the fllwing equatins: Y =, i = m {,4,5,6,7} (3.3) i I i Y 3 = I 3 (3.4) Y = I (3.5) Y = S (3.6) S = S I S ) D (3.7) ( S = S I ) D (3.8) ( S = S I ) D (3.9) ( 3 S 3 = S D (3.) where D represents the time delay f memry element (i.e., a DFF). In Figure 3., fur cded bits (Y, Y, Y, Y 3 ) cmbined with the ther uncded bits (Y 4, Y 5, Y 6, and Y 7 ) are mapped int a 56-pint cnstellatin. The inphase signal (I) and quadrature signal (Q) are mdulated and transmitted ver cmmunicatin channels. The 56-pint cnstellatin has 6 subsets (i.e., 4 frm 4 cded bits). Each subset uniquely identifies a set f 6 pints (i.e., 4 frm 4 uncded bits) ut f 56 cnstellatin pints. This TCM scheme signal space mapping is defined in such a way that each set f 6 pints is symmetrically arranged and equally spaced n the cnstellatin as shwn in Figure 3.3. Furthermre, each set f 6 pints is as far apart as pssible. 4

56 4 The figure illustrates sixteen subsets f a 56-pint cnstellatin frmed by signals labeled a, b, c, d, e, f, g, h, i, j, k, l, m, n and, p. The fur cded bits (Y, Y, Y and Y 3 ) select specific subset ut f subsets a, b, c, d, e, f, g, h, i, j, k, l, m, n and, p. The uncded bits (Y 4, Y 5, Y 6, and Y 7 ) select a particular signal ut f the signals f each subset. Figure 3.3 is based n the mapping by set partitining methds described in Chapter, Sectin..3. Imaginary Real c c d d c c d d a b a b a a b b g g h h g g h h e e f f e e f f i i j j i i j j k k l l k k l l p p p p m m n n m m n n Y Y Y a b c d e f g h Y 3 i j k l m n p c c d d c c d d a b a b a a b b g g h h g g h h e e f f e e f f i i j j i i j j k k l l k k l l p p p p m m n n m m n n c c d d c c d d a b a b a a b b g g h h g g h h e e f f e e f f i i j j i i j j k k l l k k l l p p p p m m n n m m n n c c d d c c d d a b a b a a b b g g h h g g h h e e f f e e f f i i j j i i j j k k l l k k l l p p p p m m n n m m n n Figure 3.3 A 56-signal cnstellatin fr the D 6-state TCM scheme 3.. A 4-Dimensinal Encder Implementatin Figure 3.4 depicts a schematic diagram f the 6-state TCM encder with mapping fr the 4D cnstellatin. A cmbinatin f lgic gates and DFFs as memry

57 devices are used t implement the differential cding and generate the cnvlutinal cding states. The tw D symbls I mn and I m( n+) (m =, k) are simultaneusly input int a 4D TCM encder at every tw successive time intervals n and n+. This means that the signal is sampled at every tw clck cycles, then a k-bit sampled symbl at the T clck cycle (i.e., half baud rate) is sent ut. I k ( n+) Z k ( n+) I I ( n+ ) I 3 ( n+ ) ( n+ ) I kn I n I 3n I n Differential Encder Cnvlutinal Encder rate=/3 I n I 3 n I n Y n 4D Blck Encder Bit Cnverter Z Z Z Z 3 ( n+ ) ( n+ ) Z 3n Z n Z kn ( n+ ) ( n+ ) Z n Z n Uncded digits select signal frm cnstellatin, and Cded digits select cnstellatin I Q Mapping Figure 3.4 A 6-state 4-dimensinal TCM encder The differential encder encdes tw (I n and I 3n ) ut f three mst-significant bits (I n, I n, and I 3n ) frm time interval n symbl. The differential encder uses the Blean expressins: I ( ) = ( ) ( n n I n n I n n ) (3.) I n ) = [ I ( n ) I ( n )] I ( n ) I ( ) (3.) 3n ( n n 3n 3n n where n and n - are new cntinual time intervals (i.e., half baud rate). The tw 43

58 differentially cded bits, I n and I n, are cnvlutinal encded thrugh a rate=/3 encder. The cnvlutinal encder has a same architecture and lgic functin as described in Sectin 3.. fr the D TCM scheme. After cnvlutinal encding, the extra redundant parity bit (Y n ) is added, while ther bits (I 4n I kn, I (n+) I k(n+) ) in tw D symbls remain unchanged. All the cded and uncded bits are finally mapped int the tw cnsecutive I-Q symbls by a mapping blck. The mapping cnsists f three sub-blcks 4D Blck Encder, Bit Cnverter and cnstellatin subsets selectin blck. The bit cnverter is used t select a subset D i, respective D j in the cnstellatin that depends n (, ) as defined in Table Y n I n, I n, I 3n 3., and each signal in these subsets is given by the uncded bits. Table 3. 4D subsets allcatin, 4D types (D i, D j ) Z n, Z n, Z( n+ ), Z( n+ ) Y n I n, I n, I 3n (D, D ) (D, D ) (D, D ) (D, D ) (D, D ) (D 3, D 3 ) (D, D 3 ) (D 3, D ) (D, D ) (D, D 3 ) (D, D 3 ) (D, D ) (D, D ) (D 3, D ) (D, D ) (D 3, D ) The D i subsets, i =,,, 3, are given fr each set f q uncded bits shwn (LSB t 44

59 MSB) in the QAM cnstellatin. The cmbinatins f Z n nz and Z ( n+ ) Z( n+ ) are used t select the pair f D subsets crrespnding t the 4D type. Table 3. shws the crrespndence between the bit pair Z k Z k, k = n, n+, and D subsets D, D, D, D 3. Table 3. Crrespndence between Z k Z k and fur D subsets Z k Z k D Subset D D D D 3 The Bit Cnverter lgic functin can be analyzed based n Table 3. as: Z n I n = (3.3) Z n I 3n = (3.4) Z ( n ) = Yn I n + (3.5) [ Yn I n ] I 3n I n Z ( n ) = + (3.6) The 4D-blck encder takes three f the remaining uncded infrmatin bits I ( n+ ), I ( n+ ) and I 3 ( n+ ) t generate tw pairs f selectin bits, Z nz 3n and Z Z in accrdance t Table 3.3 listed n next page. ( n+ ) 3( n+ ) The pair Z 3n nz will be used t select the inner grup r the uter grup f the selected D subset by Z n nz. The ther pair Z ( n+ ) Z3( n+ ) will be used t select the inner grup r the uter grup f the selected D subset by Z ( ) Z( ). The inner n+ n+ grup is rganized int tw halves. If the bit pair Z k Z 3k (k = n, n+) is, ne-half f the inner grup is selected, and if the bit pair is, the ther half f the inner grup is 45

60 selected; therwise the uter grup is selected. The inner grup and the uter grup are the tw grups in the D cnstellatin, as explained in Chapter, Sectin.3.3. Table 3.3 4D blck encder I ( n+ ) I ( n+ ) I 3 ( n+ ) Z n Z 3 n Z ( n+ ) Z 3 ( n+ ) The 4D-blck encder lgic functin can be btained based n Table 3.3 as: Z I I = I I I ) (3.7) n = ( n+ ) ( n+ ) ( n+ ) ( ( n+ ) ( n+ ) Z I I I ) (3.8) 3 n = ( n+ ) ( ( n+ ) + 3( n+ ) Z I I = I I I ) (3.9) ( n+ ) = ( n+ ) ( n+ ) ( n+ ) ( ( n+ ) ( n+ ) Z I I I ) (3.) 3 ( n+ ) = 3( n+ ) ( ( n+ ) + ( n+ ) The TCM encder is easy t implement int hardware using the abve infrmatin. The issue f TCM cdec is hw t implement the decder in hardware t achieve high speed with a minimum silicn area. The next sectin explains in detail the TCM decder implementatin. 3. Decder Implementatin In this thesis, the demdulatin prcess is assumed t be separated frm the decder prcess and the detectin prcess invlves hard decisins. Each single pint 46

61 frm the cnstellatin has been selected. The free Hamming distance f the cnvlutinal cde is used in Viterbi Algrithm t calculate the cst f each branch and path. The cst values are als called branch metric and path metric. The TCM technique recmmends using sft decding, which means the demdulatin prcess is incrprated int the decding prcess and the Euclidean distance is used as the cst functin quantity in the Viterbi Algrithm. As mentined in Chapter, the sft decding btains apprximate db perfrmance ver the hard decding. Due t the effect n the decding perfrmance is nt significant, using hard decding has a tremendus benefit in hardware implementatin. The reasn fr this benefit is when the Euclidean distance is increased by set partitining mapping methd; any nise perturbatin is less likely t affect the estimatin f the pints t be detected using the hard decisin detectin. In rder t increase the speed f the decder, tw pre-calculated lk-up tables (LUTs) are used. One LUT is used t btain the Hamming distance f each branch metric when the branch cst is required t be calculated. The ther LUT is used t make decisins n the utput f cnvlutinal decder when tw cntinual time interval delay states are knwn. The rest f this chapter describes in detail f the cnstructing f the Hamming Distance Lk-Up Table (HDLUT), the Output Lk-Up Table (OLUT) and the decder implementatin architecture. 3.. Structure f the HDLUT and OLUT Based n the 6-state TCM encder illustrated in Sectin 3., bth D and 4D TCM schemes have the same cnvlutinal encder structure, except they wrk at the 47

62 different baud rates. Accrding t equatins (3.6) t (3.), the 6-state Trellis diagram fr bth TCM schemes is cnstructed and shwn in Figure 3.5. Path State I I Y n n n Current Delay State Next Delay State S S S S S S S3 S3 Figure 3.5 Trellis diagram f the 6-states TCM encder In this 6-state Trellis diagram, given a particular set f delay states ( S SS S3), nt all eight path states ( ni ) are pssible t be used in that time interval, and nt Y I n all 6 delay states are pssible t be reached in the next delay state. The particular path chsen at that time interval depends n the current path state f the encder, which means the current path state cntrls which successr delay state t be reached frm that particular current delay state. Fr instance, if the current delay state is "", the successr delay state ( S SS S3 ) will be "", "", "" and "" when crrespnding t the path state ( ni ) are "", "", "" and "". Fr ne Y I n 48

63 specific current delay state, there are nly fur successr delay states being reached ut f sixteen delay states, and each branch crrespnds with ne specific path state ut f the eight pssible path states. Frm the trellis encder, the path state als represents the cded bits fr the utput f the cnvlutinal encder at the current time interval, s it reflects the true part bits ut f a symbl fr the decder input symbls. Each path state is ne 3-bit binary data f "", "", "" fr the /3 cnvlutinal encder. In the TCM cnvlutinal decder, the input symbl shuld be ne f eight pssible three cded bits frm "" t "" cmbined with the ther uncded bits at each time interval. Cmparing each pssible symbl with the truth symbl, the Hamming distance is easy t be calculated. This distance is cmputed by simply cunting hw many bit differences between the received channel symbl pairs and the pssible channel symbl pairs. Table 3.4 shws a pre-calculated HDLUT. Table 3.4 A Hamming Distance table Truth Path The crrespnding HD with the pssible part bit ut f received data sequence f the decder State (P) 3 (P) 3 (P) 3 (P3) 3 (P4) 3 (P5) 3 (P6) 3 (P7) 3 In this table, P ~ P7 represent truth path state frm t. If the current delay state ( S SS S3) is, the next delay state will be "", "", 49

64 "" and "" when crrespnding t the path state ( Y I ni n ) are P, P, P3 and P as shwn in Table 3.5. At this situatin, if the received symbl is, the three LSB bits are. It can be seen frm Table 3.4 that the cst fr each branch will be 3,,, and. Table 3.5 shws the relatinship between the delay states and the path states. Table 3.5 HDLUT using in the TCM decder Current Delay State Next Delay State The Path State Current Delay State Next Delay State The Path State Current Delay State Next Delay State The Path State Current Delay State Next Delay State The Path State P P P4 P4 P P P5 P5 P P P6 P6 P3 P3 P7 P7 P P P5 P5 P P P4 P4 P3 P3 P7 P7 P P P6 P6 P P P6 P6 P3 P3 P7 P7 P P P4 P4 P P P5 P5 P3 P3 P7 P7 P P P6 P6 P P P5 P5 P P P4 P4 In bth Figure 3. and Figure 3.4, after cnvlutinal encder, nly ne redundant bit Y is generated. This bit is cntrlled by the delay states S SS S3 and by a pair bits I n and I n. The tw bits I n and encder and they are the utputs f the cnvlutinal decder. I n are the inputs f the cnvlutinal ni is the path state Y I n shwn in Figure 3.5 the trellis diagram. Hence, if the current Delay State and the next 5

65 Delay State are determined, the particular path Y I n ni will be determined, then I n and I n will be recvered. Fr example, after tracing back, tw delay states and are determined t be the cntinual tw time interval delay states in survival path. Table 3.5 shws the path state is P ( ) crrespnding t this branch. As the result, a pair bit will be the decded I n and Figure 3.5, the OLUT is cnstructed and shwn in Table 3.6. Table 3.6 An OLUT using in the TCM decder I n bits. Based n Table 3.5 and Current Delay State The utput (I n I n ) f cnvlutinal decder when Next Delay State (S S S S 3 in decimal) is given (S S S S 3 ) () () () (3) (4) (5) (6) (7) (8) (9) () () () (3) (4) (5) *Nte: Empty cells in the table represent n relatinship between tw delay states The table shws a regular pattern between utput and delay states. Fr example, if utput is,,,, the crrespnding current delay states (S S S S 3 ) are and, r and. Accrding t the cmplementary law x + x =, states S S S S 3 ( + ) and ( + ) can be cmbined t (S S S 3 ) r. If cnsider frm next delay state, fr utput,,,, 5

66 the crrespnding next delay states (S S S S 3 ) are fur respectively grups: (,,, ), (,,, ), (,,, ) and (,,, ). Using the same law, they can be cmbined t (S S ),, and. Fllwed this pattern, Table 3.6 is simplified t Table 3.7. This simplificatin saves memry space r strage cells required in the hardware implementatin. Table 3.7 The simplified OLUT using in TCM decder Three Bits f Current Delay State The utput (I n I n ) f cnvlutinal decder when the tw bits f Next Delay State (S S ) is given (S S S 3 ) Frm this result, a decding lk-up-table is created and used in cnjunctin with the Viterbi algrithm t decde the cnvlutinal cde. Next sectin will g int detail f the architecture in implementatin f the -dimensinal and 4-dimensinal TCM decders. 3.. A Nvel TCM Decder Architecture Implementatin The TCM decder includes three prcesses: de-mapping, cnvlutinal decding, and differential decding. The implementatin algrithm f this cnvlutinal decding is mainly based n the Viterbi algrithm given in Chapter. Parallel prcessing is used at each nde (i.e., state) t trace the histry delay states f 5

67 the sixteen paths and the Hamming Distance is used as the cst functin. The distance calculatin circuit is mitted because the cst f each branch is btained frm HDLUT. This technically reduces cmplexity f the decder architecture. Utilizing the characteristics f shift registers, such as timing delay and memry, the real time tracing back prcess f the Viterbi algrithm is accmplished. In additin, in rder t shrten the time f the critical path in the decder, a pipelining technique is used; this technique increases the decding speed. When the receiver receives the signal, after de-mdulatin, the sampled signal enters the de-mapping prcess. The difference between -dimensinal and 4- dimensinal TCM scheme is in the prcessing f signal de-mapping. The cnvlutinal decding and the differential decding prcesses have the same methdlgy and structure, except they wrk at the different baud rates. The next tw subsectins describe mre details f the decder fr D and 4D TCM scheme respectively A Decder fr -Dimensinal TCM Scheme Fr D TCM scheme, the cded bits after cnvlutinal encder cmbined with the remaining uncded bits directly mapped int the 56-pint cnstellatin as shwn in Figure 3.3. The signal frm the demdulatin is sampled. The de-mapping is simply dividing the sampled signal int tw parts: 3-bits g thrugh the secnd step f TCM decder fr the cnvlutinal decding prcess, the remaining 5-bits is delayed using a grup f shift registers. Figure 3.6 shws the structure f D 6-state TCM decder. 53

68 54 Input Signal Sampling 8 3 STAU CS4U 3 "" STAU CS4U 4-LSB 9 9 "" 3 L5 L CS6U M U X D 4 D D D D D D D 4 D D D 4 4 Cnvlutinal decder 4 D D D Demapping 4 4 M U X 6 4 D 4 4 OLUT Differential Decder 4 7 utput Figure 3.6 A -dimensinal 6-state TCM decder

69 As shwn in Figure 3.6, 3-bits ut f fur LSB bits g thrugh cnvlutinal decding prcess directly; the remaining five bits enter int five grups shift register. The number f each grup shift registers is determined by the latency f the cnvlutinal decder. After cnvlutinal decding prcess cmpletes, -bit utput frm the cnvlutinal decder will cmbine with the -bit ut f 5-bits frm shifter register t execute the differential decding prcess. After differential decding, -bit frm the utput f the cnvlutinal decder, -bits frm the utput f the differential decder and 4-bits frm the utput f demapping are cmbined t frm a 7-bit utput symbl f the TCM decder. In the cnvlutinal decder, several steps are sequentially accmplished based n the Viterbi algrithm. They are represented by blcks such as State-Transitin and Add Unit (STAU), Cmpare-Selectin 4 Unit (CS4U), Cmpare-Selectin 6 Unit (CS6U), 6-t- multiplexer (MUX6) and OLUT. Since this thesis fcuses n 6- state TCM cdec, sixteen parallel paths are traced. The algrithm f bth CS4U and CS6U relies heavily n the cst functin. The minimum cst branch r path is selected. The State-Transitin and Add Unit is based n the Trellis diagram shwn in Figure 3.5. The current delay states split int fur new delay states; each branch cst is btained frm the HDLUT. The current cst adds t the previus accumulative path cst. The accumulative cst cmbines with the current delay state t be the utput f the STAU. Figure 3.7 shws the architecture f the STAU blck. 55

70 3-LSB State_Transitin and Add Unit path cst Current S SSS3 branch cst L5 4 HDLUT 5-bit Adder branch cst HDLUT 5-bit Adder branch 3 cst HDLUT 5-bit Adder branch 4 cst HDLUT 5-bit Adder Successr S S S S 3 Successr S S S S 3 Successr 3 S S S S 3 Successr 4 S S S S 3 Figure 3.7 Architecture f the STAU blck The utputs frm the STAU will input int the CS4U t select the survivr branch based n the Trellis diagram. The same successr (i.e., next delay state) branches are input int a same CS4U blck. Sixteen CS4U blcks are in path rder parallel arranged frm t. Since each utput f the STAU includes accumulative cst and current delay state, the CS4U selects the minimum accumulative cst branch as the new path accumulative cst. Fr this minimum accumulative cst, the crrespnding current delay state is chsen t be the predecessr delay state. The predecessr f the chsen survivr branch will be ne utput f the CS4U. The ther utput f the CS4U is the new path accumulative cst cmbined with the path label (i.e., sixteen paths, ). The predecessr utput f the CS4U is put int a shift register. The grups f shift registers are used t stre the histry delay states f the 6 paths. A minimum number f 6 shift registers is used t stre the past delay states. This numbers is 4 r 5 times the cde cnstraint length [6]; this length is the number f memry bits in the 56

71 cnvlutinal encder. A cnstraint length f 4 is used in this 6-state TCM scheme. The new path accumulative cst is taken frm the ther utput f the CS4U and sent back t the STAU. This path cst will be used in the STAU blck when the branch accumulative cst is calculated at the next time interval. Simultaneusly, the accumulative path cst inputs t the CS6U t select the survivr path, which is the path with minimum accumulative cst. Once the survivr path is chsen, sixteen sequential MUX6 lgics perfrm the delay states trace back. Once the fremst tw delay states are prduced, they will be sent t the OLUT. The OLUT is a pseud-rom and used t recnstruct the data I n and I n which was sent t cnvlutinal encder. The address t this ROM is the cmbinatin f tw cnsequence delay states as illustrated in Table 3.7 in Sectin 3... Finally, the LSB bit I n f the cnvlutinal decder and the delayed bit I 3 n ut frm the 4-LSB are differential decded. The differential decder perfrms the reverse functin f the differential encder in 6-states TCM encder as fllws: I ( ) = ( ) ( n n I n n I n n ) (3.) I n ) = [ I ( n ) I ( n )] I ( n ) I ( ) (3.) 3n ( n n sn 3n n where n and n - are cntinual half baud rate time intervals A Decder fr 4-Dimensinal TCM Scheme Fr the 4D TCM encder scheme, the cded bits after cnvlutinal encded are cnverted thrugh a Bit Cnverter t generate selectin pair bits fr the 4-dimensinal mapping as shwn in Figure 3.4. Hence fr 4D TCM decder, the signal frm the demdulatin is sampled and the de-mapping prcess perfrms the reverse f the 57

72 encder Bit Cnverter blck and the reverse f the 4D-blck encder. The lgic functin f the Bit Cnverter and the 4D-blck decder in the 4D TCM decder are the reverse functins f the 4D TCM encder. The lgic relatinship f these tw blcks was described in Sectin 3... The Bit Cnverter lgic functin in decder can be analyzed based n Table 3. as fllwing: Y (3.3) n = Zn Z( n+ ) (3.4) I n = Z n I Z Z Z Z Z ) (3.5) n = ( n+ ) n n ( n ( n+ ) (3.6) I 3 n = Z n The 4D-blck decder lgic functin can be analyzed based n Table 3.3 as: I + ) = Z( n+ ) ( Zn Z3 ) (3.7) ( n n I (3.8) ( n+ ) = Z3n + Z ( n+ ) I (3.9) 3 ( n+ ) = Z3( n+ ) + Z3n Z ( n+ ) Equatins (3.3) (3.9) can be easily cnverted int a schematic diagram. Figure 3.8 shws a schematic diagram f the Bit Cnverter used in the 4D TCM decder. Figure 3.9 shws the schematic diagram f the 4D-blck decder. 58

73 Z n Z n I n I 3 n Z Z ( n+ ) ( n+ ) I n Y n Figure 3.8 Schematic diagram f the bit cnverter Z n I ( n+ ) Z 3n Z ( n+ ) I ( n+ ) Z 3 ( n+ ) I 3 ( n+ ) Figure 3.9 Schematic diagram f the 4D-blck decder Figure 3. shws the structure f a 6-state 4-dimensinal TCM decder. In this structure, after de-mapping, three LSB bits ut f fur bits frm the Bit Cnverter are sent t the cnvlutinal decder. The ther bit is send t the shift register and will be cmbined with the utput bit frm the cnvlutinal decder. These tw bits are then sent t a differential decder. The remaining eight uncded bits and three bits frm 4Dblck decder are als sent t the shift registers. The number f shift registers is determined by the latency f the cnvlutinal decding prcess. This latency is the same as the D scheme, except the clck rate is different. If the clck f the D scheme is T, the clck f the 4D scheme is T. 59

74 L5 4 4 Input Signal Sampling "" 3 STAU 9 CS4U 9 4 CS6U M UX D D D D 4 M UX Bit Cnverter 3 3 "" STAU L5 9 CS4U 4 D D D D 4 Cnvlutinal decder 4 4D Blck D D D Decder 3 D D D 8 Demapping D 4 4 OLUT Differential Decder 4 utput Figure 3. A 6-state 4-dimensinal TCM decder

75 After the differential-decding cmpletes, the 4-bit symbl will be the utput f the TCM 4D decder. This symbl includes -bit frm the utput f the cnvlutinal decder, -bits frm the utput f the differential decder and -bits frm the utput f the de-mapping. Details f the cnvlutinal decder and the differential decder are the same as in the D TCM scheme, which are described in Sectin 3... Fr the 4D TCM scheme, tw mre blcks are required t accmplish the cnversin between tw symbls frm tw cntinual clck cycles f full baud rate t ne symbl fr half baud rate. Since tw cntinual symbls are cded simultaneusly fr 4D TCM encder as illustrated in Figure 3.4, the system input wrks at a full baud rate while the 4D TCM encder and decder wrk at a half baud rate. The blck diagram explaining this idea is shwn in Figure 3.. The detailed architecture f the blcks will be discussed in the next chapter. D Symbls D Symbls Tw-t-One Cnverter 4D TCM Encder Mdulatr Clck CLK-Div Channel D Symbls D Symbls One-t-Tw Cnverter 4D TCM Decder Demdulatr Figure 3. The 4-dimensinal TCM cding system 6

76 CHAPTER 4 TCM CODEC ASIC IMPLEMENTATION This chapter intrduces the cncept and design flw f the ASIC; centering n the TCM cdec ASIC implementatin, this chapter als illustrates the methdlgy used t increase the speed f the cdec such as pipelining techniques, and ther chip architectures such as the clck divider and the Built-In-Self-Test (BIST). 4. ASIC Design Intrductin Applicatin Specific Integrated Circuit (ASIC) design is an efficient way t implement specific system functins int a single chip [8]. The technique is widely used in high-speed internet chip design and telecmmunicatin applicatins. ASICs ffer sme advantages such as high speed, small area and lw cst manufactry in high vlumes fr industry specific prducts. A typical ASIC design prcess includes three basic stages: HDL design capture, HDL design synthesis, and design implementatin. Figure 4. shws a flw chart f an ASIC design prcess. 6

77 () HDL Design Capture Design Specificatin Behaviral Descriptin RTL Descriptin Verificatin Vectrs RTL Functinality Verified? N () HDL Design Synthesis Yes RTL t Lgic Cnstraints Lgic Optimizatin Lgic t Technlgy Cnstraints Timing/Area Optimizatin Scan Path Insertin & Test Vectr Generatin Netlist Lgic & Timing Verified? N (3) Design Implementatin Yes Flr Planning Place & Rute Physical Layut Layut Functin & Timing Verified? N Yes Chip Fabricatin Figure 4. A flw chart f the ASIC design prcess 63

78 () HDL design capture implements the tp-dwn design methdlgy frm abstract cncept r algrithm dwn t hardware in manageable and verifiable steps. This invlves develping a design specificatin that will be used t create a high level behaviral abstractin with high level prgramming languages such as C r C++. Additinally, the behaviral abstractin may als be created using hardware descriptin languages (HDL) such as VHDL r Verilg. The behaviral abstractin shuld be simulated in rder t verify that the desired functinality is captured cmpletely and crrectly. The behaviral abstractin is then used as a reference t create and refine a synthesizable register transfer level (RTL) abstractin. This RTL cde captures desired functinality required by the design specificatin. The difference between a purely behavir abstractin mdel and a RTL abstractin mdel will be described later; bth mdels are used in functinality verificatin, but slightly different in the hardware synthesis. Generally, the designs are represented in HDL at three levels f abstractin: Behaviral level: a design is implemented in terms f the desired algrithm, much like sftware prgramming and withut regard fr actual hardware. Fr example, a Verilg HDL mdel written at the behaviral level is usually nt synthesizable int hardware mdel by the synthesis tls. Register transfer level: a design is implicitly mdeled in terms f hardware registers and cmbinatinal lgic that exists between them t prvide the desired data prcessing. The key feature f this level is that an RTL descriptin can be translated int hardware mdel by the synthesis tls. Structural level: a design is realized thrugh explicit instances f lgic 64

79 primitives and intercnnectins between them. This level is als referred t as a gate level mdel. It is a hardware mdel and is used t create the flrplan f the circuit layut. Mst synthesis tls can generate the gate-level mdel after synthesizing the RTL cde. HDL Design Capture is cmpleted with pre-synthesis simulatins t verify that the RTL abstractin fully prvides the desired functin. The functinal verificatin in the design prcess that ccurs at this pint must be as cmplete and thrugh as pssible. The test vectrs used during simulatin shuld prvide the fault cverage necessary t ensure the design meet specificatins. () HDL design synthesis invlves steps using a synthesis tl t: Translate the abstract RTL design descriptin t register elements and cmbinatinal lgic. Optimize the cmbinatinal lgic by minimizing and flattening the resultant Blean equatins. Translate the ptimized lgic level descriptin t a gate level descriptin using lgic cells frm the specified technlgy library. Optimize the gate level descriptin using cell substitutin t meet the specified area and timing cnstraints. Prduce a gate-level netlist f the ptimized circuit with accurate cell timing infrmatin. HDL design synthesis finishes with pst-synthesis simulatins t verify that the gate level circuit fully prvides the desired functinality and meets the apprpriate timing requirements. 65

80 (3) Design implementatin invlves steps using layut tls [3] t: Create a flrplan fr the IC frm the gate-level netlist fr the design including a default grup f cells, I/O ring cnnected, and defined placement sites fr all the cells. Place cre cells by using frward-anntated timing cnstraints infrmatin frm the synthesis step. Add clck buffer cells and nets t create a balanced clck tree, which exceeds the parameters specified in synthesis. Generate a glden netlist f the design t be used fr final verificatin. Verify the functinality f the glden netlist. Rute the pwer, clck, and regular nets f the design. Functinally verify the physical (placed and ruted) layut f design that cntains the same instances, nets, and cnnectivity as the verified glden netlist. Alternatively, d the layut-versus-schematic (LVS) verificatin. Execute the design rules check (DRC) f the layut and fix DRC errrs. In the VLSI design rules, circuit gemetry is specified based n methdlgy. The unit f measurement can easily be scaled t different fabricatin prcesses as semicnductr technlgy advances. Each design has a technlgy-cde assciated with the layut file. Each technlgy-cde may have ne r mre assciated ptins added fr the purpse f specifying either (a) special features fr the target prcess r (b) the presence f nvel devices in the design. This ASIC implementatin is based n the.8µm CMOS technlgy. Identify nets with antenna rule check (ARC) and perfrm the advanced DRC 66

81 under manufactry requirements. Antenna rules deals with the prcesses which may cause gate xide damage such as: (a) expse plysilicn and metal structures, (b) cnnect t a thin xide transistr, (c) cllect charge frm the prcessing envirnment (e.g., reactive in etch), and (d) develp ptentials sufficiently large current t flw thrugh the thin xide. Failing t cnsider antenna rules in the design may lead t either reduce perfrmance r induce damage in the transistrs expsed prcess. The chip may be ttally failure if the antenna rules are seriusly vilated. Design implementatin is cmpleted with the physical verificatin n the chip layut which shuld have DRC and ARC errr free. The final chip can nw be fabricated. This stage is the black bx prcess in the digital flw fr.8µm CMOS technlgy. The TCM cdec chip implemented in this prject fllws the abve ASIC design digital flw. Next sectin describes the verall architecture f this chip. 4. Tp Mdule Architecture f the TCM Cdec ASIC Chip Figure 4. shws the verall architecture f the TCM encder/decder chip implemented in this prject which includes D and 4D TCM schemes. In the encder, the blck labelled tcmencderd perfrms the D TCM encder architecture described in Sectin 3... The blck labelled tcmencder4d perfrms the 4D TCM encder architecture described in Sectin

82 inde_ena switch 6 ut_enc tcmdecderd bist_ena input_data 6 sample tcmencderd 3 4 decder6 7 7 ut_dec input4d tcmencder4d tcmdecder4d utput4d 68 clk slw_clk 5 6 rst test_mde BIST test_ut Figure 4. Overall ASIC chip architecture f the TCM cdec

83 In the decder, bth D and 4D share the same blck labelled decder6, which executes the cnvlutinal decding prcess described in Sectin 3... This blck wrks at different timing cycle cntrlled by a switch signal. Meanings f all the I/O signals used in the cdec will be described in Sectin 4... The blck labelled tcmdecderd perfrms the de-mapping and the differential decding prcesses fr the D TCM decder, while the blck labelled tcmdecder4d perfrms the demapping and the differential decding prcesses fr the 4D TCM decder. Details f these tw blcks are described in Sectin 3... Sectin 4.. will describe the remaining blcks in detail. 4.. I/O Signal Descriptin Figure 4.3 shws the input and utput signals fr the TCM chip designed in this thesis. Sme f the IO signals are nt implemented in the finally chip due t the limitatin in silicn area prvided by CMC. inde_ena switch bist_ena input_data[5..] clk rst test_mde TCM Cdec ut_enc[5..] ut_dec[6..] test_ut Figure 4.3 I/O signals illustratin f the TCM cdec The inde_ena is a decder enable signal which cntrls the input symbl fr TCM decder. When the cntrl signal inde_ena is set t, the TCM decder will decde the symbl sequence cming frm external input input_data, which is a 6-bit 69

84 data sequence fr tcmdecder4d and a lw 8-bit data sequence fr tcmdecderd. When inde_ena is set t, the TCM decder will decde the symbl sequence cming frm the internal signal, which is the utput f multiplexer in Figure 4.. The switch signal cntrls the functin f the TCM cdec chip. If the switch is, the chip wrks in the D TCM scheme; if the switch is, the chip wrks in the 4D TCM scheme. The bist_ena is a BIST enable signal which enables r disables the chip in BIST mde. If it is, the utput f multiplexer (i.e. input f the encder) takes 7 LSBs ut f the 6 bits input_data. If it is, the utput takes the pseud input generated frm the BIST blck. The input_data is a 6-bit input signal f this chip. Fr general TCM encder/decder applicatin, the external input symbl sequence fr TCM encder is the LSB 7-bits ut f 6-bits input_data fr bth the D and 4D encders. In the layut flrplan creating prcess, since the chip size is decided by PAD limited plicy, which means ptimizing based n the number f all I/O PAD and pwer PAD. In rder t minimize the number f I/O PAD, the input_data signal used in the chip is 6 bits nly when the 4D TCM decder part requires t be tested. The clk is the glbal clck signal f this TCM cdec chip. The rst is the reset signal f the chip; this is an active lw signal, the system will reset if rst is. The test_mde signal cntrls the chip transfrm its wrking status between nrmal cdec functin and scan test. When the chip is under scan test, all blcks related t the 4D TCM scheme will be frced t wrk at high frequency. That means if test_mde is, the clck f all blcks related t the 4D TCM scheme will use an 7

85 external system clck; if test_mde is, the clck f all these blcks will use the clck selected by the switch cntrl signal. This signal is used t keep the scan test simple. Scan test is used t detect prblems ccurred at the time f fabricating and packaging. The ut_enc is a 6-bit utput signal f TCM encder blcks. It is a mapping signal ready fr D r 4D mdulatin. This ut_enc signal is the utput frm multiplexer in Figure 4. cntrlled by the switch signal. When switch is, nly the 8-LSB ut f ut_enc is available fr D mdulatin. The ut_dec is a 7-bit utput signal f the TCM decder blck. It is the recvered riginal input signal. This signal sequence shuld be same as the 7-LSB f input_data signal sequence if the chip functins prperly. The test_ut is an utput signal indicating the result f BIST. If it is, it shws the TCM cdec functinal self-test passed. If test-ut is, there are prblems existing in the system, which culd be design and/r fabricatin faults. Sectin will describe in detail the BIST f this design. 4.. Individual Blck Descriptin Fr the D TCM scheme, the 7-bits input data is directly cded thrugh tcmencderd blck at full-baud rate. Fr the 4D TCM scheme, the input f encder spans ver tw cnsecutive symbl perids. These tw-symbl bits are cnverted int parallel m-tuples at half f the baud rate. As described in Chapter 3, Sectin 3..., the 4D TCM cding system requires mre lgic blcks cmpared t the D TCM system. The blck input4d perfrms tw D signals t ne 4D signal cnversin. The 7

86 utput4d perfrms the reverse prcess. The clk_div implements the half-baud rate clck cnversin. This clck is used fr all the blcks within the 4D TCM scheme. The next subsectins describe these blcks in detail The Multiplexers There are seven -t- multiplexers (MUX) used in this chip tp mdule: MUX selects input signal fr TCM encder. It is cntrlled by the signal bist_ena. MUX selects the utput frm TCM encder blcks tcmencderd and tcmencder4d. It is cntrlled by the signal switch. MUX 3 selects the input signal fr TCM decder. It is cntrlled by the signal inde_ena. MUX 4 selects de-mapping symbl bits frm tcmdecderd and tcmdecder4d, which will be used in the cnvlutinal decding prcess. It is cntrlled by the signal switch. MUX 5 selects the different clck fr each TCM scheme, the external input clck (i.e. full-baud rate) is fr D TCM scheme, test mde and input/utput f the 4D scheme; the internal divided clck (i.e. half-baud rate) is used in the 4D TCM scheme. It is als cntrlled by the signal switch. MUX 6 selects the clck fr blck decder6, tcmencder4d and tcmdecder4d. It is cntrlled by the signal test_mde. In the case when the system is under the scan test, all the blcks f the chip wrk at the same clck rate. 7

87 MUX 7 selects the utput f TCM decder blcks tcmdecderd and utput4d. It is cntrlled by the signal switch The Clck Divider Clck divider is the div_clk blck shwn in Figure 4.. Fr the 4D TCM scheme implementatin, the encder and decder wrk at half-baud rate, which means the data transmissin rate is nly the half f the D TCM scheme cdec. Since the trellis states and structure are same in bth D and 4D TCM scheme, if the data transmissin rates are the same in bth TCM cdec systems, the thrughput f the 4D TCM scheme will be duble f the ne in the D TCM scheme. If the input clck perid is T, in rder t get the new clck perid T t cntrl the 4D TCM cdec, a clck divider is required. Figure 4.4 illustrates the signals f clck divider. rst clk Clck Divider div_clk phase Figure 4.4 Clck divider signals illustratin There is a D-Flip-Flp used t generate div_clk and phase signals inside the Clck Divider blck. When rst is, the DFF is initialized. Else when rst is, the DFF wrks at psitive edge f clck clk t invert the input f DFF. The signal phase is used fr crrecting the half phase deviatin ccurring when the tw cnsecutive symbls are cnverted t ne symbl in the input4d blck and ne symbl is cnverted t tw cnsecutive symbls in the utput4d blck. Figure 4.5 shws the wavefrms f the clck divider. 73

88 rst T clk q div_clk phase T Figure 4.5 The wavefrm f clck divider The div_clk and phase signals are the same but they are used in different lcatins f the chip. The div_clk signal is required t be clean t generate the clck tree in the chip layut prcess The Built-In Self Test The BIST blck is used fr functinality self-testing f the chip, including bth D and 4D TCM schemes. BIST is defined as a design-fr-test (DFT) technique in which testing (test generatin and test applicatin) is accmplished thrugh the built-in hardware features [8-9]. The BIST technique ffers a number f advantages in chip design: Fast and efficient: same hardware is capable f testing chips, bards and systems. At the system level, BIST is a cheap testing slutin. Testing during peratin and maintenance. Unifrm technique fr prductin, system and maintenance tests. Dynamic prperties f the circuit can be tested at speed. 74

89 Supprt cncurrent testing. Can be used fr delay testing as it can be used in real time. Hwever, BIST technique als expses sme disadvantages: Silicn area verhead: additinal silicn area f the chip must be reserved fr BIST circuitry. This increases the cst f the IC. Access time: by adding additinal test circuitry, it is necessary t add at least ne extra level f lgic peratin between inputs and design chip circuitry, as well as a level lgic peratin at the utput f the chip. Requires extra input/utput cnnectin: BIST circuitry may require I/O pins t cmmunicate with the utside. Crrectness is nt assured: it is difficult t test the chip hardware under all cnditins. Verifying crrect peratin f such hardware is a difficult issue. A BIST test structure used in this chip is a Linear Feedback Shift Register (LFSR). The LFSR prduces a pseud randm symbl sequence. Therefre it is als called a Pseud Randm Pattern Generatr (PRPG). The plynmial used in this BIST is +x 4 +x 5. Figure 4.6 shws a PRPG based n this plynmial. initializatin status data I I I I 3 I I 4 5 I6 + Figure 4.6 The structure f LFSR 75

90 The 7-bit LFSR scrambler can be used t create a pseud randm 7-bit signal sequence. In rder t create a lnger nn-repeat randm sequence, a 5-bit LFSR scrambler is used in this prject. The length f this randm pattern is 5. The 7 bits test vectr, I II I 3I 4I 5I 6 is randmly selected frm the 5-bit LFSR and it is fixed n this selectin. It will be used as the test input signal sequence f the TCM cdec system. The utput f the TCM cdec will be fed back t the BIST t be cmpared with the pseud randm symbls created by anther randmizer LFSR-D r LFSR-4D dependent n the switch signal. Figure 4.7 shws the architecture f the BIST blck. TCM cdec system clk rst LFSR + test_result cunter-d LFSR-D cunter-4d LFSR-4D switch BIST Figure 4.7 The architecture f the BIST blck n the TCM cdec chip LFSR-D and LFSR-4D have the same structure as LFSR. They are initialized at different clck cycle based n the result f the cunter-d and cunter-4d, which are the latency f the TCM cdec fr the D TCM scheme and the 4D TCM scheme, respectively. If the utput signal test_result is, the TCM cdec chip functins prperly; therwise, the chip fails n its functinal self-test. 76

91 4.3 Register Transfer Level Cde in VHDL In this research, all register transfer level cdes are written in VHDL. VHDL stands fr VHSIC (Very High-Speed Integrated Circuit) Hardware Descriptin Language [3]. It can be used fr behaviral mdeling f designs r fr lgic synthesis using either behaviral r structural descriptins. Since writing structural circuit descriptins is like trying t describe a circuit using text instead f a schematic editr, the advantage f VHDL is in its behaviral synthesis ptential. Fr cmplex circuit designs like this TCM cdec, writing RTL cde in descriptin language is mre simple and cnvenient than drawing schematic circuits. Based n the architecture shwn in Figure 4. and the behavir described in Chapter 3 and Sectin 4.., the RTL cdes f the tp mdule and each blck f the chip were written in VHDL. All the RTL cdes were cmpiled and simulated using Cadence NC-Sim. Functinal simulatin result f the design perfrmed as expected and will be described in Chapter 5. Increasing the speed f the chip is equivalent t shrten the length f its critical signal path. This can be achieved by using a technique called pipelining. 4.4 Pipelining Pipelining refers t the partitining f a prcess int successive, synchrnized stages such that multiple prcesses can be executed in parallel. Depending n the granularity f the prcess, three types f pipelining techniques can be identified [8]: Instructin pipelining partitins prcesses int stages f instructin fetchdecde, perand-fetch, and executin. 77

92 Intra-functinal unit pipelining divides the executin unit (usually a cmbinatinal circuit) int several segments f equal delay time. Inter-functinal unit pipelining invlves predefining a sequence f frequently encuntered primitive peratins such as multiplier r accumulatr structure. In this TCM cdec system, the intra-functinal pipelining methd is used. Extra registers are inserted t divide the executin path int several shrt paths. Pipelining techniques aim at imprving system thrughput. It allws digital synchrnus system t be clcked at a higher rate. In digital cmmunicatin systems, the thrughput f the chip is defined as the number f bits that can be transferred by the system per secnd. Nrmally, it is the number f bit in data symbls times the system frequency. Fr example, if 8-bit symbls are prcessed thrugh a MHz cmmunicatin system, then the thrughput f the system is 8MHz (i.e., 8Mbits/secnd). Generally, system frequency is determined by the prpagatin delay f the lngest path in the pipeline segments (i.e., the critical timing path in the chip). The path starts frm ne register and ended at the next register. By using pipelining technlgy, extra registers are inserted int the critical path. The insertin shrtens the path and decreases timing f the critical path; this results in an imprvement f the system frequency and thrughput. One drawback f the pipelining technique is, while the path gets shrter, the system latency gets lnger because extra delays are intrduced due t the increase in the number f shift registers. Latency refers t the number f clck cycles that the system takes t respnd t the input, which means the time taken when the first input symbl entering the decder t be restred at the utput. 78

93 4.5 System Synthesis The Synpsys design cmpiler is used t perfrm the synthesis f the system RTL cde. Design cmpiler is the cre f the Synpsys synthesis sftware prducts. It prvides cnstraint-driven sequential ptimizatin and supprts a wide range f design styles. The design cmpiler synthesizes a HDL descriptin int a technlgy-dependent, gate-level design. Using design cmpiler defines the envirnmental cnditins, cnstraints, cmpile methdlgy, design rules, and target libraries t achieve design gals. The TSMC.8µm CMOS technlgy library is used in this research. The synthesis prcess fllws these general steps: Read in the design and its sub-designs. Set design attributes n the tp-level design. Set realistic timing r area gals fr the design. Run check-design t verify the design. Identify and crrect any errrs. Perfrm design cmpiler ptimizatin. Run area and cnstraint reprts t determine whether design gals are met. Insert scan circuitry. Perfrm final check and generate gate-level Verilg netlist. During the synthesis prcess, the scan chain is added int the chip. Scan chains are rutes included n a chip fr testing purpses. The Synpsys test cmpiler substitutes all sequential devices (i.e. flip-flps) with scan equivalents, and then cnnects them tgether t frm a scan chain. Each scan chain will be rerdered during layut place and rute prcess t minimize ruting based n layut flrplan placement. 79

94 The test cmpiler will then be used t create a set f test vectrs which can detect Stuck-At- and Stuck-At- faults in the chip. Stuck-At- and Stuck-At- are tw mdels f stuck-at faults fr each cell pin in ASIC cell pin test. The measure f test quality is ften based n the percentage f ASIC cell pin stuck-at faults that are detected. Cell utput faults are interpreted as the utput is stuck-at either the lgical ne r the lgical zer state independent f the input cnditin. Other features such as vectr cmpactin and fault cverage estimatin are als perfrmed. If basic design methds are fllwed, the fault cverage shuld btain abve 9%. In industry, the higher the fault cverage, the fewer defective chips will be packaged and placed in prducts. In this designed chip, the fault cverage achieved t 96%. Reducing the number f defective chips used at the time f initial testing (with the scan-based test) reduces the time and mney spent n defective devices. Purpse f scan-based test is t detect prblems created at the time f fabricating and packaging; the scan test des nt intend t find design faults. The synthesis prcess als generates timing cnstraints f the design and a gatelevel netlist; these cnstraints infrmatin are used in Cadence layut tls t prduce a chip layut. All the results f simulatin and chip layut will be prvided in Chapter 5. 8

95 CHAPTER 5 RESULTS This chapter prvides the simulatin and hardware implementatin results f the TCM D and 4D cdec system. The research was accmplished in fur stages:. Using MATLAB t simulate the Viterbi algrithm cmbining with the use f Hamming distance and utput lk-up table.. Using an Altera FPGA device t implement and simulate the cdec in bth functinality and timing analysis. 3. Using Cadence NC-Sim t simulate system functinality, using Synpsys t synthesize hardware language cde, and using Cadence tls t finish chip layut. 4. Using lab equipment t test the final ASIC upn receiving. In additin, hardware implementatin results in FPGA and ASIC are als cmpared. 5. MATLAB System Simulatin Results MATLAB is a simulatin tl. It stands fr "matrix labratry" because the prgram is based n matrices t perfrm all the calculatins in the simulatin prcess. MATLAB is an integrated technical cmputing envirnment that cmbines numeric cmputatin, advanced graphics and visualizatin, and a high-level prgramming 8

96 language. It has widely applicatin areas as technical cmputing, digital signal prcessing and cmmunicatin design, cntrl design, image prcessing, test and measurement, financial mdeling and analysis. In this research, Hamming Distance and utput lk-up tables are intrduced int the Viterbi algrithm t simplify calculatin and cmplexity in the decding prcess as shwn in Sectin..6 and Sectin 3... In rder t test the feasibility f the algrithms and techniques, MATLAB cde was written fr the cnvlutinal cdec using the methds described in previus chapters. In this cde, the Hamming distance and the decder utput lk-up tables were built int matrices. The input sequence initialized int tw matrices represented the tw-bit input f the cnvlutinal encder. The cnvlutinal cde rate was /3. Lgic functins frm the MATLAB library were used in the cde. MATLAB simulatin was run using the written cde. Figure 5. shws the input sequence f the TCM encder. Figure 5. shws the cdewrd sequence at the utput f the encder. This cdewrd sequence was then entered t the decder t decde the sequence and retrieve the riginal input. The utput sequence frm the TCM decder is shwn in Figure 5.3. The written MATLAB cde was simulated t verify the use f lk-up table in the Viterbi algrithm t decde the cnvlutinal cde in the TCM cdec. The simulatin stred data in ne-dimensinal matrix and did nt cnsider any timing requirement therefre there were n delays shwn in simulatin result graphs. This MATLAB simulatin is different frm hardware descriptin language simulatin in which HDL simulatin shws timing and latency f the system. MATLAB simulatin 8

97 simply verifies the feasibility f the algrithm and functinality f the cdec. Signal Value Time Interval Figure 5. Input sequence f the cnvlutinal encder 8 Signal Value Time Interval Figure 5. Cdewrd sequence f the cnvlutinal cding Signal Value Time Interval Figure 5.3 Output sequence f the cnvlutinal decder 83

98 The input used tw-bit symbl sequence. The utput result in Figure 5.3 was the same as the input signal sequence in Figure 5.. This indicated that the decder successfully recvered the riginal signal sequence. It als demnstrated that the simplified algrithm is practical. This simulatin cnfirmed the methd and crrectness f the lk-up tables described in Chapter 3. Next sectin describes the implementatin results in FPGA, which further cnfirms the feasibility f hardware implementatin f the algrithm and the technique develped in this research. 5. FPGA Prttype Implementatin Results As the simplified algrithm was verified thrugh MATLAB simulatin, a synthesizable VHDL cde was written in particular fr the Altera FPGA device cmpiler. The hardware language cde fr the TCM encder/decder was based n the architecture described in Chapter 3 fr -dimensinal and 4-dimensinal TCM cdec. The VHDL cde was imprted int the Altera MAXPLUS II and cmpiled. After successfully cmpiled, a netlist was generated and the design was fit int an autmatically chsen FPGA device. The cmpiler generated a reprt t indicate the amunt f hardware required t implement the cdec. Timing analysis was perfrmed t determine the peratin frequency (i.e., data rate) f the cdec fr that particular FPGA device. Finally, a simulatin was run based n that device t perfrm functinality and timing analysis. MAXPLUS II prvides a pwerful simulatin tl which allws the user generate input data and change value f the signal at any time interval f the simulated wavefrms. Table 5. shws the verall results fr D and 4D 84

99 TCM cdec system n Altera FPGA device. The peratin frequencies are based n the fastest simulatin clck using MAXPLUS II. Altera FPGA device name Table 5. FPGA implementatin results D TCM cdec 4D TCM cdec Encder Decder Encder Decder EPFK RC4-3 EPFKL C84-3 EPFKL C84-3 EPFKL C84-3 Number f Lgic Cells Amunt f Memry Operatin frequency MHz MHz 5MHz 33MHz Input pins Output pins Data bits Thrughput (Bit rate) 7Mbps 6Mbps.75Gbps 58Mbps After cnfirming the feasibility f the algrithm and architecture frm sftware simulatin and FPGA implementatin, the TCM cdec was implemented int an ASIC using the ASIC design prcess described in Chapter 4. Next sectin shws the details f the implementatin results. 5.3 ASIC Implementatin Results The TCM cdec was implemented int an ASIC using TSMC.8µm CMOS technlgy. This TSMC technlgy is a single ply, six metal layers prcess. The technlgy nt nly achieves minimum drawn gate length f.8µm, but als layut and intercnnects design rules that are apprpriate t the new generatin f chip design and fabricatin. This technlgy has the tightest metal pitches with.46µm cntacted metal layer,.56µm cntacted metal layers thrugh 5, and.9µm n metal layer 6. These pitches prvide a higher gate density and mre die per wafer, which leads t a 85

100 lwer cst per chip. The.8µm CMOS technlgy ffers the ptimal cmbinatin f density, speed and pwer t serve a brad range f cmputing, cmmunicatins and cnsumer electrnics applicatins. This technlgy is suitable fr IC design in varius micrelectrnics areas such as analg, lw pwer, RF, and full custm digital circuits. The recmmended nminal supply vltages fr this technlgy are.8 and 3.3 vlts. In the ASIC implementatin, the time delay cntrls the verall peratin frequency f the device. This delay is determined by the lngest time f the critical path in the design. Pipelining is a technique t reduce delays f these critical paths. Pipelining was inserted in this design t imprve decding speed and data integrity. As shwn in the ASIC design flw (Figure 4., Sectin 4.), Cadence NC-Sim was used t cmplete the RTL cde simulatin in the first step. Next, Synpsys synthesis tl was used t synthesize the RTL cde and generate a Verilg gate-level netlist. This netlist was then used in the layut creatin. Cadence physical design planner (PDP r DP) was used t accmplish the flrplan initializatin, I/O cells creatin, grup s placement definitin, pwer planning, and clck tree generatin. After the clck tree was successfully generated, anther Verilg netlist was generated and this netlist was used t simulate the functinality f the cdec again. Bth Verilg netlist simulatins passed and verified that the design functin prperly. Cadence silicn ensemble (SE) interfaces was used as a tl t rute pwer, clck, and regular nets f the design. After ruting, SE exprted the design t a design exchange frmat (DEF) file. This file was then imprted int the Cadence design framewrk II (DFII) envirnment t perfrm layut-versus-schematic (LVS) and design rule check (DRC) verificatins. The final step n the chip layut is metal sltting, lg 86

101 adding, and streaming ut the design int a GDSII database fr fabricatin in.8µm CMOS. The GDSII stream frmat is the standard file frmat fr transferring/archiving D graphical design data. The file cntains a hierarchy f the design structures; each structure cntains layut elements such as bundary/plygn, path/pltline, textbx, structure references, and structure array references. These elements are situated n different layers. The stream is a binary frmat that is platfrm independent because it uses internally defined frmats fr its data types. The next sectins prvide results f each stage in the ASIC implementatin flw Register Transfer Level Cde Simulatin The RTL cde fr the TCM cdec was written based n the architecture described in Sectin 4.. The cde was simulated using Cadence NC-Sim. This simulatr is an ptimum verificatin slutin fr system-n-a-chip (SOC) design. It is a flexible and adaptable simulatr because it prvides the freedm t transparently mix Verilg and VHDL, and ther interface standards. A test bench prvided the system clck and reset signals. Inside the test bench cde, values f input signals shwn in Figure 4.3 were changed each time befre cmpiling the testbench, NC-Sim executed the testbench and prvided the fllwing simulatin results:. D BIST simulatin (switch =, bist_ena = ) 87

102 . 4D BIST simulatin (switch =, bist_ena = ) 88

103 89

104 3. D real input simulatin (switch =, bist_ena = ) 9

105 4. 4D real input simulatin (switch =, bist_ena = ) 9

106 In the signal wavefrms frm the simulatin results, the enin signal indicated the utput f the MUX in Figure 4. described in Chapter 4. The LSB 7-bits ut f 6-bit external input data were taken by enin when bist_ena was. When bist_ena was, enin tk the randm data generated frm BIST blck. All values shwn fr the input, enin and utput were hex numbers. These simulatin results verified the design functinality. The utput data sequence (i.e., utput signal) was the same as the input data sequence (i.e., the enin signal) after an encding/decding latency. The RTL functinal simulatin results are summarized in Table 5.. When BIST is active and functins prperly, the test_ut shuld be always. If Stuck-At- errr happened n this signal during fabricatin, the scan test shuld detect the errr. As shwn in Figure 4.7, the BIST blck generates a randm symbl sequence therefre it has anther extra clck cycle t input the sequence int the encder. Table 5. RTL cde simulatin results Functinal simulatin Result Latency D BIST simulatin Pass, test_ut = 36 clck cycles 4D BIST simulatin Pass, test_ut = 76 clck cycles D real input simulatin Pass, signal recvered after latency 35 clck cycles 4D real input simulatin Pass, signal recvered after latency 75 clck cycles 9

107 5.3. Register Transfer Level Cde Synthesis After RTL functinality verificatin, the HDL cde fr the system was synthesized using Synpsys. Synpsys synthesis tl includes features such as synthesis fr virtually any clcking scheme, autmatic cnstraint derivatin, embedded pint-tpint timing analysis, and industry-supprted links t layut. Sectin 4.5 intrduced sme infrmatin f the synthesis. As a cre f Synpsys synthesis tl, design cmpiler ptimizes lgic designs fr speed, area, and rutability. In the TCM cdec synthesis prcess, this ptimizatin was perfrmed fr hierarchical cmbinatinal r sequential circuit design descriptins. The design cmpiler synthesized the circuit and put it in the TSMC.8µm CMOS technlgy. Table 5.3 shws the physical results f the chip tp mdule synthesis befre scan insertin. Table 5.3 Synpsys synthesizes physical results f the chip Parameters Value Remark Number f prts 3 Nt including pwer and scan pins Number f nets 887 Wire Number f cells 6 Ttal lgic cell Number f references 38 Single lgic cell Ttal cell area (µm ) 337,65.35 Cmbinatinal and nn-cmbinatinal area withut ptimizatin. The synthesis area shwn in Table 5.3 is fr the cre area nly (i.e., withut cnsidering area required fr the I/O pads). This area is an estimatin result withut cnsidering ptimizatin f the cell placement and rute. The finalized chip area will be reprt in next sectin after the chip layut is generated. 93

108 Frm the synthesis timing reprt, the critical path f this cdec chip was fund in the decder blck. A critical path is the lngest path between tw shift registers. Timing f the critical path decides peratin frequency f the entire chip. A 6.9ns data arrival time was reprted after synthesis. This time indicated that the highest frequency f D TCM cdec is 44MHz and 89MHz f 4D TCM cdec withut any the I/O pad delay (i.e., I/O pad delay is extra). These perating frequencies result in a decding thrughput f.8gbps fr a 7-bit symbl sequence in the D cdec and.3gbps in the 4D cdec. Hwever, fr the current.8µm CMOS technlgy, there is a delay n the I/O pad in the rder f ns prvided in the design library; therefre the ptimal frequency f the chip will be in the range f 59MHz (D) and 74MHz (4D). Delay f the I/O pads reduces the thrughput f real chip t 47Mbps fr the D cdec and.84gbps fr the 4D cdec. This data rate is still faster than FPGA synthesis results fr the decder shwn in Table 5.. Table 5.4 prvides the cmparisn f the synthesis results between the FPGA and ASIC TCM decders. The ASIC achieves a tw fld imprvement in the decding speed. All these results are simulatin results. FPGA device used here is the Altera EPFKLC84-3. ASIC implementatin is using.8µm CMOS technlgy. The results prvided here are FPGA and CMOS technlgy dependent. Table 5.4 The synthesis results f FPGA and ASIC TCM decder TCM ASIC FPGA Decder Withut bnding pad With bnding pad EPFKLC84-3 Operatin D 44MHz 59MHz MHz frequency 4D 89MHz 74MHz 33MHz Thrughputs D.8Gbps 47Mbps 6Mbps (Bit rate) 4D.3Gbps.84Gbps 58Mbps 94

109 5.3.3 Layut Generatin After synthesis, the design is cnverted t a gate-level Verilg netlist frm the RTL cde. A Verilg test bench was written t generate data and timing in rder t run the gate-level netlist simulatin. The netlist f this chip was tested with a Verilg test bench. Simulatin results btained were the same as the results in Sectin This utcme verified functinality f the gate netlist. The successfully simulated gate-level Verilg netlist was imprted int Cadence PDP fr physical layut. The physical placement started with the creatin f a design flrplan. Creating a prper I/O flrplan is ne f the mst critical stages in the digital design prcess. At the flrplan creatin stage, pwer pads require t be added t the design. As shwn in Figure 4., a ttal f 46 Input/Output pins are required, nt including scan/bist I/O pins. After scan insertin, there are three mre I/O pins added fr scan test which are the scan test input (test_si), the scan test enable (test_se) and the scan test utput (test_s). Cnsidering VDD and VSS pins necessary t pwer the chip, 4 pairs f ring pwer pads and 4 pairs f cre pwer pads were inserted. The number f ring pwer pads is determined by a rule f thumb f ne pair f pwer ring fr every 4-6 utput pins. In additin, using the rule f thumb f ma per micrn f metal width and 4-micrn wide pwer cnnectins are used, fur pairs f cre pwer pads shuld allw fr an average flw f 6mA f current t the cre. This cmes t the ttal f 65 I/O pads required fr the chip. Since the chip area was based n the pad-limited plicy and the area granted by CMC was nt sufficient fr all these 65 pads, 6 utput pins f the encder were eliminated in the final chip lay ut fr fabricatin. At the final stage, nly 49 pins were put in the ASIC, including 3 I/O pins, 3 scan test pins and 6 pwer 95

110 pins. In the flrplanning, a default grup f cells was created. An I/O ring is cnnected by abutment and the placement sites fr all the cells are defined. After flrplanning, PDP uses frward-anntated timing infrmatin frm Synpsys synthesis t place the cre cells. This placement is ptimized. Hence the cre area f all the cells cnnectin is smaller than the ttal cell area reprted in Table 5.3. Once the cells were placed, a clck tree was created at this stage. Creating the clck tree is t add clck buffer cells and nets t create a balanced clck tree which meets timing parameters specified in the synthesis. At this pint, the PDP generated a glden netlist. The netlist was then simulated again t ensure the clck tree generatin did nt alter the netlist. This glden netlist was used as a schematic when the final layut was verified with autmatic layut-versus-schematic (LVS) at the end f the design cycle. Then the placed design was imprted int the silicn ensemble envirnment t rute the pwer, clck, and regular nets f the design. After placed and ruted, the Cadence DFII tl was used t perfrm LVS and DRC check; bth the LVS and DRC tests passed at this step. Then the GDSII frmat file was streamed ut and sent t CMC t perfrm the ARC and DRC checks. Finally, bnding pads were added t the layut. Figure 5.4 shws the chip layut befre sending t TSMC fr fabricatin. The ptimized IP cre layut dimensin is 97.43µm x 38.56µm (an area f.mm shwn in the centre f Figure 5.4). After adding bnding pads, the final chip layut has a dimensin f 59.6µm x 9.6µm (r an area f 3.3mm ). The cre area 96

111 is 33.% f the final chip (i.e., a utilizatin f 33%). Mst f the area in the layut is used fr ruting the 49 I/O and bnding pads. Ruting wire Ring Pwer Pad Cre Pwer Pad Cre Area Bnding pad Lg (metal 6) I/O pad Figure 5.4 Final layut f the TCM cdec ASIC 97

112 5.4 The Fabricated TCM Cdec Figure 5.5 is a micrgraph f the fabricated ASIC received frm CMC. This phtgraph was taken frm a die. The picture shws the structure is similar t the final layut in Figure 5.4. Ruting wire Ring Pwer Pad Cre Pwer Pad Bnding pad Cre Area Lg (metal 6) Figure 5.5 Phtgraph f the TCM cdec chip with bnding pads 98

113 The fabricated TCM cdec ASIC was packaged using the standard 68CPGA package. The 68CPGA package has 68 pins with thrugh hle pin type. The cavity size is 8.89mm x 8.89mm r 35mils x 35mils. Figure 5.6 shws the 68CPGA-bnding diagram and pin ut diagram. The third empty circle in the bttm view left tp crner indicates pin # lcatin DIE BOTTOM VIEW Bnding diagram Pin ut diagram (bttm view) Figure CPGA pin bnding and pin ut diagram 5.5 Testing Results Functinal testing aimed t determine the ASIC functinality which includes pwer-up self-test (i.e., t verify the chip is wrking using BIST), decder functin test and encder/decder functin tests. These tests were perfrmed in the lwer clck rates (less than MHz). The tests were set up using an FPGA and varius testing equipment. Figure 5.7 shws the test set-ups. The FPGA generated data and signals required t perate the ASIC. The adaptr was used t cnvert the TTL utputs frm the FPGA (i.e., 5V) t the 3.3V inputs f the ASIC. A lgic analyzer was used t capture the input 99

114 and utput wavefrms. Pwer cnsumptin was measured t determine the ASIC pwer requirement. The average pwer cnsumptin was 9.8µW when cnnected t a 3.3V pwer supply. Hwever, this measurement des nt indicate the actual pwer cnsumptin because the faster the device run, the mre pwer it draws. +5V +3.3V +3.3V sys_clk sys_clk sys_rst sys_rst FPGA Adapter ASIC data data 6 6 GND 9 Lgic Analyzer Figure 5.7 Functinal test set-ups The FPGA was used t generate the clck and reset signal fr the ASIC. A 6- bit cunter implemented in the FPGA was used t generate the data sequence. The data sequence was recvered frm the utput f the ASIC. This indicated that the data sequence g thrugh the encder and the decder; the data was encded and then decded crrectly by the cdec. Unfrtunately, at higher frequency, the utput f the cdec was nt stable. In additin, the BIST was nt passed when the chip was pwered up and the switches were set prperly fr the built-in self-test. Figure 5.8 and Figure 5.9 shw the signal wavefrms captured by the lgic analyzer. The wavefrms shw the results fr bth D and 4D functinal testing when using the input data sequence generated by the FPGA.

115 Clck Input Output Figure 5.8 Functinal testing fr D scheme Clck Input Output Figure 5.9 Functinal testing fr 4D scheme The functinal testing f the ASIC was perfrmed at a 3.5MHz clck. Because f the stability prblem f the testing results, the chip culd nt be tested fully t prvide timing results. The high frequency testing was nt perfrmed successfully at this time.