II. OPERATIONAL PRINCIPLES The operational principles of flyback converter with RCD snubber are discussed in this section. Fig.

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1 中華民國第三十一屆電力工程研討會台灣台南 年 月 3-4 日 Vltage-Lp Cmpensatr esign fr Cnstant On-ime Cntrl Based Flyback Cnverter with RC Snubber Jia-Ci Liu and Ray-Lee Lin epartment f Electrical Engineering Natinal Cheng Kung University ainan City, AWAN syig@htmail.cm Abstract n this paper, a vltage-lp cmpensatr design fr cntrl based flyback cnverter with RC snubber is presented. n rder t reduce pwer lss during perating at light lad, the cntrl technique is applied t the prpsed circuit. Mrever, the mathematic sftware MathCA is used t cmplete the cmpensatr parameters design f the prpsed circuit fr imprving the system stability. Finally, in rder t ensure verall system stability, the simulatin sftware SMPLS is utilized t cmplete the system analysis f the flyback cnverter with RC snubber. Keywrdsflyback; RC snubber; cmpensatr design; cnstant n-time cntrl. 摘要本文主旨為設計一具 RC 緩衝器之返馳式電路的電壓迴路補償器 為了降低在輕載的損失, 恆定開關導通時間控制法被用於此電路 接著, 利用 MathCA 數學軟體設計補償器以改善系統穩定度 最後, 利用電路模擬軟體 SMPLS 驗證系統穩定度 關鍵字 返馳式轉換器 RC 緩衝器 補償器 恆定開關導通時間控制. NROUCON he cnventinal flyback cnverter has been widely used in industry applicatins. he majr advantages include unnecessarily extra utput filter, less elements requirement, lw cst, and high pwer density. Hwever, the cnventinal flyback cnverter has sme prblems, such as high-vltage spike n the switch and lw cnversin efficiency. n rder t imprve the drawbacks, the RC snubber [4-6] and cntrl techniques are applied t cnventinal flyback cnverter fr reducing the high-vltage spike n the switch and imprving the cnversin efficiency, as shwn in Fig.. N S Vs One sht VCO Vc key wavefrms f the prpsed circuit perating in cntinuus cnductin mde (CCM) withut any equivalent series resistance (ESR) and parasitical elements. Hwever, the primary leakage inductr (L r ) f islated transfrmer is cnsidered in the peratinal principles fr discussing the high-vltage spike n the pwer switch [7-]. One switching cycle includes three peratinal mdes, and each mde will be explained in detail as fllws. V g / V i / A i C / A V / V V C / V V / V V s / V t 3 t t t Fig.. he key wavefrms f the prpsed circuit. Mde (t - t ) n the duratin between t and t, the switch S is turned n. he input vltage V in prvides energy t the magnetizing inductr L m. herefre, the magnetizing inductr current i increases linearly. Mrever, the switching vltage V s is less than snubber capacitr vltage V. hus, the snubber dide s is turned ff, and the snubber capacitr current flws int the energy t snubber resistr. At the same time, the utput energy is delivered by utput capacitr C. V N Fig.. he prpsed circuit with Cnstant n-time cntrl.. OPERAONAL PRNCPLES he peratinal principles f flyback cnverter with RC snubber are discussed in this sectin. Fig. shws the S VS S Vg Fig. 3. Circuit diagram during Mde. 94

2 中華民國第三十一屆電力工程研討會台灣台南 年 月 3-4 日 Mde (t t ) n the duratin between t and t, the switch S is turned ff. he switch vltage V s is higher than the vltage f RC snubber. hus, the RC snubber dide s is cnducting. herefre, the current still flws thrugh the magnetizing inductr, the primary leakage f transfrmer, snubber dide, and snubber capacitr. he energy f primary leakage inductr f transfrmer is delivered t RC snubber capacitr. hus, the peak vltage pulse f the switch is reduced. V Vg S VS N Fig. 4. Circuit diagram during Mde. Mde 3 (t t 3 ) n the duratin between t and t 3, the switch S is still turned ff. he energy f magnetizing inductr L m is delivered t secndary f pwer transfrmer. At the same time, the secndary dide is cnducting. Mrever, the energy f pwer transfrmer is transferred t utput capacitr and lad. At this mment, the vltage f switch is less than snubber capacitr vltage C s. hus, the snubber dide s is turned ff, and the energy f snubber capacitr C s is cnsumed by snubber resistr R s. V Vg S VS N l lc l Fig. 5. Circuit diagram during Mde 3.. ESGN GUELNES he ideal frmulas f flyback cnverter with RC snubber are discussed in this sectin. he flyback cnverter with RC snubber perates in cntinuus cnductin mde (CCM) withut any equivalent series resistance (ESR) and parasitical elements. n rder t calculate the ideal frmulas fr the flyback cnverter with RC snubber, the vltage-secnd balance, ampere-secnd balance and law f cnservatin f energy are used. (a) Vltage Cnversin Rati When the switch S is turned n, the magnetizing inductr vltage V is equal t the input vltage V in by btaining in Figure 3, as shwn in Equatin (). V V in () When the switch S is turned ff, the magnetizing inductr vltage V is btained in Fig., as shwn in Equatin (). V V N () he relatinship between input vltage V in and utput vltage V is presented by vltage-secnd balance, as shwn in Equatin (3). Using the Equatin (3), the equatin is derived as shwn in the Equatin (4). s V ( ) s N (3) N V in s V ( ) s N (4) Accrding t the Equatin (4), the vltage cnversin rati f the prpsed circuit is derived as shwn in the Equatin (5). V N (5) (b) Maximum, Minimum and Average Values f Magnetizing Current he maximum and minimum values f the magnetizing inductr current i are derived by the relatinship between magnetizing inductr vltage and magnetizing inductr, as shwn in the Equatin (6). di V L m (6) dt Accrding t the Equatin (6), the magnetizing inductr current ripple Δi is calculated, as shwn in the Equatin (7). n V i ( ) s, where n (7) N he utput current will be calculated by using the relatinship f utput vltage V, utput current, and lad resistr R, as shwn in the Equatin (8). V (8) R Accrding t the law f cnservatin f energy, the input pwer P in is equal t the utput pwer P. he input current in is derived by the Equatin (8), as shwn in the Equatin (9). V in (9) he magnetizing inductr average current,avg is derived by utput current and transfrmer turn rati, as shwn the Equatin (). N,avg () he maximum magnetizing inductr current max and minimum magnetizing inductr current min are derived frm the Equatin (7) and (), as shwn in the Equatin () and (), respectively. 94

3 中華民國第三十一屆電力工程研討會台灣台南 年 月 3-4 日,avg i () max,avg i () min (c) Bundary inductance Assuming the minimum value f magnetizing inductr current min is equal t zer, as shwn in Equatin (3). he Equatin (4) is derived frm Equatin (7) and Equatin (3). he bundary inductance is calculated frm Equatin (4), as shwn in Equatin (5).,avg i (3) n V ( ) s (4) n V ( ) s (5),avg (d) Output Vltage Ripple Percentage he utput vltage ripple ΔV is derived by using ampere-secnd balance. he psitive area between utput vltage and zer is calculated fr getting the utput vltage ripple, as shwn in the Equatin (6). he utput vltage ripple percentage is derived frm the Equatin (6), as shw in the Equatin (7). Q V s s v (6) C C R C v V s R C (7) V. OPEN-LOOP SMULAON AN ANALYSS he specificatins f the prpsed circuit are designed fr an adapter f ntebk, as listed in able. he mathematic sftware MathCA is used t cmplete the parameters design f the RC snubber and flybsack cnverter, as listed in able. able. he specificatins f prpsed circuit. Value nput vltage(v in ) 56V dc Output vltage(v ) 9V dc Rated utput pwer(p ) 65W Switching frequency(f s ) k Hz Output vltage ripple percentage(δv /V ) % able. he parameters f the prpsed circuit. Parameter Value Magnetizing inductr(l m ) 669.6μH Output capacitr(c O ) μf Snubber resistance(r s ).8kΩ Snubber capacitr(c s ) 5.6nF ransfrmer turn rati(n /N ) 4 he simulatin sftware SMPLS is used t build the simulatin circuit f flyback cnverter with RC snubber. he simulatin circuit is built fr analyzing the frequency dmain Bde diagrams, such as cntrl-t-utput, line-t-utput, input impedance, and utput impedance. he fixed-frequency PWM and varying-frequency cntrl pen-lp circuit at the same cnditins are built fr frequency dmain analysis. he Bde diagrams f cntrl-t-utput perating at full and 5% lad are shwn in Fig. 6 t Fig. 9, respectively. he values f pen-lp PWM cntrl and cntrl perating at full and 5% lad are listed in able 3 and able4, respectively. Cmpare t pen-lp cntrl t utput perating at full lad, phase margins and gain margins f PWM cntrl and cntrl are higher as perating at 5% lad (degree) Fig. 6. PWM cntrl-t-utput perating at full lad. - 5 (degree) Fig. 7. Cnstant n-time cntrl-t-utput perating at full lad. able3. Cmparisn between PWM and Cnstant n-time cntrl perating at full lad. margin() 5 margin() 5 db db Band wide() 4.8k Hz 4.3k Hz 4.3 db 4.3 db Resnant frequency(f ).653k Hz.653k Hz 4 (degree) Fig. 8. PWM cntrl-t-utput perating at 5% lad. 5 - (degree) Fig. 9. Cnstant n-time cntrl-t-utput perating at 5% lad.

4 中華民國第三十一屆電力工程研討會台灣台南 年 月 3-4 日 able4. Cmparisn between PWM cntrl and cntrl perating at 5% lad. margin() margin() 5 db 3dB Band wide() 4.8k Hz 4.4k Hz 4.7 db 4.5 db Resnant frequency(f ).653k Hz.653k Hz he line-t-utput, input impedance and utput impedance f PWM cntrl and cntrl are the same, as shwn in Fig. t Fig., respectively. he input surce nise immunity f PWM cntrl and cntrl are bserved by f line t utput. Accrding t the input impedance Bde diagrams f PWM cntrl and cntrl, the gain f input impedance is as high as pssible fr better lad matching. Using the utput impedance Bde diagrams f the PWM cntrl and the cntrl utput impedance are as small as pssible fr better lad matching. (db) Fig.. Full lad line-t-utput based n PWM cntrl and cntrl. 8 (db) 6 4 increasing the phase margin f the PWM cntrl and cntrl. he ples are set at 87.3 khz and 6.53 khz fr reducing the high frequency nise. he cmpensatr is used in PWM cntrl and cntrl (db) - fz&fz V Frequency (Hz) R3 R C R Vref C3 - C Fig.3. Cmpensatr. fp fp 5 5 (degree) Frequency (Hz) Vc fz&fz (a) (b) Fig. 4. Cmpensatr Bde diagrams. able 5. he ples and zers f cmpensatr. f z f z f p f p 43Hz 43Hz 87.3kHz 6.53kHz V. CLOSE-LOOP SMULAON AN ANALYSS he clsed- lp cntrl diagrams are shwn in Fig. 5. he cntrl diagram is cmpsed f the flyback with RC snubber, cmpensatr, vltage cntrl scillatr, and ne-sht. N Rx fp fp Fig.. Full lad input impedance based n PWM cntrl and cntrl. S One sht VCO Z - Vref Z Ry (db) Fig.. Full lad utput impedance based n PWM cntrl and cntrl. V. COMPENSAOR ESGN he utput vltage f pen-lp is impacted because the input vltage r utput current is changed. Fr imprving the verall system stability, the cmpensatr type is chsen, as shwn in Fig. 3. he cmpensatr includes an integratr, tw ples and tw zers. he high f cntrl-t-utput can reduce the steady-state errr. he zers f cmpensatr can raise the phase margin fr increasing the verall system stability. he ples f cmpensatr can raise the gain margin fr reducing the high frequency nise. he Bde diagrams f the cmpensatr are shwn in Fig. 4. he ples and zers f cmpensatr are listed in able 5. he zers f cmpensatr are chsen befre cut-ff frequency fr Fig. 5. Clsed-lp cntrl diagram. he PWM cntrl and cntrl clsed-lp circuit are built fr achieving better input vltage and lad regulatin. he Bde diagrams f clsed-lp cntrl-t-utput perating at full and 5% lad are shwn in Fig. 6 t Fig. 9, respectively. he full and 5% lad clsed-lp characteristics f PWM cntrl and cntrl are listed in able 6 and able 7. Accrding t the able 6 and able 7, the, the gain margin, and the phase margin perating at 5% lad is greater than full lad. Hwever, the bandwidth perating at full lad is greater than 5% lad (degree) Fig. 6. PWM cntrl lp gain perating at full lad.

5 中華民國第三十一屆電力工程研討會台灣台南 年 月 3-4 日 (degree) Fig. 7. Cnstant n-time cntrl lp gain perating at full lad. able 6. Cmparisns between cntrl and PWM cntrl perating at full lad. margin() margin() 3 db.85 db Band wide() 5k Hz 4.8k Hz db db Switch frequency k Hz.6k Hz (degree) Fig. 8. PWM cntrl lp gain perating at 5% lad (degree) Fig. 9. Cnstant n-time cntrl lp gain perating at 5% lad (db) Fig.. Full lad clsed-lp input impedance based n PWM cntrl and cntrl. (db) Fig.. Full lad clsed-lp utput impedance based n PWM cntrl and cntrl V. CONCLUSON his paper presents the vltage-lp cmpensatr design fr cntrl based flyback cnverter with RC snubber. he simulatin sftware SMPLS is utilized t cmplete the system analysis f the flyback cnverter with RC snubber in rder t ensure verall system stability. he steady-state errr and system stability f cntrl are greater than PWM cntrl. Hwever, the reactin speed and high frequency decay f PWM cntrl are greater than cntrl. he phase margin and gain margin f flyback with RC snubber arise in the duratin f perating at light lad. he bandwidth decreases during perating at light lad. able 7. Cmparisns between cntrl and PWM cntrl perating at 5% lad. margin() margin() 8 db 5.36 db Band wide() 5k Hz 4.8k Hz db db Resnant frequency(f ) k Hz.4k Hz Fig. t shw the line-t-utput, input impedance, and utput impedance Bde diagrams f clsed-lp PWM cntrl and cntrl, respectively. he input impedance Bde diagram f cntrl is less than PWM cntrl. Mrever, the input lading effect f PWM cntrl is less than cntrl. he utput impedance Bde diagram f PWM cntrl is less than cntrl. hus, the utput lading effect f PWM cntrl is less than cntrl. 4 (db) Fig.. Full lad clsed-lp line-t-utput based n PWM cntrl and cntrl ACKNOWLEGE his wrk was spnsred by the Natinal Science Cuncil, aiwan, under Award Numbers NSC 99--E-6-3. Als, this wrk made use f Shared Facilities supprted by the Prgram f p Universities Advancement, Ministry f Educatin, aiwan. REFERENCES [] AN848 ata Sheet, Maxim ntegrated Prducts ncrprated,. [].W. Hfsajer, J.A. Ferreira, J.. van Wyk, M.K.F. Hlm, A Planar ntegrated RC Snubber/Vltage Clamp, in Prceedings f EEE AS995, vl., Sept-Oct. 995, pp [3] S. J. Finney, B. W. Williams,. C. Green, RC snubber revisited, EEE rans. ndustry Applicatins, 3 (996) [4] A. Hren, J. Krelic, M. Milanvic, RC-RC clamp circuit fr ringing lsses reductin in a flyback cnverter, EEE rans. Circuits and systems - Express briefs, 53 (6) [5] W. Mcmurray, Selectin f snubbers and clamps t ptimize the design f transistr switching cnverters, EEE ransactin n nd. Applicatin, vl. A-6, pp , July-Avg. 98. [6] M. Milanvic, J. Krelic, A. Hren, F. Mihalic, P. Slibar, he RC-RC clamp circuit fr fly-back cnverter, in Prceedings f ndustrial Electrnics, vl., June 5, pp [7] S. Y. Lin, C. L. Chen, Analysis and design fr RC clamped snubber used in utput rectifier f phase-shift full-bridge ZVS cnverters. EEE rans. ndustrial Electrnics, 45 (998)