Current Mirrors and Biasing Prof. Ali M. Niknejad Prof. Rikky Muller

Transcription

1 EECS 105 Spring 2017, Modue 4 Current Mirrors and Biasing Prof. Ai M. Niknejad Department of EECS

2 Announcements HW9 due on Friday 2

3 Load Impedance 3 Courtesy M.H. Perrott

4 Issue: Headroom Limitations 4 Courtesy M.H. Perrott

5 Achieving High Gain 5 Courtesy M.H. Perrott

6 Diode Connected Device How do we buid current sources? Let s start with a diode connected device A MOS device with gate and drain shorted operates ike a diode (but not exponentia) 6

7 Diode Connected -- SS Mode We can derive the sma-signa mode by shorting out the hybrid-pi mode Note that a Gm generator with it s controing terminas connected to the Gm is more simpy a? 7

8 The Integrated Current Mirror High Res Low Resis M 1 and M 2 have the same V GS If we negect CLM (λ=0), then the drain currents are equa Since λ is sma, the currents wi neary mirror one another even if V out is not equa to V GS1 We say that the current I REF is mirrored into i OUT Notice that the mirror works for sma and arge signas! 8

9 Mutipication Ratio I IN = k W 1 L 1 (V GS1 V T ) 2 I OUT = k W 2 L 2 (V GS 2 V T ) 2 V GS1 =V GS 2 I OUT = k W 2 L 2 (V GS 2 V T ) 2 = I IN W 2 / L 2 W 1 / L 1 = NI IN 9

10 Current Mirror as Current Source 10 The output current of M 2 is ony weaky dependent on v OUT due to high output resistance of FET M2 acts ike a current source to the rest of the circuit For good current source behavior, what is the minimum v OUT?

11 Sma-Signa Resistance of I-Source 11

12 Improved Current Sources Goa: increase R o(ut) Approach: ook at ampifier output resistance resuts to see topoogies that boost resistance R out >> r o Looks ike the output impedance of a commonsource ampifier with source degeneration 12

13 Effect of Source Degeneration v = ( i g v ) r + v t t m gs o R S R eq 1 g m v v v gs R S R t S S = ir v = ( i + g R i ) r + ir t t m S t o t S v R = + g R r ( 1 ) t o m S o it 13 Equivaent resistance oading gate is dominated by the diode resistance assume this is a sma impedance Output impedance is boosted by factor ( 1+ gmrs)

14 Improved Current Sources How woud you scae the output current? I IN = k W 1 L 1 (V G V S V T ) 2 V S = I IN R S 14

15 Cascode (or Stacked) Current Source Insight: V GS2 = constant AND V DS2 = constant Sma-Signa Resistance R o : ( 1 ) R + g R r o m S o ( 1 ) R + g r r o m o o R g r >> r 2 o m 0 o 15

16 Drawback of Cascode I-Source What is the minimum output votage to keep a transistors in saturation? 16

17 Drawback of Cascode I-Source Minimum output votage to keep both transistors in saturation: i OUT V = V + V OUT, MIN DS 4, MIN DS 2, MIN V > V V = V DS 2, MIN GS 2 T 0 DSAT 2 V > V + V = V + V V D4 DSAT2 GS4 GS2 GS4 T0 17 V = V + V V OUT, MIN GS 2 GS 4 T 0 v OUT In EE140 we wi earn circuit tricks to overcome this probem!

18 Current Sinks and Sources Sink: output current goes to ground Source: output current comes from votage suppy 18

19 Current Mirrors Idea: we ony need one reference current to set up a the current sources and sinks needed for a mutistage ampifier. 19

20 Exampe: Common-Drain Ampifier W 1 ( ) 2 IDS = µ Cox VGS VT L 2 v in 20

21 Common Drain AC Schematic How does a REAL current source fit in to the sma-signa mode? v in 21

22 CD Votage Gain With Rea I-Source v in 22 Idea I-Source v out R L r o = g m v gs v out R L r o = g m ( v in v out ) R L Rea I-Source

23 CD Votage Gain (Cont.) KCL at source node: Votage gain: 23

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