Multi-stage Amplifiers Prof. Ali M. Niknejad Prof. Rikky Muller

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1 EECS 105 Spring 2017, Modue 4 Muti-stage Ampifiers Prof. Ai M. Niknejad Department of EECS

2 Announcements HW10 due on Friday Lab 5 due this week 2 weeks of ecture eft! 2

3 Mutistage Ampifiers Why cascade singe-stage ampifier stages? More gain! Gain/stage imited, especiay in nanoscae devices Input/output resistance matching Source/oad impedance may be too high/ow Improve Bandwidth De-coupe high impedance nodes from arge capacitors Output stages to drive externa oads 3 DC couping (no passive eements to bock the signa) Use ampifiers to naturay eve shift signa

4 1-Stage Ampifier Types 4 Courtesy M.H. Perrott

5 Transistor Ampifiers à Gm/V/I Gm Ampifier Common Source I-Buffer Common Gate V-Buffer Source Foower 5

6 Impedance Match On-chip circuits often use votage/current matching to minimize oading Keep in mind the input resistance and output resistance of each type of stage so that the oading does not create an undesired effect Votage: Current: Transconductance: Transresistance: R in R out

7 Two-Stage Votage Ampifier Boost gain by cascading Common-Source stages CS 1 CS 2 CS 1,2 Can combine into a singe 2-port mode Resuts of new 2-port: R in = R in1, R out = R out2 7

8 CS Cascade Anaysis v in g m1 v in v int g m2 v int v out Resuts of new 2-port: R in = R in1 = R out = R out2 = A V = v out /v in = 8

9 CS Cascade Bandwidth v in g m1 v in v int g m2 v int v out 9 Two time constants: τ 1 = τ 2 =

10 Bandwidth Extension Common Source stage has high gain, but ow bandwidth Note that Mier effect is the cuprit Foower stage can buffer source resistance from Mier cap 10

11 Bandwidth Extension Using SF COMMON SOURCE COMMON DRAIN COMMON SOURCE v in g m1 v in v v int g out m2 v int 11

12 CS Exampe with Cap Load 12 C in and C S are very arge, therefore they ook ike short circuits to the AC signa. If C L is very arge, its poe dominates, et s anayze

13 CS with Cap Load Sma Signa R d R 2 //R g1 //R g2 ~R 2 13 What are the time constants associated with the capacitors in this circuit? What can we do if we have to drive a arge C L?

14 CS with Cap Load Bandwidth 14 How can we reduce the impact of C L? One way is to reduce the resistance R d, but this reduces our ow-frequency gain To recover the gain we can increase g m1. What does this cost us?

15 CS with Cap Load BW Extension 15 A better way to extend the bandwidth is to add a source-foower stage. Simiar to previous exampe

16 CS with Cap Load BW Extension 1/g m2 v in g m1 v in v int v int By adding a CD (Source Foower) we can increase the bandwidth It costs us power for the CD stage Remember that increasing the BW by increasing g m1 costs us much more 16

17 CS + CG Common source provides gain, CG acts as a buffer, but is it even heping? How do you bias this circuit? 17

18 Merged CS + CG = Cascode Let s appy 2-port sma-signa anaysis v out v int In this case, we care about the input current to the second stage Note that the input resistance of the CG is ow, therefore the majority of the CS current is fed to the CG A v = 18

19 Cascode Bandwidth Draw in the C gs and C gd capacitors. Which ones are Mier effected? Is this better or worse than a CS without a CG? 19

20 Cascode Bandwidth Draw in the capacitors and input resistance v out v int 20

21 Cascode Biasing CG has a very arge output resistance Loading it with R D is ikey to reduce the votage gain We can increase the gain by using a current source oad, but r oc needs to be very arge. Can use a cascode current mirror! 21

22 Compete Ampifier Design Goas: g m1 = 1 ms, R out =5 MΩ For simpicity, et s assume a g m and r o vaues are equa A V g m1 R out = 1mS * 5MΩ = 5, 000 R out 1 2 g m r o2 = 5MΩ r o = 20MΩ = 10MΩ g m 1mS =100kΩ 22

23 Bias Current & Device Sizing Need to know process parameters to sove for W/L k = 100 µa/v 2 λ = 0.1 [V -1 ] r o = 1 λi DS =100kΩ I DS = g m = W L = 1.1V 1 *100kΩ =100µA 2k ' W L g 2 m = 2k 'I DS I DS =1mS (1mS) 2 2 *100µ *100µA = 50 23

24 Output (Votage) Swing Need to know V GS V T (eg. V DSAT, V OV ) g m = 2I DS V GS V T =1mS V GS V T = 2I DS g m = 2 *100µA 1mS = 0.2V 24 Maximum V OUT = Minimum V OUT = Input Bias V IN =

25 Anaysis Exampe 25

26 Cutting Through the Compexity 1. Identify the signa path between the input and output 2. Eiminate background transistors to reduce cutter 3. For background transistors, understand their roe (e.g. DC biasing) 4. For frequency response, identify hi-z nodes. 26

27 Eiminate Cutter 27

28 Identify Signa Path & Ampifier Stages V B3 V B2 V B1 28

29 DC Biasing V B3 V B2 V B1 29

30 Sma-Signa Modes r o1 r o4 30

31 Two-Port Mode 31

32 Externa Loads Many appications must drive externa oads that are very ow impedance compared to on-chip eves These stages must drive high votages/currents so inearity is a concert. We must consider arge signa behavior Exampe: Speaker at 8 ohms versus Megaohms onchip Foower is natura choice, but it can ony source current (think in terms of arge signas) 32

33 Design Issue: DC Couping Constraint: arge inductors and capacitors are not avaiabe Output of one stage is directy connected to the input of the next stage à must consider DC eves why? 33