Lecture 29: Diode connected devices, mirrors, cascode connections. Context

Size: px
Start display at page:

Download "Lecture 29: Diode connected devices, mirrors, cascode connections. Context"

Transcription

1 Lecture 9: Diode coected devices, mirrors, cascode coectios Prof J. S. Smith Cotext Today we will be lookig at more sigle trasistor active circuits ad example problems, ad the startig multi-stage amplifiers 1

2 Lecture Outlie Summary of sigle-trasistor amplifiers Diode coected MOSFETs Curret Mirrors Biasig Schemes Sigle Stage Amplifiers Commo-source is the oly stage that provides both curret ad voltage gai Miller effect limits high frequecy respose Commo-drai ca buffer a poor voltage source ito a very good voltage source oe Commo-gate ca buffer a poor curret source ito a very good curret source, or replicate a curret source ito may curret sources (curret mirror)

3 NMOS pullup Rather tha usig a big (ad expesive) resistor, let s look at a NMOS trasistor as a active pullup +V device v out Note that whe the trasistor is coected this way, it is ot a amplifier, it is a two termial device. Whe the gate is coected to the drai of this NMOS device, it will be i saturatio, so we get the equatio for the drai curret: I D W = µ C SG T 1 + L ( V V ) ( λ V ) SD Small sigal model So we have: The N chael MOSFET s trascoductace is: Ad so the small sigal model for this device will be a resistor with a resistace: W I D = µ C L W = µ C L SG ( V V ) ( 1 + λ V ) SG W L ( V V ) ( 1 + λ V ) µ C ( V V ) T W W g m = D µ SG T µ v L L T ( i ) = C ( V V ) C ( I ) Q SD 1 r = g m D T 3

4 IV for NMOS pull-up The I-V characteristic of this pull-up device: I W = µ C L ( V V ) D1 DD T I ( V ) DD V t V V DD Active Load We ca use this as the pullup device for a NMOS commo source amplifier: V DD W 1 I ( ) D1 = C V gs1 VT1 L µ 1 M I D W = L µ C ( V V ) gs T + v i M 1 + v out V V 0 = V DD V 0 gs = V DD V t I µ C ( W / L ) 4

5 Active Load Sice I =I 1 we have: V DD V 0 = V DD V t I1 µ C ( W / L ) M Ad sice: V = V gs1 i + v i M 1 + v out V 0 = V DD V t1 ( W1 / L1 ) ( ) ( V ) i Vt1 W / L Behavior If the output voltage goes higher tha oe threshold below VDD, trasistor goes ito cutoff ad the amplifier will clip. If the output goes too low, the trasistor 1 will fall out of the saturatio mode. Withi these limitatios, this stage gives a good liear amplificatio. 5

6 CMOS Diode Coected Trasistor Short gate/drai of a trasistor ad pass curret through it Sice VGS = VDS, the device is i saturatio sice VDS > VGS-VT Sice FET is a square-law (or weaker) device, the I-V curve is very soft compared to PN juctio diode Diode Equivalet Circuit R D di dv OUT = 0 1 OUT = = R OUT D I 1 g m vt i t Equivalet Circuit: R D i OUT V D v OUT - 6

7 The Itegrated Curret Mirror High Res Low Resis M 1 ad M have the same V GS If we eglect CLM (λ=0), the the drai currets are equal Sice λ is small, the currets will early mirror oe aother eve if V out is ot equal to V GS1 We say that the curret I REF is mirrored ito i OUT Notice that the mirror works for small ad large sigals! Curret Mirror as Curret Source The output curret of M is oly weakly depedet o v OUT due to high output resistace of FET M acts like a curret source to the rest of the circuit 7

8 Small-Sigal Resistace of I-Source Improved Curret Sources Goal: icrease r oc Approach: look at amplifier output resistace results to see topologies that boost resistace R out >> r o Looks like the output impedace of a commosource amplifier with source degeeratio 8

9 Effect of Source Degeeratio R eq 1 g m ( 1 ) t o m S o it v = ( i g v ) r + v t t m gs o R S gs R S Equivalet resistace loadig gate is domiated by the diode resistace assume this is a small impedace Output impedace is boosted by factor ( 1+ gmrs) v v v = ir RS t S vt = ( it + gmrsit) ro + ir t S v R = + g R r Cascode (or Stacked) Curret Source Isight: V GS = costat AND V DS = costat Small-Sigal Resistace r oc : ( 1 ) R + g R r o m S o ( 1 ) R + g r r o m o o R g r >> r o m 0 o 9

10 Drawback of Cascode I-Source Miimum output voltage to keep both trasistors i saturatio: V = V + V i OUT OUT, MIN DS 4, MIN DS, MIN V > V V = V DS, MIN GS T0 DSAT V > V + V = V + V V D4 DSAT GS 4 GS GS 4 T 0 V = V + V V OUT, MIN GS GS 4 T 0 v OUT Curret Siks ad Sources Sik: output curret goes to groud Source: output curret comes from voltage supply 10

11 Curret Mirrors Idea: we oly eed oe referece curret to set up all the curret sources ad siks eeded for a multistage amplifier. The Itegrated Curret Mirror High Res Low Resis M 1 ad M have the same V GS If we eglect CLM (λ=0), the the drai currets are equal Sice λ is small, the currets will early mirror oe aother eve if V out is ot equal to V GS1 We say that the curret I REF is mirrored ito i OUT Notice that the mirror works for small ad large sigals! 11

12 Curret Mirror as Curret Source The output curret of M is oly weakly depedet o v OUT due to high output resistace of FET M acts like a curret source to the rest of the circuit Small-Sigal Resistace of I-Source 1

13 Improved Curret Sources Goal: icrease r oc Approach: look at amplifier output resistace results to see topologies that boost resistace R out >> r o Looks like the output impedace of a commosource amplifier with source degeeratio Effect of Source Degeeratio R eq 1 g m ( 1 ) t o m S o it v = ( i g v ) r + v t t m gs o R S gs R S Equivalet resistace loadig gate is domiated by the diode resistace assume this is a small impedace Output impedace is boosted by factor ( 1+ gmrs) v v v = ir RS t S vt = ( it + gmrsit) ro + ir t S v R = + g R r 13

14 Cascode (or Stacked) Curret Source Isight: V GS = costat AND V DS = costat Small-Sigal Resistace r oc : ( 1 ) R + g R r o m S o ( 1 ) R + g r r o m o o R g r >> r o m 0 o Drawback of Cascode I-Source Miimum output voltage to keep both trasistors i saturatio: V = V + V i OUT OUT, MIN DS 4, MIN DS, MIN V > V V = V DS, MIN GS T0 DSAT V > V + V = V + V V D4 DSAT GS 4 GS GS 4 T 0 V = V + V V OUT, MIN GS GS 4 T 0 v OUT 14

15 Curret Siks ad Sources Sik: output curret goes to groud Source: output curret comes from voltage supply Curret Mirrors Idea: we oly eed oe referece curret to set up all the curret sources ad siks eeded for a multistage amplifier. 15

Lecture 21: Voltage/Current Buffer Freq Response

Lecture 21: Voltage/Current Buffer Freq Response Lecture 21: Voltage/Current Buffer Freq Response Prof. Niknejad Lecture Outline Last Time: Frequency Response of Voltage Buffer Frequency Response of Current Buffer Current Mirrors Biasing Schemes Detailed

More information

Lecture 28: MOSFET as an Amplifier. Small-Signal Equivalent Circuit Models.

Lecture 28: MOSFET as an Amplifier. Small-Signal Equivalent Circuit Models. hites, EE 320 ecture 28 Page 1 of 7 ecture 28: MOSFET as a Amplifier. Small-Sigal Equivalet Circuit Models. As with the BJT, we ca use MOSFETs as AC small-sigal amplifiers. A example is the so-called coceptual

More information

(2) The MOSFET. Review of. Learning Outcome. (Metal-Oxide-Semiconductor Field Effect Transistor) 2.0) Field Effect Transistor (FET)

(2) The MOSFET. Review of. Learning Outcome. (Metal-Oxide-Semiconductor Field Effect Transistor) 2.0) Field Effect Transistor (FET) EEEB73 Electroics Aalysis & esig II () Review of The MOSFET (Metal-Oxide-Semicoductor Field Effect Trasistor) Referece: Neame, Chapter 3 ad Chapter 4 Learig Outcome Able to describe ad use the followig:

More information

Lab 2: Common Source Amplifier.

Lab 2: Common Source Amplifier. epartet of Electrical ad Coputer Egieerig Fall 1 Lab : Coo Source plifier. 1. OBJECTIVES Study ad characterize Coo Source aplifier: Bias CS ap usig MOSFET curret irror; Measure gai of CS ap with resistive

More information

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on April 26, 2018 at 7:00 PM

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on April 26, 2018 at 7:00 PM Departmet of Electrical ad omputer Egieerig, orell Uiersity EE 350: Microelectroics Sprig 08 Homework 0 Due o April 6, 08 at 7:00 PM Suggested Readigs: a) Lecture otes Importat Notes: ) MAKE SURE THAT

More information

Lecture 29: MOSFET Small-Signal Amplifier Examples.

Lecture 29: MOSFET Small-Signal Amplifier Examples. Whites, EE 30 Lecture 9 Page 1 of 8 Lecture 9: MOSFET Small-Sigal Amplifier Examples. We will illustrate the aalysis of small-sigal MOSFET amplifiers through two examples i this lecture. Example N9.1 (text

More information

ELEC 350 Electronics I Fall 2014

ELEC 350 Electronics I Fall 2014 ELEC 350 Electroics I Fall 04 Fial Exam Geeral Iformatio Rough breakdow of topic coverage: 0-5% JT fudametals ad regios of operatio 0-40% MOSFET fudametals biasig ad small-sigal modelig 0-5% iodes (p-juctio

More information

After completing this chapter you will learn

After completing this chapter you will learn CHAPTER 7 Trasistor Amplifiers Microelectroic Circuits, Seeth Editio Sedra/Smith Copyright 015 by Oxford Uiersity Press After completig this chapter you will lear 1. How to use MOSFET as amplifier. How

More information

Summary of pn-junction (Lec )

Summary of pn-junction (Lec ) Lecture #12 OUTLNE iode aalysis ad applicatios cotiued The MOSFET The MOSFET as a cotrolled resistor Pich-off ad curret saturatio Chael-legth modulatio Velocity saturatio i a short-chael MOSFET Readig

More information

R. W. Erickson. Department of Electrical, Computer, and Energy Engineering University of Colorado, Boulder

R. W. Erickson. Department of Electrical, Computer, and Energy Engineering University of Colorado, Boulder R. W. Erickso Departmet of Electrical, Computer, ad Eergy Egieerig Uiversity of Colorado, Boulder 4.2.2. The Power MOSFET Gate Source Gate legths approachig oe micro p - p Cosists of may small ehacemetmode

More information

Thermal nodes Input1 2 o-- ---O Input2 3 o O Junction Temp o

Thermal nodes Input1 2 o-- ---O Input2 3 o O Junction Temp o CMOS NAND Gate with Juctio temperature moscadt CMOS NAND Gate with Juctio temperature Vdd 1 o *-------------------------* ----+ ---+ Thermal odes Iput1 o-----o Iput 3 o-------o Juctio Temp ----+ ---+ 6

More information

Current Mirrors and Biasing Prof. Ali M. Niknejad Prof. Rikky Muller

Current Mirrors and Biasing Prof. Ali M. Niknejad Prof. Rikky Muller EECS 105 Spring 2017, Modue 4 Current Mirrors and Biasing Prof. Ai M. Niknejad Department of EECS Announcements HW9 due on Friday 2 Load Impedance 3 Courtesy M.H. Perrott Issue: Headroom Limitations 4

More information

Lecture 33: Context. Prof. J. S. Smith

Lecture 33: Context. Prof. J. S. Smith Lecture 33: Prof J. S. Smith Context We are continuing to review some of the building blocks for multi-stage amplifiers, including current sources and cascode connected devices, and we will also look at

More information

SEE 3263: ELECTRONIC SYSTEMS

SEE 3263: ELECTRONIC SYSTEMS SEE 3263: ELECTRONIC SYSTEMS Chapter 5: Thyristors 1 THYRISTORS Thyristors are devices costructed of four semicoductor layers (pp). Four-layer devices act as either ope or closed switches; for this reaso,

More information

Analysis and Design of Analog Integrated Circuits Lecture 8. Cascode Techniques

Analysis and Design of Analog Integrated Circuits Lecture 8. Cascode Techniques Analysis and Design of Analog Integrated Circuits Lecture 8 Cascode Techniques Michael H. Perrott February 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Review of Large Signal Analysis

More information

HEXFET MOSFET TECHNOLOGY

HEXFET MOSFET TECHNOLOGY PD - 91555A POWER MOSFET SURFACE MOUNT (SMD-1) IRFNG40 1000V, N-CHANNEL HEXFET MOSFET TECHNOLOGY Product Summary Part Number RDS(o) ID IRFNG40 3.5Ω 3.9A HEXFET MOSFET techology is the key to Iteratioal

More information

HEXFET MOSFET TECHNOLOGY

HEXFET MOSFET TECHNOLOGY PD - 91290C POWER MOSFET THRU-HOLE (TO-257AA) IRFY340C,IRFY340CM 400V, N-CHANNEL HEXFET MOSFET TECHNOLOGY Product Summary Part Number RDS(o) ID Eyelets IRFY340C 0.55 Ω 8.7A Ceramic IRFY340CM 0.55 Ω 8.7A

More information

Lecture 34: Designing amplifiers, biasing, frequency response. Context

Lecture 34: Designing amplifiers, biasing, frequency response. Context Lecture 34: Designing amplifiers, biasing, frequency response Prof J. S. Smith Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will

More information

Applying MOSFETs in Amplifier Design. Microelectronic Circuits, 7 th Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc.

Applying MOSFETs in Amplifier Design. Microelectronic Circuits, 7 th Edition Sedra/Smith Copyright 2010 by Oxford University Press, Inc. Applyig MOSFETs i Aplifier esig Microelectroic Circuits, 7 th Editio Sedra/Sith Copyright 010 by Oxford Uiersity Press, Ic. oltage Trasfer Characteristics (TC) i 1 k ( GS t ) S i R Microelectroic Circuits,

More information

Reading. Lecture 33: Context. Lecture Outline. Chapter 9, multi-stage amplifiers. Prof. J. S. Smith

Reading. Lecture 33: Context. Lecture Outline. Chapter 9, multi-stage amplifiers. Prof. J. S. Smith eading Lecture 33: Chapter 9, multi-stage amplifiers Prof J. S. Smith Context Lecture Outline We are continuing to review some of the building blocks for multi-stage amplifiers, including current sources

More information

ECE315 / ECE515 Lecture 9 Date:

ECE315 / ECE515 Lecture 9 Date: Lecture 9 Date: 03.09.2015 Biasing in MOS Amplifier Circuits Biasing using Single Power Supply The general form of a single-supply MOSFET amplifier biasing circuit is: We typically attempt to satisfy three

More information

Revision: June 10, E Main Suite D Pullman, WA (509) Voice and Fax

Revision: June 10, E Main Suite D Pullman, WA (509) Voice and Fax 1.8.0: Ideal Oeratioal Amlifiers Revisio: Jue 10, 2010 215 E Mai Suite D Pullma, WA 99163 (509) 334 6306 Voice ad Fax Overview Oeratioal amlifiers (commoly abbreviated as o-ams) are extremely useful electroic

More information

ICM7213. One Second/One Minute Timebase Generator. Features. Description. Ordering Information. Pinout. August 1997

ICM7213. One Second/One Minute Timebase Generator. Features. Description. Ordering Information. Pinout. August 1997 August 997 Features Guarateed V Operatio Very Low Curret Cosumptio (Typ).... µa at V All Outputs TTL Compatible O Chip Oscillator Feedback Resistor Oscillator Requires Oly Exteral compoets: Fixed Capacitor,

More information

R. W. Erickson. Department of Electrical, Computer, and Energy Engineering University of Colorado, Boulder

R. W. Erickson. Department of Electrical, Computer, and Energy Engineering University of Colorado, Boulder R. W. Erickso Departmet of Electrical, Computer, ad Eergy Egieerig Uiversity of Colorado, Boulder Specific o-resistace R o as a fuctio of breakdow voltage V B Majority-carrier device: AARR #$ = kk μμ $

More information

Lecture 3. OUTLINE PN Junction Diodes (cont d) Electrostatics (cont d) I-V characteristics Reverse breakdown Small-signal model

Lecture 3. OUTLINE PN Junction Diodes (cont d) Electrostatics (cont d) I-V characteristics Reverse breakdown Small-signal model Lecture 3 AOUCEMETS HW2 is osted, due Tu 9/11 TAs will hold their office hours i 197 Cory Prof. Liu s office hours are chaged to TuTh 12-1PM i 212/567 Cory EE15 accouts ca access EECS Widows Remote eskto

More information

The Silicon Controlled Rectifier (SCR)

The Silicon Controlled Rectifier (SCR) The Silico Cotrolled Rectifier (SCR The Silico Cotrolled Rectifier, also called Thyristor, is oe of the oldest power devices, ad it is actually employed as power switch for the largest currets (several

More information

HB860H 2-phase Hybrid Servo Drive

HB860H 2-phase Hybrid Servo Drive HB860H 2-phase Hybrid Servo Drive 20-70VAC or 30-100VDC, 8.2A Peak No Tuig, Nulls loss of Sychroizatio Closed-loop, elimiates loss of sychroizatio Broader operatig rage higher torque ad higher speed Reduced

More information

Microelectronics Circuit Analysis and Design. MOS Capacitor Under Bias: Electric Field and Charge. Basic Structure of MOS Capacitor 9/2/2013

Microelectronics Circuit Analysis and Design. MOS Capacitor Under Bias: Electric Field and Charge. Basic Structure of MOS Capacitor 9/2/2013 Micrelectrics Circuit Aalysis ad Desig Dald A. Neae Chapter 3 The Field Effect Trasistr I this chapter, we will: Study ad uderstad the perati ad characteristics f the varius types f MOSFETs. Uderstad ad

More information

Lecture 14. FET Current and Voltage Sources and Current Mirrors. The Building Blocks of Analog Circuits - IV

Lecture 14. FET Current and Voltage Sources and Current Mirrors. The Building Blocks of Analog Circuits - IV Lecture 4 FET Current and oltage s and Current Mirrors The Building Blocks of Analog Circuits n this lecture you will learn: Current and voltage sources using FETs FET current mirrors Cascode current mirror

More information

INF 5460 Electronic noise Estimates and countermeasures. Lecture 11 (Mot 8) Sensors Practical examples

INF 5460 Electronic noise Estimates and countermeasures. Lecture 11 (Mot 8) Sensors Practical examples IF 5460 Electroic oise Estimates ad coutermeasures Lecture 11 (Mot 8) Sesors Practical examples Six models are preseted that "ca be geeralized to cover all types of sesors." amig: Sesor: All types Trasducer:

More information

Physical Sciences For NET & SLET Exams Of UGC-CSIR. Part B and C. Volume-16. Contents

Physical Sciences For NET & SLET Exams Of UGC-CSIR. Part B and C. Volume-16. Contents Physical cieces For NET & LET Exams Of UC-CIR Part B ad C Volume-16 Cotets VI. Electroics 1.5 Field Effect evices 1 2.1 Otoelectroic evices 51 2.2 Photo detector 63 2.3 Light-Emittig iode (LE) 73 3.1 Oeratioal

More information

ECE 2201 PRELAB 4A MOSFET SWITCHING APPLICATIONS. Digital CMOS Logic Inverter

ECE 2201 PRELAB 4A MOSFET SWITCHING APPLICATIONS. Digital CMOS Logic Inverter ECE 2201 PRELAB 4A MOSFET SWITCHING APPLICATIONS Digital CMOS Logic Iverter Had Aalysis P1. I the circuit of Fig. P41, estimate the roagatio delays t PLH ad t PHL usig the resistive switch model for each

More information

Improved Inverter: Current-Source Pull-Up. MOS Inverter with Current-Source Pull-Up. What else could be connected between the drain and V DD?

Improved Inverter: Current-Source Pull-Up. MOS Inverter with Current-Source Pull-Up. What else could be connected between the drain and V DD? Improved Inverter: Current-Source Pull-Up MOS Inverter with Current-Source Pull-Up What else could be connected between the drain and? Replace resistor with current source I SUP roc i D v IN v OUT Find

More information

Lecture 16: MOS Transistor models: Linear models, SPICE models. Context. In the last lecture, we discussed the MOS transistor, and

Lecture 16: MOS Transistor models: Linear models, SPICE models. Context. In the last lecture, we discussed the MOS transistor, and Lecture 16: MOS Transistor models: Linear models, SPICE models Context In the last lecture, we discussed the MOS transistor, and added a correction due to the changing depletion region, called the body

More information

Lecture 13. Biasing and Loading Single Stage FET Amplifiers. The Building Blocks of Analog Circuits - III

Lecture 13. Biasing and Loading Single Stage FET Amplifiers. The Building Blocks of Analog Circuits - III Lecture 3 Biasing and Loading Single Stage FET Amplifiers The Building Blocks of Analog Circuits III In this lecture you will learn: Current biasing of circuits Current sources and sinks for CS, CG, and

More information

NOISE IN A SPECTRUM ANALYZER. Carlo F.M. Carobbi and Fabio Ferrini Department of Information Engineering University of Florence, Italy

NOISE IN A SPECTRUM ANALYZER. Carlo F.M. Carobbi and Fabio Ferrini Department of Information Engineering University of Florence, Italy NOISE IN A SPECTRUM ANALYZER by Carlo.M. Carobbi ad abio errii Departet of Iforatio Egieerig Uiversity of lorece, Italy 1. OBJECTIVE The objective is to easure the oise figure of a spectru aalyzer with

More information

EECS3611 Analog Integrated Circuit Design. Lecture 3. Current Source and Current Mirror

EECS3611 Analog Integrated Circuit Design. Lecture 3. Current Source and Current Mirror EECS3611 Analog ntegrated Circuit Design Lecture 3 Current Source and Current Mirror ntroduction Before any device can be used in any application, it has to be properly biased so that small signal AC parameters

More information

Lecture 22. Circuit Design Techniques for Wireless Communications

Lecture 22. Circuit Design Techniques for Wireless Communications ecture ircuit Desig Techiques for Wireless ommuicatios this lecture you will lear: ircuits for wireless commuicatios Sigal multipliers ad mixers Sigle-balaced ad double-balaced mixers MOS F Oscillators

More information

Microelectronics Circuit Analysis and Design

Microelectronics Circuit Analysis and Design Microelectronics Circuit Analysis and Design Donald A. Neamen Chapter 3 The Field Effect Transistor Neamen Microelectronics, 4e Chapter 3-1 In this chapter, we will: Study and understand the operation

More information

A Simplified Method for Phase Noise Calculation

A Simplified Method for Phase Noise Calculation Poster: T-18 Simplified Method for Phase Noise Calculatio Massoud Tohidia, li Fotowat hmady* ad Mahmoud Kamarei Uiversity of Tehra, *Sharif Uiversity of Techology, Tehra, Ira Outlie Itroductio Prelimiary

More information

EE105 Fall 2015 Microelectronic Devices and Circuits

EE105 Fall 2015 Microelectronic Devices and Circuits EE105 Fall 2015 Microelectronic Devices and Circuits Multi-Stage Amplifiers Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of MOS Amplifiers Common

More information

4.5 Biasing in MOS Amplifier Circuits

4.5 Biasing in MOS Amplifier Circuits 4.5 Biasing in MOS Amplifier Circuits Biasing: establishing an appropriate DC operating point for the MOSFET - A fundamental step in the design of a MOSFET amplifier circuit An appropriate DC operating

More information

RAD-Hard HEXFET SURFACE MOUNT (LCC-28)

RAD-Hard HEXFET SURFACE MOUNT (LCC-28) IRHQ567 RADIATION HARDENED V, Combiatio 2N-2P-CHANNEL POWER MOSFET RAD-Hard HEXFET SURFACE MOUNT (LCC-28) 5 PD-9457D TECHNOLOGY Product Summary Part Number Radiatio Level RDS(o) ID CHANNEL IRHQ567 K Rads

More information

IRHF57230SE. Absolute Maximum Ratings

IRHF57230SE. Absolute Maximum Ratings PD-93857C RADIATION HARDENED POWER MOSFET THRU-HOLE ( TO-39) Product Summary Part Number Radiatio Level RDS(o) ID QPL Part Number IRHF57230SE K Rads (Si) 0.24Ω 6.7A JANSR2N7498T2 IRHF57230SE JANSR2N7498T2

More information

D n ox GS THN DS GS THN DS GS THN. D n ox GS THN DS GS THN DS GS THN

D n ox GS THN DS GS THN DS GS THN. D n ox GS THN DS GS THN DS GS THN Name: EXAM #3 Closed book, closed notes. Calculators may be used for numeric computations only. All work is to be your own - show your work for maximum partial credit. Data: Use the following data in all

More information

RAD Hard HEXFET TECHNOLOGY

RAD Hard HEXFET TECHNOLOGY PD-9889E RADIATION HARDENED POWER MOSFET THRU-HOLE (TO-254AA) IRHM915 JANSR2N7422 V, P-CHANNEL REF: MIL-PRF-195/662 RAD Hard HEXFET TECHNOLOGY Product Summary Part Number Radiatio Level RDS(o) ID QPL Part

More information

Measurement of Equivalent Input Distortion AN 20

Measurement of Equivalent Input Distortion AN 20 Measuremet of Equivalet Iput Distortio AN 2 Applicatio Note to the R&D SYSTEM Traditioal measuremets of harmoic distortio performed o loudspeakers reveal ot oly the symptoms of the oliearities but also

More information

Components. Magnetics. Capacitors. Power semiconductors. Core and copper losses Core materials

Components. Magnetics. Capacitors. Power semiconductors. Core and copper losses Core materials Compoets Magetics Core ad copper losses Core materials Capacitors Equivalet series resistace ad iductace Capacitor types Power semicoductors Diodes MOSFETs IGBTs Power Electroics Laboratory Uiversity of

More information

IRHE9130 JANSR2N7389U 100V, P-CHANNEL REF: MIL-PRF-19500/630 RAD-Hard HEXFET MOSFET TECHNOLOGY RADIATION HARDENED POWER MOSFET SURFACE MOUNT (LCC-18)

IRHE9130 JANSR2N7389U 100V, P-CHANNEL REF: MIL-PRF-19500/630 RAD-Hard HEXFET MOSFET TECHNOLOGY RADIATION HARDENED POWER MOSFET SURFACE MOUNT (LCC-18) PD-9088D RADIATION HARDENED POWER MOSFET SURFACE MOUNT (LCC-8) IRHE930 JANSR2N7389U 00V, P-CHANNEL REF: MIL-PRF-9500/630 RAD-Hard HEXFET MOSFET TECHNOLOGY Product Summary Part Number Radiatio Level RDS(o)

More information

IRHM7450 JANSR2N V, N-CHANNEL REF: MIL-PRF-19500/603 RAD-Hard HEXFET TECHNOLOGY RADIATION HARDENED POWER MOSFET THRU-HOLE (TO-254AA)

IRHM7450 JANSR2N V, N-CHANNEL REF: MIL-PRF-19500/603 RAD-Hard HEXFET TECHNOLOGY RADIATION HARDENED POWER MOSFET THRU-HOLE (TO-254AA) PD - 90673B RADIATION HARDENED POWER MOSFET THRU-HOLE (TO-254AA) IRHM7450 JANSR2N7270 500V, N-CHANNEL REF: MIL-PRF-19500/603 RAD-Hard HEXFET TECHNOLOGY Product Summary Part Number Radiatio Level RDS(o)

More information

Basic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair,

Basic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, Basic Circuits Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, CCS - Basic Circuits P. Fischer, ZITI, Uni Heidelberg, Seite 1 Reminder: Effect of Transistor Sizes Very crude classification:

More information

A 5th order video band elliptic filter topology using OTRA based Fleischer Tow Biquad with MOS-C Realization

A 5th order video band elliptic filter topology using OTRA based Fleischer Tow Biquad with MOS-C Realization Natural ad Egieerig Scieces 44 olume 1, No. 2, 44-52, 2016 A 5th order video bad elliptic filter topology usig OTA based Fleischer Tow Biquad with MOS-C ealiatio Ahmet Gökçe 1*, Uğur Çam 2 1 Faculty of

More information

REF: MIL-PRF-19500/662 RAD Hard HEXFET TECHNOLOGY

REF: MIL-PRF-19500/662 RAD Hard HEXFET TECHNOLOGY PD-913E RADIATION HARDENED POWER MOSFET SURFACE MOUNT (SMD-1) IRHN925 JANSR2N7423U 2V, P-CHANNEL REF: MIL-PRF-195/662 RAD Hard HEXFET TECHNOLOGY Product Summary Part Number Radiatio Level RDS(o) ID QPL

More information

Depletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET

Depletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET Ch. 13 MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor : I D D-mode E-mode V g The gate oxide is made of dielectric SiO 2 with e = 3.9 Depletion-mode operation ( 공핍형 ): Using an input gate voltage

More information

Electronic Circuits for Mechatronics ELCT 609 Lecture 7: MOS-FET Amplifiers

Electronic Circuits for Mechatronics ELCT 609 Lecture 7: MOS-FET Amplifiers Electronic Circuits for Mechatronics ELCT 609 Lecture 7: MOS-FET Amplifiers Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 Enhancement N-MOS Modes of Operation Mode V GS I DS V DS Cutoff

More information

RAD-Hard HEXFET TECHNOLOGY. n Single Event Effect (SEE) Hardened n n n n n n n n

RAD-Hard HEXFET TECHNOLOGY. n Single Event Effect (SEE) Hardened n n n n n n n n PD - 90882F RADIATION HARDENED POWER MOSFET THRU-HOLE (TO-39) IRHF930 JANSR2N7389 0V, P-CHANNEL REF: MIL-PRF-9500/630 RAD-Hard HEXFET TECHNOLOGY Product Summary Part Number Radiatio Level RDS(o) ID QPL

More information

Design and Simulation of Low Voltage Operational Amplifier

Design and Simulation of Low Voltage Operational Amplifier Design and Simulation of Low Voltage Operational Amplifier Zach Nelson Department of Electrical Engineering, University of Nevada, Las Vegas 4505 S Maryland Pkwy, Las Vegas, NV 89154 United States of America

More information

55:041 Electronic Circuits

55:041 Electronic Circuits 55:041 Electronic Circuits Mosfet Review Sections of Chapter 3 &4 A. Kruger Mosfet Review, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width 1 10-6 m or less Thickness 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor

More information

Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages

Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages Lecture 20 Transistor Amplifiers (II) Other Amplifier Stages Outline Common drain amplifier Common gate amplifier Reading Assignment: Howe and Sodini; Chapter 8, Sections 8.78.9 6.02 Spring 2009 . Common

More information

Digital Electronics. Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region. Positive Logic.

Digital Electronics. Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region. Positive Logic. Digital Electronics Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region Positive Logic Logic 1 Negative Logic Logic 0 Voltage Transition Region Transition

More information

Reading. Lecture 17: MOS transistors digital. Context. Digital techniques:

Reading. Lecture 17: MOS transistors digital. Context. Digital techniques: Reading Lecture 17: MOS transistors digital Today we are going to look at the analog characteristics of simple digital devices, 5. 5.4 And following the midterm, we will cover PN diodes again in forward

More information

MOS Field Effect Transistors

MOS Field Effect Transistors MOS Field Effect Transistors A gate contact gate interconnect n polysilicon gate source contacts W active area (thin oxide area) polysilicon gate contact metal interconnect drain contacts A bulk contact

More information

ECE 546 Lecture 12 Integrated Circuits

ECE 546 Lecture 12 Integrated Circuits ECE 546 Lecture 12 Integrated Circuits Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 Integrated Circuits IC Requirements

More information

Laboratory Exercise 3: Dynamic System Response Laboratory Handout AME 250: Fundamentals of Measurements and Data Analysis

Laboratory Exercise 3: Dynamic System Response Laboratory Handout AME 250: Fundamentals of Measurements and Data Analysis Laboratory Exercise 3: Dyamic System Respose Laboratory Hadout AME 50: Fudametals of Measuremets ad Data Aalysis Prepared by: Matthew Beigto Date exercises to be performed: Deliverables: Part I 1) Usig

More information

Building Blocks of Integrated-Circuit Amplifiers

Building Blocks of Integrated-Circuit Amplifiers Building Blocks of ntegrated-circuit Amplifiers 1 The Basic Gain Cell CS and CE Amplifiers with Current Source Loads Current-source- or active-loaded CS amplifier Rin A o R A o g r r o g r 0 m o m o Current-source-

More information

11.11 Two-Channel Filter Banks 1/27

11.11 Two-Channel Filter Banks 1/27 . Two-Chael Filter Baks /7 Two-Chael Filter Baks M We wat to look at methods that are ot based o the DFT I geeral we wat to look at Fig..6 rom Porat ad igure out how to choose i & i to get Perect Reco

More information

CMOS Cascode Transconductance Amplifier

CMOS Cascode Transconductance Amplifier CMOS Cascode Transconductance Amplifier Basic topology. 5 V I SUP v s V G2 M 2 iout C L v OUT Device Data V Tn = 1 V V Tp = 1 V µ n C ox = 50 µa/v 2 µ p C ox = 25 µa/v 2 λ n = 0.05 V 1 λ p = 0.02 V 1 @

More information

The MOSFET. D PMOS and a fourth (substrate) which we normally omit from figures We use enhancement mode devices Normally turned off

The MOSFET. D PMOS and a fourth (substrate) which we normally omit from figures We use enhancement mode devices Normally turned off The MOSFET Metal Oxide Silico Field Effect Trasistor Three termial device Source source of charge carriers (curret) rai sik for charge carriers (curret) Gate potetial (voltage) o gate cotrols curret flow

More information

Week 7: Common-Collector Amplifier, MOS Field Effect Transistor

Week 7: Common-Collector Amplifier, MOS Field Effect Transistor EE 2110A Electronic Circuits Week 7: Common-Collector Amplifier, MOS Field Effect Transistor ecture 07-1 Topics to coer Common-Collector Amplifier MOS Field Effect Transistor Physical Operation and I-V

More information

Review Sheet for Midterm #2

Review Sheet for Midterm #2 Review Sheet for Midterm #2 Brian Bircumshaw brianb@eecs.berkeley.edu 1 Miterm #1 Review See Table 1 on the following page for a list of the most important equations you should know from Midterm #1. 2

More information

EECE2412 Final Exam. with Solutions

EECE2412 Final Exam. with Solutions EECE2412 Final Exam with Solutions Prof. Charles A. DiMarzio Department of Electrical and Computer Engineering Northeastern University Fall Semester 2010 My file 11480/exams/final General Instructions:

More information

Indicator No mark Single preset Dual preset DIN W144 H72mm DIN W48 H96mm No mark DIN W72 H72mm (4 digit) (6 digit) Counter/Timer

Indicator No mark Single preset Dual preset DIN W144 H72mm DIN W48 H96mm No mark DIN W72 H72mm (4 digit) (6 digit) Counter/Timer FX/FX/FX Series DIN W7 7, W8 96, W 7mm er/timer Features 6 iput modes ad output modes ig speed: cps/cps/kcps/kcps Selectable voltage iput (PNP) or No voltage iput (NPN) dditio of Up/Dow iput mode Wide

More information

Lecture 16: Small Signal Amplifiers

Lecture 16: Small Signal Amplifiers Lecture 16: Small Signal Amplifiers Prof. Niknejad Lecture Outline Review: Small Signal Analysis Two Port Circuits Voltage Amplifiers Current Amplifiers Transconductance Amps Transresistance Amps Example:

More information

EECE 301 Signals & Systems Prof. Mark Fowler

EECE 301 Signals & Systems Prof. Mark Fowler EECE 3 Sigals & Systems Prof. Mark Fowler Note Set #6 D-T Systems: DTFT Aalysis of DT Systems Readig Assigmet: Sectios 5.5 & 5.6 of Kame ad Heck / Course Flow Diagram The arrows here show coceptual flow

More information

Replacing MOSFETs with Single Electron Transistors (SET) to Reduce Power Consumption of an Inverter Circuit

Replacing MOSFETs with Single Electron Transistors (SET) to Reduce Power Consumption of an Inverter Circuit Vol:9, No:3, 015 Relacig MOSFETs with Sigle Electro Trasistors (SET) to Reduce Power Cosumtio of a Iverter Circuit Ahmed Shariful Alam, Abu Hea M. Mustafa Kamal, M. Abdul Rahma, M. Nasmus Sakib Kha Shabbir,

More information

INCREASE OF STRAIN GAGE OUTPUT VOLTAGE SIGNALS ACCURACY USING VIRTUAL INSTRUMENT WITH HARMONIC EXCITATION

INCREASE OF STRAIN GAGE OUTPUT VOLTAGE SIGNALS ACCURACY USING VIRTUAL INSTRUMENT WITH HARMONIC EXCITATION XIX IMEKO World Cogress Fudametal ad Applied Metrology September 6, 9, Lisbo, Portugal INCREASE OF STRAIN GAGE OUTPUT VOLTAGE SIGNALS ACCURACY USING VIRTUAL INSTRUMENT WITH HARMONIC EXCITATION Dalibor

More information

C H A P T E R 5. Amplifier Design

C H A P T E R 5. Amplifier Design C H A P T E 5 Amplifier Design The Common-Source Amplifier v 0 = r ( g mvgs )( D 0 ) A v0 = g m r ( D 0 ) Performing the analysis directly on the circuit diagram with the MOSFET model used implicitly.

More information

RAD-Hard HEXFET TECHNOLOGY. n n n n n n n n

RAD-Hard HEXFET TECHNOLOGY. n n n n n n n n PD - 9274D RADIATION HARDENED POWER MOSFET THRU-HOLE (TO-257AA) JANSR2N738 V, N-CHANNEL REF: MIL-PRF-95/64 RAD-Hard HEXFET TECHNOLOGY Product Summary Part Number Radiatio Level RDS(o) ID QPL Part Number

More information

ECE315 / ECE515 Lecture 8 Date:

ECE315 / ECE515 Lecture 8 Date: ECE35 / ECE55 Lecture 8 Date: 05.09.06 CS Amplifier with Constant Current Source Current Steering Circuits CS Stage Followed by CG Stage Cascode as Current Source Cascode as Amplifier ECE35 / ECE55 CS

More information

Field Effect Transistors

Field Effect Transistors Field Effect Transistors LECTURE NO. - 41 Field Effect Transistors www.mycsvtunotes.in JFET MOSFET CMOS Field Effect transistors - FETs First, why are we using still another transistor? BJTs had a small

More information

Chater 6 Bipolar Junction Transistor (BJT)

Chater 6 Bipolar Junction Transistor (BJT) hater 6 iolar Juctio Trasistor (JT) Xiula heg/shirla heg -5- vetio asic about JT veted i 948 by ardee, rattai ad Shockley i ell ab (First Trasistor) iolar oth tyes of carriers (electro ad hole) lay imortat

More information

Solid State Device Fundamentals

Solid State Device Fundamentals Solid State Device Fundamentals 4.4. Field Effect Transistor (MOSFET) ENS 463 Lecture Course by Alexander M. Zaitsev alexander.zaitsev@csi.cuny.edu Tel: 718 982 2812 4N101b 1 Field-effect transistor (FET)

More information

SETTLING-TIME-ORIENTED DESIGN PROCEDURE FOR TWO-STAGE AMPLIFIERS WITH CURRENT-BUFFER MILLER COMPENSATION

SETTLING-TIME-ORIENTED DESIGN PROCEDURE FOR TWO-STAGE AMPLIFIERS WITH CURRENT-BUFFER MILLER COMPENSATION SETTING-TIME-ORIENTED DESIGN PROCEDURE FOR TWO-STAGE AMPIFIERS WITH CURRENT-BUFFER MIER COMPENSATION ANDREA PUGIESE, 1 FRANCESCO AMOROSO, 1 GREGORIO CAPPUCCINO, 1 GIUSEPPE COCORUO 1 Key words: Operatioal

More information

PRACTICAL FILTER DESIGN & IMPLEMENTATION LAB

PRACTICAL FILTER DESIGN & IMPLEMENTATION LAB 1 of 7 PRACTICAL FILTER DESIGN & IMPLEMENTATION LAB BEFORE YOU BEGIN PREREQUISITE LABS Itroductio to Oscilloscope Itroductio to Arbitrary/Fuctio Geerator EXPECTED KNOWLEDGE Uderstadig of LTI systems. Laplace

More information

Pulse Width Modulated to Pneumatic Output (Closed Loop)

Pulse Width Modulated to Pneumatic Output (Closed Loop) Pulse Width Modulated to Peumatic Output (Closed Loop) Dual ad Sigle Valve, Stadard ad Fail Safe FEATURES Accepts cotact closure, trasistor, or triac iputs Field Selectable Iput Pulse Rages, plus Phase

More information

IRHF7130 IRHF8130 JANSR2N7261 JANSH2N7261

IRHF7130 IRHF8130 JANSR2N7261 JANSH2N7261 PD - 90653B REPETITIVE AVALANCHE AND dv/dt RATED HEXFET TRANSISTOR IRHF7130 IRHF8130 JANSR2N7261 JANSH2N7261 100Volt, 0.18Ω, MEGA RAD HARD HEXFET Iteratioal Rectifier s RAD HARD techology HEXFETs demostrate

More information

Analysis and Design of Analog Integrated Circuits Lecture 6. Current Mirrors

Analysis and Design of Analog Integrated Circuits Lecture 6. Current Mirrors Analysis and Design of Analog Integrated Circuits ecture 6 Current Mirrors Michael H. Perrott February 8, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. From ecture 5: Basic Single-Stage

More information

SKEL 4283 Analog CMOS IC Design Current Mirrors

SKEL 4283 Analog CMOS IC Design Current Mirrors SKEL 4283 Analog CMOS IC Design Current Mirrors Dr. Nasir Shaikh Husin Faculty of Electrical Engineering Universiti Teknologi Malaysia Current Mirrors 1 Objectives Introduce and characterize the current

More information

MEASUREMENT AND INSTRUMENTATION STUDY NOTES UNIT-I

MEASUREMENT AND INSTRUMENTATION STUDY NOTES UNIT-I MEASUREMENT AND INSTRUMENTATION STUDY NOTES The MOSFET The MOSFET Metal Oxide FET UNIT-I As well as the Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor available

More information

High-Order CCII-Based Mixed-Mode Universal Filter

High-Order CCII-Based Mixed-Mode Universal Filter High-Order CCII-Based Mixed-Mode Uiversal Filter Che-Nog Lee Departmet of Computer ad Commuicatio Egieerig, Taipei Chegshih Uiversity of Sciece ad Techology, Taipei, Taiwa, R. O. C. Abstract This paper

More information

Single Bit DACs in a Nutshell. Part I DAC Basics

Single Bit DACs in a Nutshell. Part I DAC Basics Sigle Bit DACs i a Nutshell Part I DAC Basics By Dave Va Ess, Pricipal Applicatio Egieer, Cypress Semicoductor May embedded applicatios require geeratig aalog outputs uder digital cotrol. It may be a DC

More information

Microelectronics Circuit Analysis and Design. MOS Capacitor Under Bias: Electric Field and Charge. Basic Structure of MOS Capacitor 9/25/2013

Microelectronics Circuit Analysis and Design. MOS Capacitor Under Bias: Electric Field and Charge. Basic Structure of MOS Capacitor 9/25/2013 Microelectronics Circuit Analysis and Design Donald A. Neamen Chapter 3 The Field Effect Transistor In this chapter, we will: Study and understand the operation and characteristics of the various types

More information

DIGITAL VLSI LAB ASSIGNMENT 1

DIGITAL VLSI LAB ASSIGNMENT 1 DIGITAL VLSI LAB ASSIGNMENT 1 Problem 1: NMOS and PMOS plots using Cadence. In this exercise, you are required to generate both NMOS and PMOS I-V device characteristics (I/P and O/P) using Cadence (Use

More information

Chapter 5: Field Effect Transistors

Chapter 5: Field Effect Transistors Chapter 5: Field Effect Transistors Slide 1 FET FET s (Field Effect Transistors) are much like BJT s (Bipolar Junction Transistors). Similarities: Amplifiers Switching devices Impedance matching circuits

More information

Multistage Amplifiers

Multistage Amplifiers Multistage Amplifiers Single-stage transistor amplifiers are inadequate for meeting most design requirements for any of the four amplifier types (voltage, current, transconductance, and transresistance.)

More information

55:041 Electronic Circuits

55:041 Electronic Circuits 55:041 Electronic Circuits MOSFETs Sections of Chapter 3 &4 A. Kruger MOSFETs, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width = 1 10-6 m or less Thickness = 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor

More information

Embedded Microcomputer Systems Lecture 9.1

Embedded Microcomputer Systems Lecture 9.1 Embedded Microcomputer Systems Lecture 9. Recap from last time Aalog circuit desig Noise Microphoe iterface Objectives Active low pass filter Nyquist Theorem ad aliasig Speaker amplifier Lookig at oise,

More information

PN Junction Diode: I-V Characteristics

PN Junction Diode: I-V Characteristics Chater 6. PN Juctio Diode : I-V Characteristics Chater 6. PN Juctio Diode: I-V Characteristics Sug Jue Kim kimsj@su.ac.kr htt://helios.su.ac.kr Cotets Chater 6. PN Juctio Diode : I-V Characteristics q

More information

d. Can you find intrinsic gain more easily by examining the equation for current? Explain.

d. Can you find intrinsic gain more easily by examining the equation for current? Explain. EECS140 Final Spring 2017 Name SID 1. [8] In a vacuum tube, the plate (or anode) current is a function of the plate voltage (output) and the grid voltage (input). I P = k(v P + µv G ) 3/2 where µ is a

More information

FEATURES 4:1 single-ended multiplexer Q nominal output impedance: 7Ω (V DDO

FEATURES 4:1 single-ended multiplexer Q nominal output impedance: 7Ω (V DDO ICS8304I GENERAL ESCRIPTION The ICS8304I is a low skew, 4:1, Sigle-eded ICS Multiplexer ad a member of the HiPerClockS HiPerClockS family of High Performace Clock Solutios from IT The ICS8304I has four

More information