CHAPTER 5 - CMOS AMPLIFIERS

Transcription

1 CMOS Analog Circuit Design Page 5.0 Chapter Outline 5. Inverters 5. Differential Amplifiers 5.3 Cascode Amplifiers 5.4 Current Amplifiers 5.5 Output Amplifiers 5.6 HighGain Architectures Goal CHAPTER 5 CMOS AMPLIFIERS To develop an understanding of the amplifier building blocks used in CMOS analog circuit design. Design Hierarchy Functional blocks or circuits (Perform a complex function) Chapter 5 Blocks or circuits (Combination of primitives, independent) Subblocks or subcircuits (A primitive, not independent) Fig. 5.0 CMOS Analog Circuit Design Page 5.0 Illustration of Hierarchy in Analog Circuits for an Op Amp Operational Amplifier Biasing Circuits Input Differential Amplifier Second Gain Stage Output Stage Current Source Current Mirrors Current Sink Source Coupled Pair Current Mirror Load Inverter Current Sink Load Source Follower Current Sink Load Fig. 5.0

2 CMOS Analog Circuit Design Page 5. SECTION 5. CMOS INVERTING AMPLIFIERS Characterization of Amplifiers Amplifiers will be characterized by the following properties: Largesignal voltage transfer characteristics Largesignal voltage swing limitations Smallsignal, frequency independent performance Gain Input resistance Output resistance Smallsignal, frequency response Other properties Noise Power dissipation Etc. CMOS Analog Circuit Design Page 5. Inverters The inverting amplifier is an amplifier which amplifies and inverts the input signal. The inverting amplifier generally has the source on ac ground or the commonsource configuration. Various types of inverting CMOS amplifiers: I D I D I D V GG I D v IN I D vout v IN v IN v IN v IN Active NMOS Load Inverter Active PMOS Load Inverter Depletion NMOS Load Inverter We will consider: Active PMOS Load Inverter (active load inverter) Current Source Load Inverter Pushpull Inverter Current Source Load Inverter Pushpull Inverter Fig. 5.

3 CMOS Analog Circuit Design Page 5.3 Voltage Transfer Characteristic of the Active Load Inverter ID (ma) v IN =5.0Vv IN =4.5V vin =4.0V 0.5 K J v IN =3.5V I 0.4 H v IN =3.0V G 0.3 F E v IN =.0V v IN =.5V D C A,B 0.0 v IN =.0V A B 4 C 0 0 v IN The boundary between active and saturation operation for is v DS v GS V TN v IN 0.7V vout3 v IN =.5V 5V W = µm L µm I D W v IN = µm L µm D cutoff saturated E F saturated active G H I J K Fig. 5. CMOS Analog Circuit Design Page 5.4 LargeSignal Voltage Swing Limits of the Active Load Inverter Maximum output voltage, (max): (max) V TP (ignores subthreshold current influence on the MOSFET) Minimum output voltage, (min): Assume that is nonsaturated and that V T = V T = V T. v DS v GS V TN v IN 0.7V The current through is i D = β (v GS V T )v DS v DS (V DD V T )( ) () and the current through is i D = β (v SG V T ) = β ( V T ) = β ( V T ) Equating these currents gives the minimum as, (min) = V T V T (β /β )

4 CMOS Analog Circuit Design Page 5.5 SmallSignal Midband Performance of the Active Load Inverter The development of the smallsignal model for the active load inverter is shown below: S=B v IN I D g m v gs G D=D=G v in g m v gs S=B r ds r ds R out v out v in v out g m v in rds g m v out r ds Sum the currents at the output node to get, g m v in g ds v out g m v out g ds v out = 0 Solving for the voltage gain, v out /v in, gives v out g m v = in g ds g ds g g m m g = K' N W L / m K' P L W The smallsignal output resistance can also be found from the above by letting v in = 0 to get, R out = g ds g ds g m g m Fig. 5.3 CMOS Analog Circuit Design Page 5.6 Frequency Response of the Active Load Inverter Incorporation of the parasitic capacitors into the smallsignal model (x is connected to v out ): C gs x C bd C M C gd C gd V in C bd V out C L V in gm V in R out C out V out Fig. 5.4 If we assume the input voltage has a small source resistance, then we can write the following: g V out (s) m R out s db V in (s) = z 0log0(g m R out ) s p z 0dB log 0 f where p ω 3dB g m = g m, p = R out (C out C M ), and z = g m C M and R out = [g ds g ds g m ] /g m, C M = C gd, and C out = C bd C bd C gs C L If p < z, then the 3dB frequency is approximately equal to [R out (C out C M )]. Fig. 5.4A

5 CMOS Analog Circuit Design Page 5.7 Example 5. Performance of an Active ResistorLoad Inverter Calculate the outputvoltage swing limits for = 5 volts, the smallsignal gain, the output resistance, and the 3 db frequency of active load inverter if (W /L ) is µm/ µm and W /L = µm/ µm, C gd = 00fF, C bd = 00fF, C bd = 00fF, C gs = 00fF, C L = pf, and I D = I D = 00µA, using the parameters in Table 3.. Solution From the above results we find that: (max) = 4.3 volts (min) = 0.48 volts Smallsignal voltage gain =.9V/V R out = 9.7 kω including g ds and g ds and 0 kω ignoring g ds and g ds z =.0x0 9 rads/sec p = 64.x0 6 rads/sec. Thus, the 3 db frequency is 0. MHz. CMOS Analog Circuit Design Page 5.8 Voltage Transfer Characteristic of the Current Source Inverter ID (ma) v IN =5.0Vv IN =4.5V vin =4.0V 0.5 v IN =3.5V 0.4 v IN =3.0V 0.3 vout v IN =.5V.5V KJIH F E v IN =.0V 0. G 0. D v C IN =.5V A,B 0.0 v IN =.0V A B C D 4 active 3 saturated Regions of operation for the transistors: 5V W = µm L µm I D W v IN = L µm µm saturated active E F G H I J K 0 0 v 3 4 IN 5 : v DS v GS V Tn v IN 0.7V : v SD v SG V Tp V GG V Tp 3.V Fig. 5.5

6 CMOS Analog Circuit Design Page 5.9 LargeSignal Voltage Swing Limits of the Current Source Load Inverter Maximum output voltage, (max): (max) Minimum output voltage, (min): Assume that is nonsaturated. The minimum output voltage is, (min) = (min) = ( V T ) This result assumes that v IN is taken to. β V GG V T β V T CMOS Analog Circuit Design Page 5.0 SmallSignal Midband Performance of the Current Source Load Inverter SmallSignal Model: S=B V GG v IN I D r ds G D=D v in g m v gs r ds S=B=G Midband Performance: v out g m v = in g ds g = K' N W ds L / I D λ λ A max log A v R out v out v in v out g m v in rds r ds Ι D!!! and R out = g ds g ds Fig. 5.5B I D (λ λ ) A max 0 A max 00 A max 000 Weak inversion Strong inversion I D 0.µA µa 0µA 00µA ma 0mA Fig. 5.6

7 CMOS Analog Circuit Design Page 5. Frequency Response of the Current Source Load Inverter Incorporation of the parasitic capacitors into the smallsignal model (x is connected to V GG ): C gs x C bd C M C gd C gd V in C bd V out C L V in gm V in R out C out V out Fig. 5.4 If we assume the input voltage has a small source resistance, then we can write the following: g V out (s) m R out s V in (s) = z s p where g m = g m, p = R out (C out C M ), and z = g m C M and R out = g ds g and C ds out = C gd C bd C bd C L C M = C gd Therefore, if p < z, then the 3 db frequency response can be expressed as g ds g ds ω 3dB ω = C gd C gd C bd C bd C L CMOS Analog Circuit Design Page 5. Example 5. Performance of a CurrentSink Inverter The performance of a currentsink CMOS inverter is to be examined. The currentsink inverter is shown in Fig Assume that V SG W = µm, L = µm, W = µm, L = µm, = 5 volts, V GG v IN = 3 volts, and the parameters of Table 3. describe and. Use I D v the capacitor values of Example 5. (C gd = C gd ). Calculate the OUT outputswing limits and the smallsignal performance. V Solution GG To attain the output signalswing limitations, we treat Fig. 5.7 as a current source CMOS inverter with PMOS parameters for the Figure 5.7 Current sink CMOS inverter. NMOS and NMOS parameters for the PMOS and use NMOS equations. Using a prime notation to designate the results of the current source CMOS inverter which exchanges the PMOS and NMOS model parameters, we get (max) = 5V and (min) = (50.7) = 0.74V In terms of the current sink CMOS inverter, these limits are subtracted from 5V to get (max) = 4.6V and (min) = 0V. To find the small signal performance, we must first calculate the dc current. The dc current, I D, is I D = K N W L (V GG V TN ) = 0 (30.7) = 9µA v out /v in = 9.V/V, R out = 38. kω, and f 3dB =.78 MHz.

8 CMOS Analog Circuit Design Page 5.3 Voltage Transfer Characteristic of the PushPull Inverter ID (ma) v v IN =5.0V IN =4.5V v IN =4.0V v IN =3.5V.0 v IN =0.5V 0.8 v IN =.0V v IN =.5V v IN =.0V v IN =3.0V v IN =.5V v IN =.5V F 0. H I G v IN =3.0V E v IN =.0V v IN =3.5V v IN =4.5V D v IN =.5V C J,K A,B 5 A B C v IN =.0V vout 4 3 D v IN E active saturated 5V W = µm L µm I D W = L µm µm F saturated active Note the railtorail output voltage swing G H I J K 0 0 v 3 4 IN 5 Regions of operation for and : : v DS v GS V T v IN 0.7V : v SD v SG V T v IN V T v IN 0.7V Fig. 5.8 CMOS Analog Circuit Design Page 5.4 SmallSignal Performance of the PushPull Amplifier 5V C M v in v out v in g m v in r ds g m v in r ds C out v out Fig. 5.9 Smallsignal analysis gives the following results: and v out v = (g m g m ) in g ds g = (/I D ) ds R out = g ds g ds z = g m g m C M = g m g m C gd C gd (g ds g ds ) p = C gd C gd C bd C bd C L If z > p, then g ds g ds ω 3dB = C gd C gd C bd C bd C L K' N (W /L ) K' P (W /L ) λ λ

9 CMOS Analog Circuit Design Page 5.5 Example 5.3 Performance of a PushPull Inverter The performance of a pushpull CMOS inverter is to be examined. Assume that W = µm, L = µm, W = µm, L = µm, = 5 volts, and use the parameters of Table 3. to model and. Use the capacitor values of Example 5. (C gd = C gd ). Calculate the outputswing limits and the smallsignal performance assuming that I D = I D = 300µA. Solution The output swing is seen to be from 0V to 5V. In order to find the small signal performance, we will make the important assumption that both transistors are operating in the saturation region. Therefore: v out 57µS 45µS v = in µs 5µS = 8.6V/V R out = 37 kω f 3dB =.86 MHz and z = 399 MHz CMOS Analog Circuit Design Page 5.6 Noise Analysis of Inverting Amplifiers Noise model: Approach: e n * Noise Free MOSFETs e out e n e eq v in v in * * Noise Free MOSFETs e out Fig. 5.0.) Assume a meansquare inputvoltagenoise spectral density e n in series with the gate of each MOSFET. (This step assumes that the MOSFET is the common source configuration.).) Calculate the outputvoltagenoise spectral density, e out (Assume all sources are additive). 3.) Refer the outputvoltagenoise spectral density back to the input to get equivalent input noise e eq. 4.) Substitute the type of noise source, /f or thermal.

10 CMOS Analog Circuit Design Page 5.7 Noise Analysis of the Active Load Inverter.) See model to the right..) e out = e n g m g en m 3.) e eq = e n g m g e n m e n Up to this point, the type of noise is not defined. /f Noise Substituting e KF n = fc ox WLK = B fwl, into the above gives, e eq (/f) = B fw / L K' B K' B L / L To minimize /f noise,.) Make L >>L,.) increase the value of W and 3.) choose as a PMOS. Thermal Noise Substituting e n = 8kT 3g into the above gives, m e eq (th) = 8kT( η ) 3[K' (W/L) I ] / W L K' / / L W K' To minimize thermal noise, maximize the gain of the inverter. e n * Noise Free MOSFETs e out e n e eq v in v in * * Noise Free MOSFETs e out Fig. 5.0 CMOS Analog Circuit Design Page 5.8 Noise Analysis of the Active Load Inverter Continued When calculating the contribution of e n to e out, it was assumed that the gain was unity. To verify this assumption consider the following model: e n * v gs g m v gs r ds r ds eout _ We can show that, Fig. 5. e out e = g m (r ds r ds ) n g m (r ds r ds )

11 CMOS Analog Circuit Design Page 5.9 Noise Analysis of the Current Source Load Inverting Amplifier Model: Noise e n Free MOSFETs * V GG e e n out e eq v in v in * * The outputvoltagenoise spectral density of this inverter can be written as, e out = (g m r out ) e n (g m r out ) e n or e eq = e n (g m r out ) g m g m e n (g m r out ) e n = e n e n Noise Free MOSFETs e out Fig. 5.. This result is identical with the active load inverter. Thus the noise performance of the two circuits are equivalent although the smallsignal voltage gain is significantly different. CMOS Analog Circuit Design Page 5.0 Noise Analysis of the PushPull Amplifier Model: v in e n * e n * Noise Free MOSFETs e out Fig The equivalent inputvoltagenoise spectral density of the pushpull inverter can be found as g m e n g m e n e eq = g m g m g m g m If the two transconductances are balanced (g m = g m ), then the noise contribution of each device is divided by two. The total noise contribution can only be reduced by reducing the noise contribution of each device. (Basically, both and act like the load transistor and input transistor, so there is no defined input transistor that can cause the noise of the load transistor to be insignificant.)

12 CMOS Analog Circuit Design Page 5. Summary of CMOS Inverting Amplifiers Inverter pchannel active load inverter nchannel active load inverter AC Voltage Gain gm gm gm gmgmb AC Output Resistance gm gmgmb Bandwidth (CGB=0) gm CBDCGSCGSCBD gmgmb CBDCGDCGSCBS Equivalent, inputreferred,meansquare noise voltage g m e n e n g m e n e n g m g m Current source load inverter gm gdsgds gdsgds gdsgds CBDCGDCDGCBD g m e n e n g m nchannel depletion load inverter ~ g m gmb gmbgdsgds gmbgdsgds CBDCGDCGSCBD e n e n g m g m PushPull inverter (gmgm) gdsgds gdsgds gdsgds CBDCGDCGSCBD e n g m e n g m g m g m g m g m Inverting configurations we did not examine. CMOS Analog Circuit Design Page 5. SECTION 5. DIFFERENTIAL AMPLIFIERS What is a Differential Amplifier? A differential amplifier is an amplifier that amplifies the difference between two voltages and rejects the average or common mode value of the two voltages. Symbol for a differential amplifier: v v v OUT Fig. 5.A Differential and common mode voltages: v and v are called singleended voltages. They are voltages referenced to ac ground. The differentialmode input voltage, v ID, is the voltage difference between v and v. The commonmode input voltage, v IC, is the average value of v and v. v ID = v v and v IC = v v v = v IC 0.5v ID and v = v IC 0.5v ID v ID = A VD v ID ± A VC v IC = A VD (v v ) ± A v v VC v IC v ID Fig. 5.B where A VD = differentialmode voltage gain A VC = commonmode voltage gain

13 CMOS Analog Circuit Design Page 5. Differential Amplifier Definitions Common mode rejection rato (CMRR) A VD CMRR = A VC CMRR is a measure of how well the differential amplifier rejects the commonmode input voltage in favor of the differentialinput voltage. Input commonmode range (ICMR) The input commonmode range is the range of commonmode voltages over which the differential amplifier continues to sense and amplify the difference signal with the same gain. Typically, the ICMR is defined by the commonmode voltage range over which all MOSFETs remain in the saturation region. Output offset voltage (V OS (out)) The output offset voltage is the voltage which appears at the output of the differential amplifier when the input terminals are connected together. Input offset voltage (V OS (in) = V OS ) The input offset voltage is equal to the output offset voltage divided by the differential voltage gain. V OS = V OS (out) A VD CMOS Analog Circuit Design Page 5.3 Transconductance Characteristic of the Differential Amplifier Consider the following nchannel differential amplifier (sometimes called a sourcecoupled pair): v I ID Bias M4 i D i D v G v G v GS v GS M3 I SS V Bulk Fig. 5. Where should bulk be connected? Consider a pwell, CMOS technology, D G S S G D n n p n n n pwell nsubstrate Fig. 5.3.) Bulks connected to the sources: No modulation of V T but large common mode parasitic capacitance..) Bulks connected to ground: Smaller common mode parasitic capacitors, but modulation of V T. If the technology is nwell CMOS, there is no choice. The bulks must be connected to ground.

14 CMOS Analog Circuit Design Page 5.4 Transconductance Characteristic of the Differential Amplifier Continued Defining equations: v ID = v GS v GS = i D / β i D / β and I SS = i D i D Solution: i D = I SS I SS βv ID I SS β v 4 ID 4I SS which are valid for v ID < (I SS /β) /. Illustration of the result: / and i D = I SS I SS βv ID I SS β v 4 ID 4I SS / i D /I SS i 0.6 D 0.4 i D 0. v ID (I SS /ß)0.5 Fig. 5.4 Differentiating i D (or i D ) with respect to v ID and setting V ID =0V gives g m = di D dv (V ID = 0) = (βi SS /4) / = K' I SS W / ID 4L (half the g m of an inverting amplifier) CMOS Analog Circuit Design Page 5.5 Voltage Transfer Characteristic of the Differential Amplifier In order to obtain the voltage transfer characteristic, a load for the differential amplifier must be defined. We will select a current mirror load as illustrated below. v GS v G µm µm M3 i D3 µm µm V Bias i D µm µm µm µm M4 i D4 i OUT µm i D µm v GS I SS v G M5 Fig. 5.5 Note that output signal to ground is equivalent to the differential output signal due to the current mirror. The shortcircuit, transconductance is given as g m = di OUT dv (V ID = 0) = (βi SS ) / = K' I SS W / ID L

15 CMOS Analog Circuit Design Page 5.6 Voltage Transfer Function of the Differential Amplifer with a Current Mirror Load vout (Volts) Regions of operation of the transistors: is saturated when, V IC = V M4 active M4 saturated saturated active v ID (Volts) Fig. 5.6 v DS v GS V TN V S V IC 0.5v ID V S V TN V IC V TN where we have assumed that the region of transition for is close to v ID = 0V. M4 is saturated when, v SD4 v SG4 V TP V SG4 V TP V SG4 V TP The regions of operations shown on the voltage transfer function assume I SS = 00µA. Note: V SG4 = V TP = V TP = 4V CMOS Analog Circuit Design Page 5.7 Differential Amplifier Using pchannel Input MOSFETs V Bias v G v SG i D i D3 M3 M5 IDD v SG i D i OUT i D4 v G v M4 OUT Fig. 5.7

16 CMOS Analog Circuit Design Page 5.8 Input Common Mode Range (ICMR) ICMR is found by setting v ID = 0 and varying v IC until one of the transistors leaves the saturation region. Highest Common Mode Voltage Path from G through and M3 to : V IC (max) =V G (max) =V G (max) = V SG3 V DS (sat) V GS or V IC (max) = V SG3 V TN Path from G through and M4 to : V IC (max) = V SD4 (sat) V DS (sat) V GS = V SD4 (sat) V TN V IC (max) = V SG3 V TN Lowest Common Mode Voltage V IC (min) = V DS5 (sat) V GS = V DS5 (sat) V GS v GS v G µm µm M3 i D3 µm µm V Bias i D µm µm µm µm M4 i D4 i OUT µm i D µm v GS I SS v G M5 Fig. 5.5 where we have assumed that V GS = V GS during changes in the input common mode voltage. CMOS Analog Circuit Design Page 5.9 Example 5. Calculation of the WorstCase Input CommonMode Range of the nchannel Input, Differential Amplifier Assume that varies from 4 to 6 volts and that V SS = 0, and use the values of Table 3. under worstcase conditions to calculate the input commonmode range of nchannel input differential amplifier with a current mirror load. Assume that I SS is 00 µa, W /L = W /L = 5, W 3 /L 3 = W 4 /L 4 =, and V DS5 (sat) = 0. V. Include worstcase variation in K' in calculations. Solution If varies 5 ± volts, then the upper commonmode voltage is, V IC (max) = 4 50µA 45µA/V = =. volts The lower commonmode voltage is, V IC (min) = µA 99µA/V = =.50 volts which gives a worstcase input commonmode range of 0.7 volts with a nominal 5volt power supply. Reducing by several volts more will result in a worstcase commonmode range of zero. We have assumed in this example that all bulksource voltages are zero.

17 CMOS Analog Circuit Design Page 5.0 SmallSignal Analysis of the DifferentialMode of the Differential Amplifier A requirement for differentialmode operation is that the differential amplifier is perfectly balanced. VDD v id M3 i D3 i D M4 i D4 i out i D v out G G v id v g v g C D=G3=D3=G4 C3 r ds S=S r ds i 3 r g r ds5 i 3 ds3 m3 gmv gs g m v gs S3 D=D4 r ds4 C S4 v out M5 I SS G G v D=G3=D3=G4 id V Bias i v 3 gs v gs C3 g m v gs r ds rds3 g m3 gm v gs i 3 C S=S=S3=S4 Differential Transconductance: Assume that the output of the differential amplifier is an ac short. rds D=D4 i out = g m g m3 r p g m3 r p v gs g m v gs g m v gs g m v gs = g md v id where g m = g m = g md, r p = r ds r ds3 and i' out designates the output current into a short circuit. r ds4 C i out ' v out Fig. 5.8 It can be shown that the current mirror causes this requirement to be invalid because the drain loads are not matched. However, we will continue to use the assumption regardless. See Problem 5.6. CMOS Analog Circuit Design Page 5. SmallSignal Analysis of the DifferentialMode of the Differential Amplifier Continued r out = = r g ds g ds r ds4 ds4 Differential Voltage Gain: A v = v out g md v = id g ds g ds4 If we assume that all transistors are in saturation and replace the small signal parameters of g m and r ds in terms of their largesignal model equivalents, we achieve A v = v out v = (K' I SS W /L ) / id (λ λ 4 )(I SS /) = K' W / λ λ 4 I SS L I SS Note that the smallsignal gain is inversely proportional to the square root of the bias current! Example: If W /L = µm/µm and I SS = 50µA (0µA), then A v (nchannel) = 46.6V/V (04.3V/V) v out v in A v (pchannel) = 3.4V/V (70.7V/V) r out = = g ds g ds4 5µA 0.09V = 0.444MΩ (.MΩ) Weak Inversion µa Stong Inversion log(i Bias ) ALA075

18 CMOS Analog Circuit Design Page 5. Common Mode Analysis for the Current Mirror Load Differential Amplifier The current mirror load differential amplifier is not a good example for common mode analysis because the current mirror rejects the common mode signal. M3 M3M4 M4 v out 0V v ic VBias M5 Fig. 5.8A Total common Common mode Common mode mode Output = output due to due to v ic M3M4 path output due to path Therefore The common mode output voltage should ideally be zero. Any voltage that exists at the output is due to mismatches in the gain between the two different paths. CMOS Analog Circuit Design Page 5.3 SmallSignal Analysis of the CommonMode of the Differential Amplifier The commonmode gain of the differential amplifier with a current mirror load is ideally zero. To illustrate the commonmode gain, we need a different type of load so we will consider the following: M3 M4 M3 M4 M3 v o vo v o v o v o M4 v o v v v id v id V Bias I SS M5 v ic I SS M5x V Bias I SS v ic DifferentialMode Analysis: Differentialmode circuit General circuit Commonmode circuit Fig. 5.9 and v o v id g m g m3 v o v g m id g m4 Note that these voltage gains are half of the active load inverter voltage gain.

19 CMOS Analog Circuit Design Page 5.4 SmallSignal Analysis of the CommonMode of the Differential Amplifier Continued CommonMode Analysis: v gs g m v gs v ic r ds5 rds r ds3 g m3 v o Fig. 5.0 Assume that r ds is large and can be ignored (greatly simplifies the analysis). v gs = v g v s = v ic g m r ds5 v gs Solving for v gs gives v ic v gs = g m r ds5 The singleended output voltage, v o, as a function of v ic can be written as v o v = g m [r ds3 (/g m3 )] (g m /g m3 ) ic g m r ds5 g m r g ds5 ds5 g m3 CommonMode Rejection Ratio (CMRR): CMRR = v o /v id v o /v ic = g m /g m3 g ds5 /g = g m3 m r ds5 How could you easily increase the CMRR of this differential amplifier? CMOS Analog Circuit Design Page 5.5 Frequency Response of the Differential Amplifer (Differential Mode) Back to the current mirror load differential amplifier: VDD C gs3 C gs4 M3 M4 C bd3 C bd4 v id C gd C gd4 C bd C bd M5 C gd v out C L G G v D=G3=D3=G4 id i v 3 gs v gs C3 gmv gs gm3 gmv gs i 3 C S=S=S3=S4 D=D4 i out ' rds rds4 C v out Fig. 5.0B V Bias Ignore the zeros that occur due to C gd, C gd and C gd4. C = C gd C bd C bd3 C gs3 C gs4, C = C bd C bd4 C gd C L and C 3 = C gd4 If C 3 0, then we can write g m V out (s) g ds g g m3 V ds4 g m3 sc gs (s) V gs (s) ω s ω where ω = g ds g ds4 C gm3 If we further assume that C >> g ds g ds4 C then the frequency response of the differential amplifier reduces to V out (s) V id (s) g m g ω ds g ds4 s ω (A more detailed analysis will be made later)

20 CMOS Analog Circuit Design Page 5.6 An Intuitive Method of Small Signal Analysis Small signal analysis is used so often in analog circuit design that it becomes desirable to find faster ways of performing this important analysis. Intuitive Analysis (or Schematic Analysis) Technique:.) Identify the transistor(s) that convert the input voltage to current (these transistors are called transconductance transistors)..) Trace the currents to where they flow into an equivalent resistance to ground. 3.) Multiply this resistance by the current to get the voltage at this node to ground. 4.) Repeat this process until the output is reached. Simple Example: R g m v in v o gm v o v out v in R Fig. 5.0C v o = (g m v in ) R v out = (g m v o )R v out = (g m R g m R )v in CMOS Analog Circuit Design Page 5.7 Intuitive Analysis of the CurrentMirror Load Differential Amplifier VDD M3 V Bias g m v id.) i = 0.5g m v id and i = 0.5g m v id.) i 3 = i = 0.5g m v id 3.) i 4 = i 3 = 0.5g m v id M5 g m v id M4 r out g m v id g m v id v id v id v id 4.) The resistance at the output node, r out, is r ds r ds4 or g ds g ds4 v out Fig. 5. g m v in g m v in 5.) v out = (0.5g m v id 0.5g m v id )r out = g ds g = ds4 g ds g ds4 v out g m v = in g ds g ds4

21 CMOS Analog Circuit Design Page 5.8 Some Concepts to Help Extend the Intuitive Method of SmallSignal Analysis.) Approximate the output resistance of any cascode circuit as R out (g m r ds )r ds where is a transistor cascoded by..) If there is a resistance, R, in series with the source of the transconductance transistor, let the effective transconductance be g m g m(eff) = g m R Proof: g m (eff)v in g m (eff)v in g m v gs i out v gs v in r ds v in v in r ds Smallsignal model V Bias Fig. 5.A v in v gs = v g v s = v in (g m r ds )v gs v gs = g m r ds g m v in Thus, i out = g m r = g ds m (eff) v in CMOS Analog Circuit Design Page 5.9 Slew Rate of the Differential Amplifier Slew Rate (SR) = Maximum outputvoltage rate (either positive or negative) d It is caused by the relationship, i OUT = C L dt. When i OUT is a constant, the rate becomes a constant. Consider the following currentmirror load, differential amplifiers: VDD M3 v GS v G V Bias i D3 i D M5 M4 i D4 i D i OUT v GS I SS v G C L V Bias v SG v G M3 i D i D3 M5 IDD v SG i D i OUT i D4 M4 C L v G Fig. 5.B Note that slew rate can only occur when the differential input signal is large enough to cause I SS (I DD ) to flow through only one of I the differential input transistors. SS SR = I DD C = L C If C L L = 5pF and I SS = 0µA, the slew rate is SR = V/µs. (For the BJT differential amplifier slewing occurs at ±00mV whereas for the MOSFET differential amplifier it can be ±V or more.)

22 CMOS Analog Circuit Design Page 5.0 Noise Analysis of the Differential Amplifier M5 V Bias e n e n e eq * * i to e n3 e n4 M3 * * M4 V out * M5 V Bias M3 M5 M4 Solve for the total outputnoise current to get, i to = gm e n gm e n gm3 e n3 gm4 e n4 Fig. 5.C This outputnoise current can be expressed in terms of an equivalent input noise voltage, e eq, given as i to = gm e eq Equating the above two expressions for the total outputnoise current gives, e eq = en en g m3 g e m n3 en4 /f Noise ( e n = e n and e n3 = e n4 ): Thermal Noise ( e n = e n and e n3 = e n4 ): e eq(/f) = B P fw L K N B N K L P B P L 3 e eq(th) = 6kT 3[K' (W/L) I ] / W 3 L K' 3 L / 3 W K' CMOS Analog Circuit Design Page 5. CurrentSource Load Differential Amplifier Gives a truly balanced differential amplifier. X M7 v 3 M3 X M4 X I 3 I 4 v4 I Bias v I I X X M6 M5 I 5 X X v Also, the upper input commonmode range is extended. However, a problem occurs if I I 3 or if I I 4. Fig. 5. Current Current I 3 I I 3 I 0 0 V DS <V DS (sat) v DS 0 0 V SD3 <V SD (sat) (a.) I>I3. (b.) I3>I. v DS Fig. 5.3

23 CMOS Analog Circuit Design Page 5. A DifferentialOutput, DifferentialInput Amplifier Probably the best way to solve the current mismatch problem is through the use of commonmode feedback. Consider the following solution to the previous problem. I Bias V CM MC3 Commonmode feedback circuit I C3 MC MCA MC4 I C4 MCB M3 M4 v 3 I 3 I 4 v v 4 Selfresistances of M4 v MB MC5 M5 V SS Fig. 5.4 Operation: Common mode output voltages are sensed at the gates of MCA and MCB and compared to V CM. The current in MC3 provides the negative feedback to drive the common mode output voltage to the desired level. CMOS Analog Circuit Design Page 5.3 Design of a CMOS Differential Amplifier with a Current Mirror Load Design Considerations: Constraints Specifications Power supply Technology Temperature Relationships A v = g m R out ω 3dB = /R out C L Smallsignal gain Frequency response (C L ) ICMR Slew rate (C L ) Power dissipation V IC (max) = V SG3 V TN V IC (min) = V SS V DS5 (sat) V GS = V SS V DS5 (sat) V GS vin V Bias M3 V SS I 5 M5 M4 ALA0 C L v out SR = I SS /C L P diss = ( V SS )xall dc currents flowing from or to V SS

24 CMOS Analog Circuit Design Page 5.4 Design of a CMOS Differential Amplifier with a Current Mirror Load Continued Schematicwise, the design procedure is illustrated as shown: M3 vin Min. ICMR VBias Max. ICMR V SG4 g m R out V SS M5 M4 ALA0 v out C L I 5 I 5 = SR C L, ω 3dB, P diss Procedure:.) Pick I SS to satisfy the slew rate knowing C L or the power dissipation.) Check to see if R out will satisfy the frequency response, if not change I SS or modify circuit 3.) Design W 3 /L 3 (W 4 /L 4 ) to satisfy the upper ICMR 4.) Design W /L (W /L ) to satisfy the gain 5.) Design W 5 /L 5 to satisfy the lower ICMR 6.) Iterate where necessary CMOS Analog Circuit Design Page 5.5 Example 5 Design of a MOS Differential Amplifier with a Current Mirror Load Design the currents and W/L values of the current mirror load MOS differential amplifier to satisfy the following specifications: = V SS =.5V, SR 0V/µs (C L =5pF), f 3dB 00kHz (C L =5pF), a small signal gain of 00V/V,.5V ICMR V and P diss mw. Use the parameters of K N =0µA/V, K P =50µA/V, V TN = 0.7V, V TP = 0.7V, λ N = 0.04V and λ P = 0.05V. Solution.) To meet the slew rate, I SS 50µA. For maximum P diss, I SS 00µA..) f 3dB of 00kHz implies that R out 38kΩ. This gives R out = (λ N λ P )I 38kΩ SS I SS 70µA Thus, pick I SS = 00µA 3.) V IC (max) = V SG3 V TN V =.5 V SG3 0.7 V SG3 =.V = W 3 L = W 4 3 L = 4 (0.5) = 8 g m 4.) 00V/V = g m R out = g ds g = ds4 5.) V IC (min) = V SS V DS5 (sat) V GS.5 =.5 V DS5 (sat) V DS5 (sat) = = !! 50µA 50µA/V (W 3 /L 3 ) 0.7 0µA/V (W /L ) ( ) 50µA = 3.3 W /L W L = W L = 8.4 W 5 L 5 = I SS K N V DS5 (sat) = µA 0µA/V (8.4) 0.7 We probably should increase W /L to reduce V GS and allow a smaller W 5 /L 5. If we choose W /L = 40, then W 5 /L 5 = 9. (Larger than specified gain should be okay.)

25 CMOS Analog Circuit Design Page 5.3 SECTION 5.3 CASCODE AMPLIFIER Why Use the Cascode Amplifier? Can provide higher output resistance and larger gain if the load is also high resistance. It reduces the Miller effect when the driving source has a large source resistance. V GG3 M3 v S V C GG gd R s R S v IN v Fig. 5.3 The Miller effect causes C gd to be increased by the value of (v /v in ) and appear in parallel with the gatesource of causing a dominant pole to occur. The cascode amplifier eliminates this dominant pole by keeping the value of v /v in small by making the value of R to be approximately /g m. CMOS Analog Circuit Design Page 5.3 LargeSignal Characteristics of the Cascode Amplifier v IN =5.0V v IN =4.5V 5V 0.5 v IN =4.0V M3 W v 3 = µm IN =3.5V L 3 µm 0.4 v IN =3.0V I.3V D v IN =.5V 0.3 K W G F = JIH E L µm µm 0. v IN =.0V 3.4V M3 v OUT 0. D W v = µm IN =.5V L v µm C A,B v IN IN =.0V A B C D 4 E M3 active 3 M3 saturated saturated active ID (ma) Fig. 5.3 is saturated when V GG V GS V GS V T vout F G H saturated active I J K 0 0 v 3 4 IN 5 v IN 0.5(V GG V TN ) where V GS = V GS is saturated when V DS V GS V TN V DS V GG V DS V TN V GG V TN M3 is saturated when V GG3 V TP V GG3 V TP

26 CMOS Analog Circuit Design Page 5.33 LargeSignal Voltage Swing Limits of the Cascode Amplifier Maximum output voltage, (max): (max) = Minimum output voltage, (min): Referencing all potentials to the negative power supply (ground in this case), we may express the current through each of the devices, through M3, as i D = β ( V T )v DS v DS β ( V T )v DS i D = β (V GG v DS V T )( v DS ) ( v DS ) and β (V GG v DS V T )( v DS ) i D3 = β 3 ( V GG3 V T3 ) where we have also assumed that both v DS and are small, and v IN =. Solving for by realizing that i D = i D = i D3 and β = β we get, (min) = β 3 β (V DD V GG3 V T3 ) V GG V T V T CMOS Analog Circuit Design Page 5.34 Example 5.3 Calculation of the Minimum Output Voltage for the Simple Cascode Amplifier (a.) Assume the values and parameters used for the cascode configuration plotted in the previous slide on the voltage transfer function and calculate the value of (min). (b.) Find the value of (max) and (min) where all transistors remain in saturation. Solution (a.) Using the previous result gives, (min) = 0.50 volts. We note that simulation gives a value of about 0.75 volts. If we include the influence of the channel modulation on M3 in the previous derivation, the calculated value is 0.6 volts which is closer. The difference is attributable to the assumption that both v DS and are small. (b.) The largest output voltage for which all transistors of the cascode amplifier are in saturation is given as (max) = V SD3 (sat) and the corresponding minimum output voltage is (min) = V DS (sat) V DS (sat). For the cascode amplifier of Fig. 5.3, these limits are 3.0V and.7v. Consequently, the range over which all transistors are saturated is quite small for a 5V power supply.

27 CMOS Analog Circuit Design Page 5.35 SmallSignal Midband Performance of the Cascode Amplifier Smallsignal model: Using nodal analysis, we can write, g m v gs = g m v G D=S D=D3 r ds v in = v v g m v r v gs gs rds ds3 out S=G=G3 Smallsignal model of cascode amplifier neglecting the bulk effect on. C r G D=S ds D=D3 v in g m v in rds C v r g g m v ds3 C 3 v out m Simplified equivalent model of the above circuit. Fig [g ds g ds g m ]v g ds v out = g m v in [g ds g m ]v (g ds g ds3 )v out = 0 Solving for v out /v in yields v out g m (g ds g m ) v = in g ds g ds g ds g ds3 g ds g ds3 g ds3 g m The smallsignal output resistance is, r out = [r ds r ds g m r ds r ds ] r ds3 r ds3 g m g ds3 = K' W L I D λ 3 CMOS Analog Circuit Design Page 5.36 SmallSignal Analysis of the Cascode Amplifier Continued It is of interest to examine the voltage gain of v /v in. From the previous nodal equations we can solve for this gain as, v v in = g m (g ds g ds3 ) g ds g ds g ds g ds3 g ds g ds3 g ds3 g g ds g ds3 m g g m ds3 g m g m g m = If the W/L ratios of and are identical and g ds = g ds3, then v /v in is approximately. Why is this gain instead of? Consider the smallsignal model looking into the source of : R s g m v s The voltage loop is written as, v s = (i g m v s )r ds i r ds3 i i B = i (r ds r ds3 ) g m r ds v s Solving this equation for the ratio of v s to i gives R s = v s i = r ds r ds3 g m r ds W L L W We see that R s is indeed equal to /g m if r ds r ds3. Thus, if g m g m, the voltage gain v /v in. Note that: r ds3 = 0 that R s /g m or r ds3 = r ds that R s /g m or r ds3 r ds g m r ds that R s r ds!!! Principle: The smallsignal resistance looking into the source of a MOSFET depends on the resistance connected from the drain of the MOSFET to ac ground. v s r ds i A r ds3 Fig. 5.34

28 CMOS Analog Circuit Design Page 5.37 Frequency Response of the Cascode Amplifier Smallsignal model (R S = 0): C r G D=S ds D=D3 v in g m v in rds C v r g g m v ds3 C 3 v out m Fig. 5.34A where C = C gd, C = C bd C bs C gs and C 3 = C bd C bd3 C gd C gd3 C L The nodal equations now become: (g m g ds g ds sc sc )v g ds v out = (g m sc )v in and (g ds g m )v (g ds g ds3 sc 3 )v out = 0 Solving for V out (s)/v in (s) gives, V out (s) V in (s) = (g m sc )(g ds g m ) as bs g ds g ds g ds3 (g m g ds g ds ) where a = C 3(g ds g ds g m ) C (g ds g ds3 ) C (g ds g ds3 ) g ds g ds g ds3 (g m g ds g ds ) and C 3 (C C ) b = g ds g ds g ds3 (g m g ds g ds ) CMOS Analog Circuit Design Page 5.38 A Simplified Method of Finding an Algebraic Expression for the Two Poles Assume that a general secondorder polynomial can be written as: P(s) = as bs = s p s p = s p s p p p Now if p >> p, then P(s) can be simplified as P(s) s s p p p Therefore we may write p and p in terms of a and b as p = a and p = a b Applying this to the previous problem gives, p = [g ds g ds g ds3 (g m g ds g ds )] C 3 (g ds g ds g m ) C (g ds g ds3 ) C (g ds g ds3 ) g ds3 C 3 The nondominant root p is given as p = [C 3(g ds g ds g m ) C (g ds g ds3 ) C (g ds g ds3 )] C 3 (C C ) g m C C Assuming that C, C, and C 3 are the same order of magnitude, and that g m is greater than g ds3, then p is smaller than p (closer to the origin). Therefore the approximation of p >> p is valid. Note that there is a righthalf plane zero at z = g m C.

29 CMOS Analog Circuit Design Page 5.39 Driving Amplifiers from a High Resistance Source The Miller Effect Examine the frequency response of a currentsource load inverter driven from a high resistance source: vin R s V GG R s v out V in R R s C s C C gs C V gm V C 3 R3 C 3 = C bd C bd C gd C = C gd R 3 = r ds r ds Fig Assuming the input is I in, the nodal equations are, [G s(c C )]V sc V out = I in and (g m sc )V [G 3 s(c C 3 )]V out = 0 where G = G s (=/R s ), G 3 = g ds g ds, C = C gs, C = C gd and C 3 = C bd C bd C gd. Solving for V out (s)/v in (s) gives V out (s) V in (s) = (sc g m )G G G 3 s[g 3 (C C )G (C C 3 )g m C ](C C C C 3 C C 3 )s or V out (s) V in (s) = g m [ s(c /g m )] G 3 [R (C C )R 3 (C C 3 )g m R R 3 C ]s(c C C C 3 C C 3 )R R 3 s Assuming that the poles are split allows the use of the previous technique to get, g m C p = R (C C ) R 3 (C C 3 ) g m R R 3 C g m R R 3 C and p C C C C 3 C C 3 The Miller effect has caused the input pole, /R C, to be decreased by a value of g m R 3. V out CMOS Analog Circuit Design Page 5.30 How does the Cascode Amplifier Solve the Miller Effect? The dominant pole of the inverting amplifier with a large source resistance was found to be p (inverter) = R (C C )R 3 (C C 3 )g m R R 3 C Now if a cascode amplifier is used, R 3, can be approximated as /g m of the cascoding transistor (assuming the drain sees an r ds to ac ground). p (cascode) = R (C C ) g (C m C 3 )g m R = g C m R (C C ) g (C m C 3 )R C R (C 3C ) Thus we see that p (cascode) >> p (inverter).

30 CMOS Analog Circuit Design Page 5.3 High Gain and High Output Resistance Cascode Amplifier If the load of the cascode amplifier is a cascode current source, then both high output resistance and high voltage gain is achieved. M4 V D=D3 GG4 M3 V GG3 g v m v g mbs v r ds g m3 v 4 g mbs3 v 4 r ds3 out V R out G D=S D4=S3 GG v out v in v in v r g m v ds v 4 r ds4 in G=G3=G4=S=S4 Fig The output resistance is, r out = [r ds r ds g m r ds r ds (η )] [r ds3 r ds4 g m3 r ds3 r ds4 (η 3 )] [g m r ds r ds ] [g m3 r ds3 r ds4 ] r out I.5 D λ λ K' (W/L) Knowing r out, the gain is simply λ 3 λ 4 K' 3 (W/L) 3 A v = g m r out g m {[g m r ds r ds ] [g m3 r ds3 r ds4 ]} K' (W/L) ID λ λ λ 3 λ 4 K' (W/L) K' 3 (W/L) 3 CMOS Analog Circuit Design Page 5.3 Example 5.3 Comparison of the Cascode Amplifier Performance Calculate the smallsignal voltage gain, output resistance, the dominant pole, and the nondominant pole for the lowgain, cascode amplifier and the highgain, cascode amplifier. Assume that I D = 00 microamperes, that all W/L ratios are µm/µm, and that the parameters of Table 3. are valid. The capacitors are assumed to be: C gd = 3.5 ff, C gs = 30 ff, C bsn = C bdn = 4 ff, C bsp = C bdp = ff, and C L = pf. Solution The lowgain, cascode amplifier has the following smallsignal performance: A v = 37.V/V R out = 5kΩ p g ds3 /C 3 =. MHz p g m /(C C ) = 605 MHz. The highgain, cascode amplifier has the following smallsignal performance: A v = 44V/V R out =.40 MΩ p /R out C 3 = 08 khz p g m /(C C ) = 579 MHz (Note that at this frequency, the drain of is shorted to ground by the load capacitance, C L )

31 CMOS Analog Circuit Design Page 5.33 Designing Cascode Amplifiers Pertinent design equations for the simple cascode amplifier. I = K PW 3 L 3 ( V GG3 V TP ) Fig V GG3 V GG V GG = V DS (sat) V GS v IN M3 I (max) = V SD3 (sat) =V I DD K P (W 3 /L 3 ) (min) =V DS (sat) V DS (sat) = I I K N (W /L ) K N (W /L ) I = P diss = (SR) C out A v = g m g ds3 = K N(W /L ) λ P I CMOS Analog Circuit Design Page 5.34 Example 5.33 Design of a Cascode Amplifier The specifications for a cascode amplifier are = 5V, P diss = mw, A v = 50V/V, (max) = 4V, and (min) =.5V. The slew rate with a 0pF load should be 0V/µs or greater. Solution The slew rate requires a current greater than 00µA while the power dissipation requires a current less than 00µA. Let us compromise with a current of 50µA. We will first begin with M3. W 3 I L = 3 K P [ (max)] = 50 50() = 6 From this find V GG3 : V GG3 = V TP I K P (W 3 /L 3 ) = = 3V W Next, L = (A v λ) I K = ( ) (50) N 0 =.73 To design W /L, we will first calculate V DS (sat) and use the (min) specification to define V DS (sat). I V DS (sat) = K N (W /L ) = = 0.8V Subtracting this value from.5v gives V DS (sat) = 0.7V. W L = I K N V DS (sat) = Finally, V GG = V DS (sat) = 5.57 I K N (W /L ) V TN = 0.8V 0.7V 0.7V =.V

32 CMOS Analog Circuit Design Page 5.4 SECTION 5.4 CURRENT AMPLIFIERS What is a Current Amplifier? An amplifier that has a defined outputinput current relationship Low input resistance High output resistance Application of current amplifiers: ii i i i i i o i o A i is RS A i i S RS Current Amplifier RL Current Amplifier R L Singleended input. Differential input. Fig. 5.4 R S >> R in and R out >> R L Advantages of current amplifiers: Currents are not restricted by the power supply voltages so that wider dynamic ranges are possible with lower power supply voltages. 3dB bandwidth of a current amplifier using negative feedback is independent of the closed loop gain. CMOS Analog Circuit Design Page 5.4 Frequency Response of a Current Amplifier with Current Feedback Consider the following current amplifier with resistive negative feedback applied. Assuming that the smallsignal resistance looking into the current amplifier is much less than R or R, R i A i v in v i o = A i (i i ) = A i R i in o Solving for i o gives i o = A i v in A i R v out = R i o = R A i R A v i in A o If A i (s) = s, then v out v = R ω in R A = R R A o s A i (s) = R A o R ω (A o ) A ω 3dB = ω A (A o ) Amplitude The unitygainbandwidth is GB = R R A o A ω o A (A o ) = R R (ω A A o ) = R R R R GB i A o 0dB i R i o Fig. 5.4 v out s ω A (A o ) A o ω A (A o ) ω A GB=(R /R )(A o ω A ) ω

33 CMOS Analog Circuit Design Page 5.43 Current Amplifier using the Simple Current Mirror i in I I i out i in i out R Current Amplifier R in = g R out = m λ I o and A i = W /L W /L. Frequency response: p = (g m g ds ) C C = (g m g ds ) C bd C gs C gs C gd C v R L in g m v in r ds C g m v in rds C 0 3 g m C bd C gs C gs C gd Note that the bandwidth can be almost doubled by including the resistor, R. (R removes C gs from p ) Fig CMOS Analog Circuit Design Page 5.44 Example 5.4 Performance of a Simple Current Mirror as a Current Amplifier Find the smallsignal current gain, A i, the input resistance, R in, the output resistance, R out, and the 3dB frequency in Hertz for the current amplifier of Fig. 5.43(a) if 0I = I = 00µA and W /L = 0W /L = 0µm/µm. Assume that C bd = 0fF, C gs = C gs = 00fF, and C gs = 50fF. Solution Ignoring channel modulation and mismatch effects, the smallsignal current gain, A i = W /L W /L 0A/A. The smallsignal input resistance, R in, is approximately /g m and is R in K N (/)0µA = 46.9µS =.3kΩ The smallsignal output resistance is equal to R out = λ N I = 50kΩ. The 3dB frequency is ω 3dB = 46.9µS 60fF = 80.4x06 radians/sec. f 3dB = 8.7 MHz

34 CMOS Analog Circuit Design Page 5.45 SelfBiased Cascode Current Mirror Implementation of a Current Amplifier i in R I I i out v in M3 M4 v out R in R Current Amplifier Fig g m, R out r ds g m4 r ds4, and A i = W /L W /L CMOS Analog Circuit Design Page 5.46 Example 5.4 Current Amplifier Implemented by the SelfBiased, Cascode Current Mirror Assume that I and I of the selfbiased cascode current mirror are 00µA. R has been designed to give a V ON of 0.V. Thus R = kω. Find the value of R in, R out, and A i if the W/L ratios of all transistors are 8µm/µm. Solution The input resistance requires g m which is = ms R in 000Ω 500Ω =.5kΩ From our knowledge of the cascode configuration, the small signal output resistance should be R out g m4 r ds4 r ds = (00µS)(50kΩ)(50kΩ) = 5MΩ Because V DS = V DS, the smallsignal current gain is A i = W /L W /L = Simulation results using the level model for this example give R in =.497kΩ R out = 64.7MΩ and A i =.000 A/A.

35 CMOS Analog Circuit Design Page 5.47 LowInput Resistance Current Amplifier To decrease R in below /g m requires the use of negative, shunt feedback. Consider the following example. i in I I iout I 3 M3 V GG3 i in i = 0 g m3 v gs3 v in v gs3 r v ds3 gs g m v gs r ds Fig Current Amplifier Feedback concept: Input resistance without feedback r ds. g m g m3 Loop gain g ds g assuming that the resistances of I ds3 and I 3 are very large. R in (no fb.) R in = Loop gain r ds g m r ds g m3 r = ds3 g m g m3 r ds3 Small signal analysis: i in = g m v gs g ds v gs3 and v gs3 = v in v gs = v in (g m3 v gs3 r ds3 ) = v in (g m3 r ds3 ) i in = g m (g m3 r ds3 )v in g ds v in g m g m3 r ds3 v in R in g m g m3 r ds3 CMOS Analog Circuit Design Page 5.48 DifferentialInput, Current Amplifiers Definitions for the differentialmode, i ID, and commonmode, i IC, input currents of the differentialinput current amplifier. i IC i ID i IC i i io Fig i O = A ID i ID ± A IC i IC = A ID (i i ) ± A i i IC Implementations: i i I I I i O i M3 M4 i i M3 M4 i O i i V GG M5 V GG M6 Fig. 5.47

36 CMOS Analog Circuit Design Page 5.49 Summary Current amplifiers have a low input resistance, high output resistance, and a defined outputinput current relationship Input resistances less than /g m require feedback However, all feedback loops have internal poles that cause the benefits of negative feedback to vanish at high frequencies. In addition, these feedback loops can have a slow time constant from a polezero pair. Voltage amplifiers using a current amplifier have high values of gainbandwidth Current amplifiers are useful at low power supplies and for switched current applications CMOS Analog Circuit Design Page 5.5 SECTION 5.5 OUTPUT AMPLIFIERS General Considerations of Output Amplifiers Requirements:.) Provide sufficient output power in the form of voltage or current..) Avoid signal distortion. 3.) Be efficient 4.) Provide protection from abnormal conditions (short circuit, over temperature, etc.) Types of Output Amplifiers:.) Class A amplifiers.) Source followers 3.) Pushpull amplifiers 4.) Substrate BJT amplifiers 5.) Amplifiers using negative shunt feedback

37 CMOS Analog Circuit Design Page 5.5 Class A Amplifiers Current source load inverter: V GG IQ i D i OUT V SS R L I Q i D R L dominates as the load line v IN C L V SS R L V SS I Q R L I Q R L Fig. 5.5 A Class A circuit has current flow in the MOSFETs during the entire period of a sinusoidal signal. Characteristics of Class A amplifiers: Unsymmetrical sinking and sourcing Linear Poor efficiency (peak) P RL R L Efficiency = P = Supply ( V SS )I = Q (peak) R L (peak) = ( V SS ) V DD V SS ( V SS ) R L Maximum efficiency occurs when (peak) = = V SS which gives 5%. CMOS Analog Circuit Design Page 5.53 Specifying the Performance of a Class A Amplifier Output resistance: r out = g ds g = ds (λ λ )I D Current: Maximum sinking current is, I ŌUT = K' W L (V DD V SS V T ) I Q Maximum sourcing current is, I OUT = K' W L (V DD V GG V T ) I Q Requirements: Want r out << R L I OUT > C L SR I OUT > (peak) R L The maximum current will be determined by both the current required to provide the necessary slew rate (C L ) and the current required to provide a voltage across the load resistor (R L ).

38 CMOS Analog Circuit Design Page 5.54 SmallSignal Performance of the Class A Amplifier Although we have considered the smallsignal performance of the Class A amplifier as the current source load inverter, let us include the influence of the load. The modified smallsignal model: The smallsignal voltage gain is: v out v in = g m g ds g ds G L C v in g m v in rds r ds R L The smallsignal frequency response includes: A zero at z = g m C gd and a pole at (g ds g ds G L ) p = C gd C gd C bd C bd C L C vout Fig. 5.5 CMOS Analog Circuit Design Page 5.55 Example 5.5 Design of a Simple ClassA Output Stage Use the values of Table 3. and design the W/L ratios of and so that a voltage swing of ± volts and a slew rate of volt/µs is achieved if R L = 0 kω and C L = 000 pf. Assume that = V SS = 3 volts and V GG = 0 volts. Let the channel lengths be µm and assume that C gd = 00fF. Solution Let us first consider the effects of R L and C L. i OUT (peak) = ±V 0kΩ = ±00µA and CL SR = = 000µA Since the slew rate current is so much larger than the current needed to meet the voltage specification across R L, we can safely assume that all of the current supplied by the inverter is available to charge C L. Using a value of ± ma, W (I OUT I Q ) L = K N ( V SS V TN ) = (5.3) 3µm µm and W I OUT L = K P ( V GG V TP ) = (.3) 5µm µm The smallsignal performance of this amplifier is, A v = 8. V/V (includes R L = 0kΩ) The roots are, Zero = g m /C gd.59ghz and r out = 50kΩ Pole = /[(R L r out )C L )].4kHz

39 CMOS Analog Circuit Design Page 5.56 Broadband Harmonic Distortion The linearity of an amplifier can be characterized by its influence on a pure sinusoidal input signal. Assume the input is, V in (ω) = V p sin(ωt) The output of an amplifier with distortion will be V out (ω) = a V p sin (ωt) a V p sin (ωt)... an V p sin(nωt) Harmonic distortion (HD) for the ith harmonic can be defined as the ratio of the magnitude of the ith harmonic to the magnitude of the fundamental. For example, secondharmonic distortion would be given as HD = a a Total harmonic distortion (THD) is defined as the square root of the ratio of the sum of all of the second and higher harmonics to the magnitude of the first or fundamental harmonic. Thus, THD can be expressed as THD = [a a3... an] / a The distortion of the class A amplifier is good for small signals and becomes poor at maximum output swings because of the nonlinearity of the voltage transfer curve for largesignal swing CMOS Analog Circuit Design Page 5.57 Source Follower Two types of source followers: v IN V SS i OUT vout v IN V GG V SS i OUT vout V SS Source follower with a MOS diode load. Large signal considerations: V SS Source Follower with a currentsink load. Fig (min) V SS and (max) = V T V ON V T But, we need to include the bulk effect on V T : V T = V T0 γ φ F v BS φ F V T0 γ v SB = V T0 γ (max) V SS (max) V SS V T0 γ (max) V SS or putting this equation in quadratic form, (max) V SS γ (max) V SS ( V T0 ) = 0 Solving the quadratic gives, (max) γ 4 V T0 γ γ 4( V SS V T0 ) Therefore if = V SS =.5V, then (max) =.46V