RF Power Field Effect Transistor N- Channel Enhancement- Mode Lateral MOSFET

Transcription

1 Technical Data RF Power Field Effect Transistor N- Channel Enhancement- Mode Lateral MOSFET Designed primarily for wideband applications with frequencies up to 0 MHz. Device is unmatched and is suitable for use in broadcast applications. Typical DVBT OFDM Performance: V DD = 50 Volts, I DQ = 2600 ma, P out = 1 Watts Avg., f = 2 MHz, Channel Bandwidth = 7.61 MHz, Input Signal PAR = % Probability on CCDF. Power Gain db Drain Efficiency 28.5% 4 MHz Offset khz Bandwidth Typical Pulsed Performance: V DD = 50 Volts, I DQ = 2600 ma, P out = 600 Watts Peak, f = 2 MHz, Pulse Width = 0 μsec, Duty Cycle = 20% Power Gain.3 db Drain Efficiency 59% Capable of Handling 5:1 50 Vdc, 2 MHz, 1 Watts CW Power; :1 50 Vdc, 2 MHz, 600 Watts Peak Power, Pulse Width = 0 μsec, Duty Cycle = 20% Features Integrated ESD Protection Excellent Thermal Stability Designed for Push- Pull Operation Greater Negative Gate- Source Voltage Range for Improved Class C Operation RoHS Compliant In Tape and Reel. R6 Suffix = 150 Units per 56 mm, 13 inch Reel. Document Number: MRF6VP2600H Rev. 0, 3/ MHz, 600 W, 50 V LATERAL N- CHANNEL BROADBAND RF POWER MOSFET CASE 375D-05, STYLE 1 NI PART IS PUSH-PULL RF ina /V GSA 3 1 RF outa /V DSA RF inb /V GSB 4 2 RF outb /V DSB Table 1. Maximum Ratings Rating Symbol Value Unit Drain-Source Voltage V DSS -0.5, +1 Vdc Gate-Source Voltage V GS -6.0, + Vdc Storage Temperature Range T stg - 65 to +150 C Case Operating Temperature T C 150 C Operating Junction Temperature T J 200 C Table 2. Thermal Characteristics (Top View) Figure 1. Pin Connections Characteristic Symbol Value (1,2) Unit Thermal Resistance, Junction to Case Case Temperature 99 C, 1 W CW R θjc 0.20 C/W 1. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. 2. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to Select Documentation/Application Notes - AN1955., Inc., All rights reserved. 1

2 Table 3. ESD Protection Characteristics Test Methodology Human Body Model (per JESD22- A114) Machine Model (per EIA/JESD22- A115) Charge Device Model (per JESD22- C1) Class 2 (Minimum) A (Minimum) IV (Minimum) Table 4. Electrical Characteristics (T C = C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Off Characteristics (1) Gate- Source Leakage Current (V GS = 5 Vdc, V DS = 0 Vdc) I GSS μadc Drain- Source Breakdown Voltage (I D = 150 ma, V GS = 0 Vdc) Zero Gate Voltage Drain Leakage Current (V DS = 50 Vdc, V GS = 0 Vdc) Zero Gate Voltage Drain Leakage Current (V DS = 0 Vdc, V GS = 0 Vdc) On Characteristics Gate Threshold Voltage (1) (V DS = Vdc, I D = 800 μadc) Gate Quiescent Voltage (2) (V DD = 50 Vdc, I D = 2600 madc, Measured in Functional Test) Drain-Source On-Voltage (1) (V GS = Vdc, I D = 2 Adc) Dynamic Characteristics (1) Reverse Transfer Capacitance (V DS = 50 Vdc ± 30 1 MHz, V GS = 0 Vdc) Output Capacitance (V DS = 50 Vdc ± 30 1 MHz, V GS = 0 Vdc) Input Capacitance (V DS = 50 Vdc, V GS = 0 Vdc ± 30 1 MHz) V (BR)DSS 1 Vdc I DSS 50 μadc I DSS 2.5 ma V GS(th) Vdc V GS(Q) Vdc V DS(on) 0. Vdc C rss 1.7 pf C oss 1 pf C iss 287 pf Functional Tests (2) (In Freescale Test Fixture, 50 ohm system) V DD = 50 Vdc, I DQ = 2600 ma, P out = 1 W Avg., f = 2 MHz, DVBT OFDM Single Channel. ACPR measured in 7.61 MHz Channel ±4 MHz Offset. Power Gain G ps db Drain Efficiency η D % Adjacent Channel Power Ratio ACPR dbc Input Return Loss IRL db 1. Each side of device measured separately. 2. Measurement made with device in push- pull configuration. 2

3 V BIAS B1 L3 L2 R1 V SUPPLY + C16 + C15 + C14 C13 C12 C11 C9 C8 C7 C C6 C19 C17 L4 C18 C20 C21 C22 + C23 + C24 + C RF INPUT Z1 C1 Z2 L1 Z3 Z4 C2 J1 Z5 Z6 Z7 Z8 Z9 DUT Z Z11 Z12 Z13 Z14 Z15 C3 Z16 Z17 C4 Z18 J2 Z19 Z20 C5 RF OUTPUT T1 T2 Z x Microstrip Z2* x Microstrip Z3* x Microstrip Z x Microstrip Z5, Z x Microstrip Z7, Z x Microstrip Z9, Z x Microstrip Z11, Z x Microstrip Z13, Z x 0.3 Microstrip Z15*, Z16* x 0.3 Microstrip Z17, Z x 0.3 Microstrip Z x Microstrip Z x Microstrip PCB Arlon CuClad 0GX , 0.030, ε r = 2.55 * Line length includes microstrip bends Figure 2. Test Circuit Schematic Table 5. Test Circuit Component Designations and Values Part Description Part Number Manufacturer B1 95 Ω, 0 MHz Long Ferrite Bead Fair- Rite C1 47 pf Chip Capacitor ATC0B470JT500XT ATC C2, C4 43 pf Chip Capacitors ATC0B430JT500XT ATC C3 0 pf Chip Capacitor ATC0B1JT500XT ATC C5 pf Chip Capacitor ATC0B7R5CT500XT ATC C6, C9 2.2 μf, 50 V Chip Capacitors C18C2J5RAC Kemet C7, C13, C20 K pf Chip Capacitors ATC200B3KT50XT ATC C8 220 nf, 50 V Chip Capacitor C1812C224J5RAC Kemet C, C17, C18 00 pf Chip Capacitors ATC0B2JT50XT ATC C11, C μf, 50 V Chip Capacitors CDR33BX4AKYS Kemet C12, C21 20K pf Chip Capacitors ATC200B203KT50XT ATC C14 μf, 35 V Tantalum Capacitor T491D6K035AT Kemet C15 22 μf, 35 V Tantalum Capacitor T491X226K035AT Kemet C16 47 μf, 50 V Electrolytic Capacitor 476KXM050M Illinois Cap C μf, Chip Capacitor 22X7R2KT3AB ATC C23, C24, C 470 μf 63V Electrolytic Capacitors EKME630ELL471MKS Multicomp J1, J2 Jumpers from PCB to T1 & T2 Copper Foil L nh 6 Turn Inductor B06T CoilCraft L2 8 Turn, #20AWG ID = 0.1 Inductor, Handwound Copper Wire L3 82 nh Inductor 1812SMS- 82NJ CoilCraft L4* 9 Turn, #18AWG Inductor, Handwound Copper Wire R1 20 Ω, 3 W Axial Leaded Resistor 5093NW20R00J Vishay T1 Balun TUI- 9 Comm Concepts T2 Balun TUO- 4 Comm Concepts *L4 is wrapped around R1. 3

4 C16 + C15 C14 C9 C8 C7 C6 B1 L3 L2 C C13 C12 C11 T1 L4, R1* C22 C21 C20 C18 C17 T2 - C23 C24 - C19 C - J1 C4 J2 C1 L1 C2 CUT OUT AREA C3 (on side) C5 MRF6VP2600H 2 MHz Rev. 3 * L4 is wrapped around R1. Figure 3. Test Circuit Component Layout 4

5 TYPICAL CHARACTERISTICS 00 0 C, CAPACITANCE (pf) 0 C oss C rss C iss Measured with ±30 1 MHz V GS = 0 Vdc I D, DRAIN CURRENT (AMPS) T J = 150 C T J = 200 C T J = 175 C V DS, DRAIN SOURCE VOLTAGE (VOLTS) Figure 4. Capacitance versus Drain- Source Voltage T C = C V DS, DRAIN SOURCE VOLTAGE (VOLTS) Figure 5. DC Safe Operating Area G ps, POWER GAIN (db) V DD = 50 Vdc, I DQ = 2600 ma f = 2 MHz Pulse Width = 0 μsec Duty Cycle = 20% 23 0 G ps η D P out, OUTPUT POWER (WATTS) PULSED Figure 6. Pulsed Power Gain and Drain Efficiency versus Output Power 20 η D, DRAIN EFFICIENCY (%) P out, OUTPUT POWER (dbm) P3dB = 59.7 dbm (938 W) P2dB = 59.1 dbm (827 W) P1dB = 53.3 dbm (670 W) P in, INPUT POWER (dbm) Ideal Actual V DD = 50 Vdc, I DQ = 2600 ma, f = 2 MHz Pulse Width = 12 μsec, Duty Cycle = 1% Figure 7. Pulsed CW Output Power versus Input Power G ps, POWER GAIN (db) V 23 V DD = 50 Vdc I DQ = 2600 ma 35 V 22 f = 2 MHz Pulse Width = 0 μsec Duty Cycle = 20% V DD = 30 V P out, OUTPUT POWER (WATTS) PULSED Figure 8. Pulsed Power Gain versus Output Power 50 V 45 V G ps, POWER GAIN (db) C 85 C T C = 30 C V DD = 50 Vdc, I DQ = 2600 ma f = 2 MHz Pulse Width = 0 μsec Duty Cycle = 20% G ps 0 00 P out, OUTPUT POWER (WATTS) PULSED Figure 9. Pulsed Power Gain and Drain Efficiency versus Output Power η D η D, DRAIN EFFICIENCY (%) 5

6 TYPICAL CHARACTERISTICS TWO- TONE IMD, INTERMODULATION DISTORTION (dbc) V DD = 50 Vdc, I DQ = 2600 ma, f1 = 222 MHz f2 = 228 MHz, Two Tone Measurements 3rd Order 5th Order 7th Order IMD, INTERMODULATION DISTORTION (dbc) V DD = 50 Vdc, P out = 500 W (PEP), I DQ = 2600 ma Two Tone Measurements 3rd Order 5th Order 7th Order 1 40 P out, OUTPUT POWER (WATTS) PEP TWO TONE SPACING (MHz) Figure. Intermodulation Distortion Products versus Output Power Figure 11. Intermodulation Distortion Products versus Tone Spacing G ps, POWER GAIN (db) ma I DQ = 2600 ma 2300 ma 2000 ma 1800 ma V DD = 50 Vdc, f1 = 222 MHz, f2 = 228 MHz Two Tone Measurements, 6 MHz Tone Spacing P out, OUTPUT POWER (WATTS) PEP Figure 12. Two- Tone Power Gain versus Output Power IMD, THIRD ORDER INTERMODULATION DISTORTION (dbc) V DD = 50 Vdc, f1 = 222 MHz, f2 = 228 MHz Two Tone Measurements, 6 MHz Tone Spacing I DQ = 1300 ma 1800 ma 2600 ma ma 2300 ma P out, OUTPUT POWER (WATTS) PEP Figure 13. Third Order Intermodulation Distortion versus Output Power 700 6

7 TYPICAL CHARACTERISTICS OFDM PROBABILITY (%) K Mode DVTB OFDM 64 QAM Data Carrier Modulation 5 Symbols PEAK TO AVERAGE (db) Figure 14. Single- Carrier DVTB OFDM 12 (db) khz BW 7.61 MHz ACPR Measured at 4 MHz Offset from Center Frequency f, FREQUENCY (MHz) 4 khz BW 8K Mode DVTB OFDM 64 QAM Data Carrier Modulation, 5 Symbols Figure 15. 8K Mode DVBT OFDM Spectrum 5 G ps, POWER GAIN (db) I DQ = 2600 ma 2300 ma 2000 ma 1800 ma 1300 ma V DD = 50 Vdc, f = 2 MHz 8K Mode OFDM, 64 QAM Data Carrier Modulation, 5 Symbols P out, OUTPUT POWER (WATTS) AVG. Figure 16. Single- Carrier DVBT OFDM Power Gain versus Output Power ACPR, ADJACENT CHANNEL POWER RATIO (dbc) V DD = 50 Vdc, f = 2 MHz 8K Mode OFDM, 64 QAM Data Carrier Modulation, 5 Symbols I DQ = 1300 ma 1800 ma 2000 ma 2300 ma 2600 ma P out, OUTPUT POWER (WATTS) AVG. Figure 17. Single- Carrier DVBT OFDM ACPR versus Output Power η D, DRAIN EFFICIENCY (%), G ps, POWER GAIN (db) C 30 C ACPR 85 C η D C T C = 30 C G ps C V DD = 50 Vdc, I DQ = 2600 MHz 20 f = 2 MHz, 8K Mode OFDM QAM Data Carrier Modulation 15 5 Symbols P out, OUTPUT POWER (WATTS) AVG. Figure 18. Single- Carrier DVBT OFDM ACPR Power Gain and Drain Efficiency versus Output Power ACPR, ADJACENT CHANNEL POWER RATIO (dbc) 7

8 TYPICAL CHARACTERISTICS MTTF (HOURS) 7 MTTF (HOURS) T J, JUNCTION TEMPERATURE ( C) T J, JUNCTION TEMPERATURE ( C) This above graph displays calculated MTTF in hours when the device is operated at V DD = 50 Vdc, P out = 1 W Avg., and η D = 28.5%. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. Figure 19. MTTF versus Junction Temperature - CW This above graph displays calculated MTTF in hours when the device is operated at V DD = 50 Vdc, P out = 600 W Peak, Pulse Width = 0 μsec, Duty Cycle = 20%, and η D = 59%. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. Figure 20. MTTF versus Junction Temperature - Pulsed 8

9 Z source f = 2 MHz Z o = Ω Z load f = 2 MHz V DD = 50 Vdc, I DQ = 2600 ma, P out = 1 W Avg. f MHz Z source Z load j j1.85 Z source = Test circuit impedance as measured from gate to ground. Z load = Test circuit impedance as measured from drain to ground. Input Matching Network + Device Under Test Output Matching Network + Z source Z load Figure 21. Series Equivalent Source and Load Impedance 9

10 C1 B1 C19 C4 C5 C6 C17 C16 C15 C18 C20 C2 C3 L1 L6, R1* C7 C8 C9 C11 L2 J1 C T1 L4 C22 C14 C13 C T2 J2 C21 L3 C12 L5 C23 C24 C26 MRF6VP2600H 88 8 MHz Rev. 1 * L6 is wrapped around R1. Figure 22. Test Circuit Component Layout 88-8 MHz

11 Table 6. Test Circuit Component Designations and Values 88-8 MHz Part Description Part Number Manufacturer B1 95 Ω, 0 MHz Long Ferrite Bead Fair- Rite C1 47 μf, 50 V Electrolytic Capacitor 476KXM050M Illinois Cap C2 22 μf, 35 V Tantalum Capacitor T491X226K035AT Kemet C3 μf, 35 V Tantalum Capacitor T491D6K035AT Kemet C4, C9, C15 K pf Chip Capacitors ATC200B3KT50XT ATC C5, C16 20K pf Chip Capacitors ATC200B203KT50XT ATC C6, C μf, 50 V Chip Capacitors CDR33BX4AKYS AVX C7, C μf, 50 V Chip Capacitors C18C2J5RAC Kemet C8 220 nf, 50 V Chip Capacitor C1812C224J5RAC Kemet C, C13, C14 00 pf Chip Capacitors ATC0B2JT50XT ATC C12 33 pf Chip Capacitor ATC0B330JT500XT ATC C18, C19, C μf, 63 V Electrolytic Capacitors EKME630ELL471MKS MultiComp C μf, 0 V Chip Capacitor G22X7R2KT3AB ATC C22, C pf, Chip Capacitors ATC0B121JT500XT ATC C pf Chip Capacitor ATC0B151JT500XT ATC C 0 pf Chip Capacitor ATC0B1JT500XT ATC C26 15 pf Chip Capacitor ATC0B150JT500XT ATC J1, J2 Jumpers from PCB to T1 & T2 Copper Foil L1 82 nh Inductor 1812SMS- 82NJ CoilCraft L2 8 Turn, #20AWG ID = 0.1 Inductor, Handwound Copper Wire L3 120 nh Inductor 1812SMS- R12J CoilCraft L4, L nh 4 Turn Inductor A04T CoilCraft L6* 9 Turn, #18AWG Inductor, Handwound Copper Wire R1 20 Ω, 3 W Axial Leaded Resistor 5093NW20R00J Vishay T1 Balun Transformer TUI- 9 Comm Concepts T2 Balun Transformer TUO- 9 Comm Concepts *L6 is wrapped around R1. 11

12 TYPICAL CHARACTERISTICS 88-8 MHz G ps, POWER GAIN (db) V DD = 50 Vdc 27 I DQ = 150 ma G ps 70 Pulse Width = 0 μsec 26 Duty Cycle = 20% MHz 98 MHz 8 MHz 8 MHz 98 MHz 88 MHz η D η D, DRAIN EFFICIENCY (%) 21 0 P out, OUTPUT POWER (WATTS) PULSED 00 Figure 23. Broadband Pulsed Power Gain and Drain Efficiency versus Output Power 88-8 MHz G ps, POWER GAIN (db) V DD = 50 Vdc, P out = 600 W Peak, I DQ = 150 ma 28.5 Pulse Width = 0 μsec, Duty Cycle = 20% η 27.5 D IRL G ps f, FREQUENCY (MHz) 45 8 Figure 24. Pulsed Power Gain, Drain Efficiency and IRL versus Frequency 88-8 MHz η D, DRAIN EFFICIENCY (%) IRL, INPUT RETURN LOSS (db) η D, DRAIN EFFICIENCY (%), G ps, POWER GAIN (db) 40 V DD = 50 Vdc, I DQ = 2600 ma η D 55 8K Mode OFDM, 64 QAM Data 88 MHz 35 Carrier Modulation, 5 Symbols 98 MHz 8 MHz MHz 98 MHz G ps MHz ACPR 98 MHz 8 MHz 88 MHz P out, OUTPUT POWER (WATTS) AVG. Figure. Single- Carrier DVBT OFDM ACPR, Power Gain and Drain Efficiency versus Output Power 88-8 MHz 65 ACPR, ADJACENT CHANNEL POWER RATIO (dbc) 12

13 TYPICAL CHARACTERISTICS 88-8 MHz V DD = 50 Vdc, I DQ = 150 ma 70 G ps, POWER GAIN (db) 28 η D G ps IRL η D, DRAIN EFFICIENCY (%) IRL, INPUT RETURN LOSS (db) f, FREQUENCY (MHz) Figure 26. CW Power Gain, Drain Efficiency and IRL versus Frequency 88-8 MHz 13

14 Z source f = 8 MHz f = 88 MHz Z o = Ω f = 88 MHz Z load f = 8 MHz V DD = 50 Vdc, I DQ = 2600 ma, P out = 1 W Avg. f MHz Z source Z load j j j j j j3.18 Z source = Test circuit impedance as measured from gate to ground. Z load = Test circuit impedance as measured from drain to ground. Input Matching Network + Device Under Test Output Matching Network + Z source Z load Figure 27. Series Equivalent Source and Load Impedance 88-8 MHz 14

15 PACKAGE DIMENSIONS 15

16 16

17 PRODUCT DOCUMENTATION Refer to the following documents to aid your design process. Application Notes AN1955: Thermal Measurement Methodology of RF Power Amplifiers Engineering Bulletins EB212: Using Data Sheet Impedances for RF LDMOS Devices The following table summarizes revisions to this document. REVISION HISTORY Revision Date Description 0 Mar Initial Release of Data Sheet 17

18 How to Reach Us: Home Page: Web Support: USA/Europe or Locations Not Listed:, Inc. Technical Information Center, EL East Elliot Road Tempe, Arizona or Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen Muenchen, Germany (English) (English) (German) (French) Japan: Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo Japan or support.japan@freescale.com Asia/Pacific: Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong support.asia@freescale.com For Literature Requests Only: Literature Distribution Center P.O. Box 5405 Denver, Colorado or Fax: LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. reserves the right to make changes without further notice to any products herein. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals, must be validated for each customer application by customer s technical experts. does not convey any license under its patent rights nor the rights of others. products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should Buyer purchase or use products for any such unintended or unauthorized application, Buyer shall indemnify and hold and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale and the Freescale logo are trademarks of, Inc. All other product or service names are the property of their respective owners., Inc All rights reserved. Document Number: MRF6VP2600H 18 Rev. 0, 3/2008