RF Power Field Effect Transistor N-Channel Enhancement-Mode Lateral MOSFET

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1 Technical Data RF Power Field Effect Transistor N-Channel Enhancement-Mode Lateral MOSFET Designed primarily for pulsed wideband applications with frequencies up to 150 MHz. Device is unmatched and is suitable for use in industrial, medical and scientific applications. Typical Pulsed Performance at 130 MHz: V DD = 50 Volts, I DQ = 150 ma, P out = 00 Watts Peak, Pulse Width = 0 μsec, Duty Cycle = % Power Gain 26 db Drain Efficiency 71% Capable of Handling :1 50 Vdc, 130 MHz, 00 Watts Peak Power Features Qualified Up to a Maximum of 50 V DD Operation Integrated ESD Protection Excellent Thermal Stability Designed for Push- Pull Operation Greater Negative Gate- Source Voltage Range for Improved Class C Operation RoHS Compliant In Tape and Reel. R6 Suffix = 150 Units per 56 mm, 13 inch Reel. Document Number: MRF6VP11KH Rev. 0, 1/ MHz, 00 W, 50 V LATERAL N- CHANNEL BROADBAND RF POWER MOSFET CASE 375D-05, STYLE 1 NI-1230 PART IS PUSH-PULL RF ina /V GSA 3 1 RF outa /V DSA RF inb /V GSB 4 2 RF outb /V DSB (Top View) Figure 1. Pin Connections Table 1. Maximum Ratings Rating Symbol Value Unit Drain-Source Voltage V DSS -0.5, 1 Vdc Gate-Source Voltage V GS -6.0, Vdc Storage Temperature Range T stg - 65 to 150 C Case Operating Temperature T C 150 C Operating Junction Temperature T J 0 C Table 2. Thermal Characteristics Characteristic Symbol Value (1,2) Unit Thermal Resistance, Junction to Case Case Temperature 80 C, 00 W Pulsed, 0 μsec Pulse Width, % Duty Cycle R θjc 0.03 C/W 1. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. 2. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to Select Documentation/Application Notes - AN1955., Inc., 08. All rights reserved. 1

2 Table 3. ESD Protection Characteristics Test Methodology Human Body Model (per JESD22-A114) Machine Model (per EIA/JESD22-A115) Charge Device Model (per JESD22-C1) Class 2 (Minimum) A (Minimum) IV (Minimum) Table 4. Electrical Characteristics (T C = 25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Off Characteristics (1) Gate-Source Leakage Current (V GS = 5 Vdc, V DS = 0 Vdc) I GSS μadc Drain-Source Breakdown Voltage (I D = 300 ma, V GS = 0 Vdc) Zero Gate Voltage Drain Leakage Current (V DS = 50 Vdc, V GS = 0 Vdc) Zero Gate Voltage Drain Leakage Current (V DS = 0 Vdc, V GS = 0 Vdc) On Characteristics Gate Threshold Voltage (1) (V DS = Vdc, I D = 1600 μadc) Gate Quiescent Voltage (2) (V DD = 50 Vdc, I D = 150 madc, Measured in Functional Test) Drain-Source On-Voltage (1) (V GS = Vdc, I D = 4 Adc) Dynamic Characteristics (1) Reverse Transfer Capacitance (V DS = 50 Vdc ± 30 1 MHz, V GS = 0 Vdc) Output Capacitance (V DS = 50 Vdc ± 30 1 MHz, V GS = 0 Vdc) Input Capacitance (V DS = 50 Vdc, V GS = 0 Vdc ± 30 1 MHz) V (BR)DSS 1 Vdc I DSS 0 μadc I DSS 5 ma V GS(th) Vdc V GS(Q) Vdc V DS(on) 0.28 Vdc C rss 3.3 pf C oss 147 pf C iss 506 pf Functional Tests (2) (In Freescale Test Fixture, 50 ohm system) V DD = 50 Vdc, I DQ = 150 ma, P out = 00 W Peak (0 W Avg.), f = 130 MHz, 0 μsec Pulse Width, % Duty Cycle Power Gain G ps db Drain Efficiency η D % Input Return Loss IRL db 1. Each side of device measured separately. 2. Measurement made with device in push-pull configuration. 2

3 V BIAS B1 L1 R1 R2 V SUPPLY C1 C2 C3 C4 C5 C6 C7 C8 C9 C C11 C13 L3 C14 C15 C16 C17 C18 C19 C RF INPUT Z1 L2 Z2 C12 Z3 J1 Z4 Z5 Z6 Z7 Z8 DUT Z9 C21 Z Z11 Z12 C23 Z13 Z14 C24 Z15 Z16 C25 Z17 J2 Z18 Z19 C26 RF OUTPUT T1 T2 C22 Z x Microstrip Z2* x Microstrip Z3* x Microstrip Z4, Z x Microstrip Z6, Z7, Z8, Z x Microstrip Z, Z x Microstrip Z12, Z x Microstrip Z14, Z x Microstrip Z16*, Z17* x Microstrip Z x Microstrip Z x Microstrip PCB Arlon CuClad 250GX , 0.030, ε r = 2.55 *Line length includes microstrip bends. Figure 2. Test Circuit Schematic Table 5. Test Circuit Component Designations and Values Part Description Part Number Manufacturer B1 95 Ω, 0 MHz Long Ferrite Bead Fair-Rite C1 47 μf, 50 V Electrolytic Capacitor 476KXM050M Illinois Cap C2 22 μf, 35 V Tantalum Capacitor T491X226K035AT Kemet C3 μf, 35 V Tantalum Capacitor T491D6K035AT Kemet C4, C9, C17 K pf Chip Capacitors ATC0B3KT50XT ATC C5, C16 K pf Chip Capacitors ATC0B3KT50XT ATC C6, C μf, 50 V Chip Capacitors CDR33BX4AKYS Kemet C7 2.2 μf, 50 V Chip Capacitor C1825C225J5RAC Kemet C μf, 0 V Chip Capacitor C1825C223K1GAC Kemet C, C11, C13, C14 00 pf Chip Capacitors ATC0B2JT50XT ATC C12 18 pf Chip Capacitor ATC0B180JT500XT ATC C18, C19, C 470 μf, 63 V Electrolytic Capacitors EKME630ELL471MK25S Multicomp C21, C22 47 pf Chip Capacitors ATC0B470JT500XT ATC C23 75 pf Chip Capacitor ATC0B750JT500XT ATC C24, C25 0 pf Chip Capacitors ATC0B1JT500XT ATC C26 33 pf Chip Capacitor ATC0B330JT500XT ATC J1, J2 Jumpers from PCB to T1 and T2 Copper Foil L1 82 nh Inductor 1812SMS-82NJLC CoilCraft L2 47 nh Inductor 1812SMS-47NJLC CoilCraft L3* Turn, #18AWG Inductor, Handwound Copper Wire R1 1 KΩ, 1/4 W Chip Resistor PTF561K0000BYEK Vishay R2 Ω, 3 W Chip Resistor 5093NWR00J Vishay T1 Balun TUI-9 Comm Concepts T2 Balun TUO-4 Comm Concepts *L3 is wrapped around R2. 3

4 C1 C19 B1 C4 C5 C6 C17 C16 C15 C18 C2 C3 L1 C L2 C7 C8 C9 C11 R1 C J1 C12 T1 CUT OUT AREA C21 C22 C24 C23 C14 C13 C25 T2 L3, R2* J2 C26 MRF6VP11KH Rev. 3 * L3 is wrapped around R2. Figure 3. Test Circuit Component Layout 4

5 TYPICAL CHARACTERISTICS 00 C iss 0 T J = 0 C C, CAPACITANCE (pf) 0 C rss C oss Measured with ±30 1 MHz V GS = 0 Vdc I D, DRAIN CURRENT (AMPS) T J = 150 C T J = 175 C T C = 25 C 0 0 V DS, DRAIN SOURCE VOLTAGE (VOLTS) V DS, DRAIN SOURCE VOLTAGE (VOLTS) Figure 4. Capacitance versus Drain- Source Voltage Figure 5. DC Safe Operating Area G ps, POWER GAIN (db) G ps η D V DD = 50 Vdc, I DQ = 150 ma, f = 130 MHz Pulse Width = 0 μsec, Duty Cycle = % P out, OUTPUT POWER (WATTS) PULSED η D, DRAIN EFFICIENCY (%) P out, OUTPUT POWER (dbm) P3dB = dbm ( W) P1dB = dbm ( W) P in, INPUT POWER (dbm) PULSED Ideal Actual V DD = 50 Vdc, I DQ = 150 ma, f = 130 MHz Pulse Width = 0 μsec, Duty Cycle = % 39 Figure 6. Pulsed Power Gain and Drain Efficiency versus Output Power Figure 7. Pulsed Output Power versus Input Power I DQ = 6000 ma G ps, POWER GAIN (db) ma 375 ma 3600 ma 1500 ma 750 ma V DD = 50 Vdc, f = 130 MHz Pulse Width = 0 μsec, Duty Cycle = % 0 P out, OUTPUT POWER (WATTS) PULSED Figure 8. Pulsed Power Gain versus Output Power G ps, POWER GAIN (db) V DD = 30 V 35 V 40 V 45 V 50 V I DQ = 150 ma, f = 130 MHz Pulse Width = 0 μsec Duty Cycle = % P out, OUTPUT POWER (WATTS) PULSED Figure 9. Pulsed Power Gain versus Output Power 5

6 TYPICAL CHARACTERISTICS P out, OUTPUT POWER (dbm) C T C = 30 C 85 C P in, INPUT POWER (dbm) PULSED V DD = 50 Vdc I DQ = 150 ma f = 130 MHz Pulse Width = 0 μsec Duty Cycle = % 45 G ps, POWER GAIN (db) G ps 25 C 0 T C = 30 C η D 85 C P out, OUTPUT POWER (WATTS) PULSED V DD = 50 Vdc I 30 DQ = 150 ma f = 130 MHz Pulse Width = 0 μsec Duty Cycle = % η D, DRAIN EFFICIENCY (%) Figure. Pulsed Output Power versus Input Power Figure 11. Pulsed Power Gain and Drain Efficiency versus Output Power 7 MTTF (HOURS) T J, JUNCTION TEMPERATURE ( C) This above graph displays calculated MTTF in hours when the device is operated at V DD = 50 Vdc, P out = 00 W Peak, Pulse Width = 0 μsec, Duty Cycle = %, and η D = 71%. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. Figure 12. MTTF versus Junction Temperature 250 6

7 f = 130 MHz Z source Z o = Ω f = 130 MHz Z load f MHz V DD = 50 Vdc, I DQ = 150 ma, P out = 00 W Peak Z source Z load j j1.85 Z source = Test circuit impedance as measured from gate to ground. Z load = Test circuit impedance as measured from drain to ground. Input Matching Network Device Under Test Output Matching Network Z source Z load Figure 13. Series Equivalent Source and Load Impedance 7

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10 PRODUCT DOCUMENTATION Refer to the following documents to aid your design process. Application Notes AN1955: Thermal Measurement Methodology of RF Power Amplifiers Engineering Bulletins EB212: Using Data Sheet Impedances for RF LDMOS Devices The following table summarizes revisions to this document. REVISION HISTORY Revision Date Description 0 Jan. 08 Initial Release of Data Sheet

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