RF Power Field Effect Transistor N-Channel Enhancement-Mode Lateral MOSFET

Transcription

1 Technical Data RF Power Field Effect Transistor N-Channel Enhancement-Mode Lateral MOSFET Designed for broadband commercial and industrial applications with frequencies to 5 MHz. The high gain and broadband performance of this device make it ideal for large- signal, common source amplifier applications in.5 volt mobile FM equipment. Specified 5 MHz,.5 Volts D Output Power Watts Power Gain db Efficiency % Capable of Handling : 5.5 Vdc, 5 MHz, db Overdrive Features Excellent Thermal Stability G Characterized with Series Equivalent Large- Signal Impedance Parameters N Suffix Indicates Lead- Free Terminations. RoHS Compliant. In Tape and Reel. T Suffix =, Units per mm, S 7 inch Reel. Document Number: MRF5N Rev., /9 5 MHz, W,.5 V LATERAL N- CHANNEL BROADBAND RF POWER MOSFET CASE -, STYLE PLD-.5 PLASTIC Table. Maximum Ratings Rating Symbol Value Unit Drain-Source Voltage V DSS -.5, + Vdc Gate-Source Voltage V GS ± Vdc Drain Current Continuous I D Adc Total Device T C = 5 C () Derate above 5 C P D.5.5 W W/ C Storage Temperature Range T stg - 5 to +5 C Operating Junction Temperature T J 5 C Table. Thermal Characteristics Characteristic Symbol Value () Unit Thermal Resistance, Junction to Case R θjc C/W Table. Moisture Sensitivity Level Test Methodology Rating Package Peak Temperature Unit Per JESD-A, IPC/JEDEC J-STD- C TJ TC. Calculated based on the formula P D = RθJC. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. NOTE - CAUTION - MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and packaging MOS devices should be observed., Inc., -9. All rights reserved.

2 Table. Electrical Characteristics (T A = 5 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Off Characteristics Zero Gate Voltage Drain Current (V DS = Vdc, V GS = Vdc) Gate-Source Leakage Current (V GS = Vdc, V DS = Vdc) On Characteristics Gate Threshold Voltage (V DS =.5 Vdc, I D = μa) Drain-Source On-Voltage (V GS = Vdc, I D = Adc) Dynamic Characteristics Input Capacitance (V DS =.5 Vdc, V GS =, f = MHz) Output Capacitance (V DS =.5 Vdc, V GS =, f = MHz) Reverse Transfer Capacitance (V DS =.5 Vdc, V GS =, f = MHz) Functional Tests (In Freescale Test Fixture) Common-Source Amplifier Power Gain (, P out = Watts, I DQ = 5 ma, f = 5 MHz) Drain Efficiency (, P out = Watts, I DQ = 5 ma, f = 5 MHz) I DSS μadc I GSS μadc V GS(th).. Vdc V DS(on). Vdc C iss pf C oss pf C rss.5 pf G ps db η %

3 V GG C C7 + C R B R C B C5 C + C V DD RF INPUT N C Z C Z C Z R C Z R Z5 DUT C5 Z L Z7 Z Z9 Z C9 C C C N RF OUTPUT B, B Short Ferrite Beads, Fair Rite Products (7) C, C pf, mil Chip Capacitors C, C, C, C to pf Trimmer Capacitors C pf, mil Chip Capacitor C5, C pf, mil Chip Capacitors C, C μf, 5 V Electrolytic Capacitors C7, C, pf, mil Chip Capacitors C, C5. F, mil Chip Capacitors C9 pf, mil Chip Capacitor L 55.5 nh, 5 Turn, Coilcraft N, N Type N Flange Mounts R 5 Ω Chip Resistor (5) R 5 Ω, / W Resistor R Ω Chip Resistor (5) R kω, / W Resistor Z.5 x. Microstrip Z.5 x. Microstrip Z. x. Microstrip Z.55 x. Microstrip Z5, Z. x. Microstrip Z7.5 x. Microstrip Z. x. Microstrip Z9. x. Microstrip Z. x. Microstrip Board Glass Teflon, mils, oz. Copper Figure. 5-5 MHz Broadband Test Circuit TYPICAL CHARACTERISTICS, 5-5 MHz 7 MHz 5 MHz 5 MHz 5 MHz P in, INPUT POWER (WATTS) IRL, INPUT RETURN LOSS (db) MHz 7 MHz 5 MHz 5 MHz P out Figure. Output Power versus Input Power Figure. Input Return Loss versus Output Power

4 TYPICAL CHARACTERISTICS, 5-5 MHz GAIN (db) MHz 5 MHz 7 MHz 5 MHz P out 7 5 MHz 7 MHz 5 5 MHz 5 MHz P out Figure. Gain versus Output Power Figure 5. Drain Efficiency versus Output Power 7 MHz 5 MHz 5 MHz 5 MHz P in =. dbm I DQ, BIASING CURRENT (ma) 7 7 MHz 5 5 MHz MHz 5 MHz P in =. dbm I DQ, BIASING CURRENT (ma) Figure. Output Power versus Biasing Current Figure 7. Drain Efficiency versus Biasing Current MHz 5 MHz MHz 5 5 MHz 55 5 MHz 5 5 MHz 5 MHz 5 MHz 5 I DQ = 5 ma I DQ = 5 ma P in =. dbm 5 P in =. dbm V DD, SUPPLY VOLTAGE (VOLTS) V DD, SUPPLY VOLTAGE (VOLTS) Figure. Output Power versus Supply Voltage Figure 9. Drain Efficiency versus Supply Voltage

5 V GG B + C C7 C C5 B V DD + C C C C5 R L RF INPUT N L C Z C Z Z C Z C DUT Z5 Z C9 Z7 C Z C N RF OUTPUT B, B Long Ferrite Beads, Fair Rite Products C, C9 pf, mil Chip Capacitors C. pf, mil Chip Capacitor C, C pf, mil Chip Capacitors C5 5 pf, mil Chip Capacitor C, C pf, mil Chip Capacitors C7, C.9 μf, mil Chip Capacitors C μf, V Tantalum Chip Capacitor C pf, mil Chip Capacitor C, C 5 pf, mil Chip Capacitors C5 μf, 5 V Tantalum Chip Capacitor L, L.5 nh, 5 Turn, Coilcraft N, N Type N Flange Mounts R 7 Ω Chip Resistor (5) Z.5 x. Microstrip Z.7 x. Microstrip Z.5 x. Microstrip Z.5 x. Microstrip Z5. x. Microstrip Z. x. Microstrip Z7. x. Microstrip Z.759 x. Microstrip Board Glass Teflon, mils, oz. Copper Figure. - 5 MHz Broadband Test Circuit TYPICAL CHARACTERISTICS, - 5 MHz. MHz MHz 5 MHz MHz P in, INPUT POWER (WATTS) IRL, INPUT RETURN LOSS (db) 5 MHz MHz MHz MHz P out Figure. Output Power versus Input Power Figure. Input Return Loss versus Output Power 5

6 TYPICAL CHARACTERISTICS, - 5 MHz GAIN (db) MHz MHz MHz MHz P out 7 5 MHz MHz 5 MHz MHz P out Figure. Gain versus Output Power Figure. Drain Efficiency versus Output Power MHz MHz 5 MHz MHz I DQ, BIASING CURRENT (ma) MHz MHz MHz MHz I DQ, BIASING CURRENT (ma) Figure 5. Output Power versus Biasing Current Figure. Drain Efficiency versus Biasing Current MHz MHz MHz 5 MHz 75 MHz MHz 55 MHz 5 5 MHz V DD, SUPPLY VOLTAGE (VOLTS) V DD, SUPPLY VOLTAGE (VOLTS) Figure 7. Output Power versus Supply Voltage Figure. Drain Efficiency versus Supply Voltage

7 V GG C C9 + C R B R C B C7 C + C5 V DD RF INPUT N C Z Z Z Z C C C C5 R C Z5 R Z DUT C7 Z7 L Z Z9 Z Z C C C C N RF OUTPUT B, B Short Ferrite Beads, Fair Rite Products (7) C, C pf, mil Chip Capacitors C, C, C, C, C, C to pf Trimmer Capacitors C5 pf, mil Chip Capacitor C 7 pf, mil Chip Capacitor C7, C pf, mil Chip Capacitors C, C5 μf, 5 V Electrolytic Capacitors C9, C, pf, mil Chip Capacitors C, C7. μf, mil Chip Capacitors L 55.5 nh, 5 Turn, Coilcraft N, N Type N Flange Mounts R 5 Ω Chip Resistor (5) R 5 Ω, / W Resistor R Ω Chip Resistor (5) R kω, / W Resistor Z.7 x. Microstrip Z.7 x. Microstrip Z. x. Microstrip Z. x. Microstrip Z5.75 x. Microstrip Z, Z7. x. Microstrip Z.9 x. Microstrip Z9. x. Microstrip Z. x. Microstrip Z.55 x. Microstrip Board Glass Teflon, mils, oz. Copper Figure MHz Broadband Test Circuit TYPICAL CHARACTERISTICS, - 7 MHz. MHz MHz 7 MHz P in, INPUT POWER (WATTS) IRL, INPUT RETURN LOSS (db) 5 5 MHz MHz 7 MHz P out Figure. Output Power versus Input Power Figure. Input Return Loss versus Output Power 7

8 TYPICAL CHARACTERISTICS, - 7 MHz GAIN (db) MHz MHz 7 MHz P out Figure. Gain versus Output Power MHz MHz MHz P out Figure. Drain Efficiency versus Output Power MHz MHz 7 MHz P in =. dbm I DQ, BIASING CURRENT (ma) MHz MHz MHz P in =. dbm I DQ, BIASING CURRENT (ma) Figure. Output Power versus Biasing Current Figure 5. Drain Efficiency versus Biasing Current MHz 75 7 MHz 5 7 MHz 55 MHz 7 MHz 5 5 MHz I DQ = 5 ma I DQ = 5 ma P in =. dbm 5 P in =. dbm V DD, SUPPLY VOLTAGE (VOLTS) V DD, SUPPLY VOLTAGE (VOLTS) Figure. Output Power versus Supply Voltage Figure 7. Drain Efficiency versus Supply Voltage

9 V GG C9 C + C7 R B R C7 B C C5 + C V DD RF INPUT N C Z C L C Z Z C R C5 Z R Z5 DUT C Z Z7 L Z L L Z9 Z C C C C RF OUTPUT N B, B Short Ferrite Beads, Fair Rite Products (7) C, C pf, mil Chip Capacitors C, C, C to pf Trimmer Capacitors C pf, mil Chip Capacitor C5 pf, mil Chip Capacitor C, C7 75 pf, mil Chip Capacitors C7, C μf, 5 V Electrolytic Capacitors C, C5, pf, mil Chip Capacitors C9, C. μf, mil Chip Capacitors C 75 pf, mil Chip Capacitor C pf, mil Chip Capacitor L nh, Turn, Coilcraft L 5 nh, Turn, Coilcraft L nh, 5 Turn, Coilcraft Figure MHz Broadband Test Circuit L 55.5 nh, 5 Turn, Coilcraft N, N Type N Flange Mounts R 5 Chip Resistor (5) R 5, / W Carbon Resistor R Chip Resistor (5) R k, / W Carbon Resistor Z.5 x. Microstrip Z.55 x. Microstrip Z.7 x. Microstrip Z.9 x. Microstrip Z5, Z. x. Microstrip Z7.5 x. Microstrip Z.9 x. Microstrip Z9.5 x. Microstrip Z.55 x. Microstrip Board Glass Teflon, mils, oz. Copper TYPICAL CHARACTERISTICS, 5-75 MHz 55 MHz 75 MHz 5 MHz... P in, INPUT POWER (WATTS). IRL, INPUT RETURN LOSS (db) MHz 5 MHz 75 MHz P out Figure 9. Output Power versus Input Power Figure. Input Return Loss versus Output Power 9

10 TYPICAL CHARACTERISTICS, 5-75 MHz 9 GAIN (db) MHz 75 MHz 55 MHz P out 7 55 MHz 5 MHz 5 75 MHz P out Figure. Gain versus Output Power Figure. Drain Efficiency versus Output Power 55 MHz 5 MHz 75 MHz P in =.5 dbm MHz 5 MHz 75 MHz P in =.5 dbm I DQ, BIASING CURRENT (ma) I DQ, BIASING CURRENT (ma) Figure. Output Power versus Biasing Current Figure. Drain Efficiency versus Biasing Current MHz MHz 7 55 MHz 75 MHz 5 5 MHz 75 MHz I DQ = 5 ma I P in =.5 dbm DQ = 5 ma P 5 in =.5 dbm V DD, SUPPLY VOLTAGE (VOLTS) V DD, SUPPLY VOLTAGE (VOLTS) Figure 5. Output Power versus Supply Voltage Figure. Drain Efficiency versus Supply Voltage

11 TYPICAL CHARACTERISTICS 9 MTTF FACTOR (HOURS X AMPS ) T J, JUNCTION TEMPERATURE ( C) This above graph displays calculated MTTF in hours x ampere drain current. Life tests at elevated temperatures have correlated to better than ±% of the theoretical prediction for metal failure. Divide MTTF factor by I D for MTTF in a particular application. Figure 7. MTTF Factor versus Junction Temperature

12 Z o = Ω Z o = Ω 5 Z in 5 f = 5 MHz f = 5 MHz Z OL * f = 5 MHz f = 5 MHz Z OL * f = MHz Z in f = MHz V DD =.5 V, I DQ = 5 ma, P out = W V DD =.5 V, I DQ = 5 ma, P out = W f MHz Z in Ω Z OL * Ω f MHz Z in Ω Z OL * Ω 5.9 +j.5. +j. Z in = Complex conjugate of source impedance with parallel 5 Ω resistor and pf capacitor in series with gate. (See Figure ). Z OL * = 7.5 +j j. 5. +j..7 +j j.9. +j.7 Complex conjugate of the load impedance at given output power, voltage, frequency, and η D > 5 %.. -j.. +j. Z in = Complex conjugate of source impedance. Z OL * =.9 -j.. +j.7. -j.. +j j..7 +j.79 Complex conjugate of the load impedance at given output power, voltage, frequency, and η D > 5 %. Note: Z OL * was chosen based on tradeoffs between gain, drain efficiency, and device stability. Input Matching Network Device Under Test Output Matching Network Z in Z OL * Figure. Series Equivalent Input and Output Impedance

13 f = 7 MHz Z in Z OL * f = 7 MHz 5 ZOL * f = 75 MHz Z in 75 f = 5 MHz Z o = Ω V DD =.5 V, I DQ = 5 ma, P out = W V DD =.5 V, I DQ = 5 ma, P out = W f MHz Z in Ω Z OL * Ω f MHz Z in Ω Z OL * Ω. +j.. +j.7.5 +j5.. +j j..9 +j. 5. -j j j j j j. Z in = Complex conjugate of source impedance with parallel 5 Ω resistor and 7 pf capacitor in series with gate. (See Figure 9). Z in = Complex conjugate of source impedance with parallel 5 Ω resistor and pf capacitor in series with gate. (See Figure ). Z OL * = Complex conjugate of the load impedance at given output power, voltage, frequency, and η D > 5 %. Z OL * = Complex conjugate of the load impedance at given output power, voltage, frequency, and η D > 5 %. Note: Z OL * was chosen based on tradeoffs between gain, drain efficiency, and device stability. Input Matching Network Device Under Test Output Matching Network Z in Z OL * Figure. Series Equivalent Input and Output Impedance (continued)

14 Table 5. Common Source Scattering Parameters () I DQ = 5 ma f S S S S MHz S φ S φ S φ S φ I DQ = ma f S S S S MHz S φ S φ S φ S φ I DQ =.5 A f S S S S MHz S φ S φ S φ S φ

15 APPLICATIONS INFORMATION DESIGN CONSIDERATIONS This device is a common-source, RF power, N-Channel enhancement mode, Lateral Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET). Freescale Application Note ANA, FETs in Theory and Practice, is suggested reading for those not familiar with the construction and characteristics of FETs. This surface mount packaged device was designed primarily for VHF and UHF portable power amplifier applications. Manufacturability is improved by utilizing the tape and reel capability for fully automated pick and placement of parts. However, care should be taken in the design process to insure proper heat sinking of the device. The major advantages of Lateral RF power MOSFETs include high gain, simple bias systems, relative immunity from thermal runaway, and the ability to withstand severely mismatched loads without suffering damage. MOSFET CAPACITANCES The physical structure of a MOSFET results in capacitors between all three terminals. The metal oxide gate structure determines the capacitors from gate-to-drain (C gd ), and gate-to-source (C gs ). The PN junction formed during fabrication of the RF MOSFET results in a junction capacitance from drain-to-source (C ds ). These capacitances are characterized as input (C iss ), output (C oss ) and reverse transfer (C rss ) capacitances on data sheets. The relationships between the inter- terminal capacitances and those given on data sheets are shown below. The C iss can be specified in two ways:. Drain shorted to source and positive voltage at the gate.. Positive voltage of the drain in respect to source and zero volts at the gate. In the latter case, the numbers are lower. However, neither method represents the actual operating conditions in RF applications. Gate C gd C gs Drain C ds Source C iss = C gd + C gs C oss = C gd + C ds C rss = C gd DRAIN CHARACTERISTICS One critical figure of merit for a FET is its static resistance in the full-on condition. This on-resistance, R DS(on), occurs in the linear region of the output characteristic and is specified at a specific gate- source voltage and drain current. The drain-source voltage under these conditions is termed V DS(on). For MOSFETs, V DS(on) has a positive temperature coefficient at high temperatures because it contributes to the power dissipation within the device. BV DSS values for this device are higher than normally required for typical applications. Measurement of BV DSS is not recommended and may result in possible damage to the device. GATE CHARACTERISTICS The gate of the RF MOSFET is a polysilicon material, and is electrically isolated from the source by a layer of oxide. The DC input resistance is very high - on the order of 9 Ω resulting in a leakage current of a few nanoamperes. Gate control is achieved by applying a positive voltage to the gate greater than the gate- to- source threshold voltage, V GS(th). Gate Voltage Rating Never exceed the gate voltage rating. Exceeding the rated V GS can result in permanent damage to the oxide layer in the gate region. Gate Termination The gates of these devices are essentially capacitors. Circuits that leave the gate open- circuited or floating should be avoided. These conditions can result in turn-on of the devices due to voltage build-up on the input capacitor due to leakage currents or pickup. Gate Protection These devices do not have an internal monolithic zener diode from gate- to- source. If gate protection is required, an external zener diode is recommended. Using a resistor to keep the gate-to-source impedance low also helps dampen transients and serves another important function. Voltage transients on the drain can be coupled to the gate through the parasitic gate- drain capacitance. If the gate-to-source impedance and the rate of voltage change on the drain are both high, then the signal coupled to the gate may be large enough to exceed the gate-threshold voltage and turn the device on. DC BIAS Since this device is an enhancement mode FET, drain current flows only when the gate is at a higher potential than the source. RF power FETs operate optimally with a quiescent drain current (I DQ ), whose value is application dependent. This device was characterized at I DQ = 5 ma, which is the suggested value of bias current for typical applications. For special applications such as linear amplification, I DQ may have to be selected to optimize the critical parameters. The gate is a dc open circuit and draws no current. Therefore, the gate bias circuit may generally be just a simple resistive divider network. Some special applications may require a more elaborate bias system. GAIN CONTROL Power output of this device may be controlled to some degree with a low power dc control signal applied to the gate, thus facilitating applications such as manual gain control, ALC/AGC and modulation systems. This characteristic is very dependent on frequency and load line. 5

16 MOUNTING The specified maximum thermal resistance of C/W assumes a majority of the.5 x. source contact on the back side of the package is in good contact with an appropriate heat sink. As with all RF power devices, the goal of the thermal design should be to minimize the temperature at the back side of the package. Refer to Freescale Application Note AN5/D, Thermal Management and Mounting Method for the PLD-.5 RF Power Surface Mount Package, and Engineering Bulletin EB9/D, Mounting Method for RF Power Leadless Surface Mount Transistor for additional information. AMPLIFIER DESIGN Impedance matching networks similar to those used with bipolar transistors are suitable for this device. For examples see Freescale Application Note AN7, Impedance Matching Networks Applied to RF Power Transistors. Large- signal impedances are provided, and will yield a good first pass approximation. Since RF power MOSFETs are triode devices, they are not unilateral. This coupled with the very high gain of this device yields a device capable of self oscillation. Stability may be achieved by techniques such as drain loading, input shunt resistive loading, or output to input feedback. The RF test fixture implements a parallel resistor and capacitor in series with the gate, and has a load line selected for a higher efficiency, lower gain, and more stable operating region. Two-port stability analysis with this device s S- parameters provides a useful tool for selection of loading or feedback circuitry to assure stable operation. See Freescale Application Note AN5A, RF Small- Signal Design Using Two- Port Parameters for a discussion of two port network theory and stability.

17 PACKAGE DIMENSIONS A..7 F B D R L.5.9 ZONE V ZONE W G Q N K H ÉÉ ÉÉÉ ÉÉ ÉÉÉ ÉÉ ÉÉÉ ÉÉ ÉÉÉ ZONE X VIEW Y-Y S.5 (.9) X 5 5 U C P Y NOTES:. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y.5M, 9.. CONTROLLING DIMENSION: INCH. RESIN BLEED/FLASH ALLOWABLE IN ZONE V, W, AND X. STYLE : PIN. DRAIN. GATE. SOURCE. SOURCE CASE - ISSUE D PLD-.5 PLASTIC Y DRAFT E..5 inches mm SOLDER FOOTPRINT INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D..5.. E...5. F.... G H.5... J K L N P.... Q R S...5. U...5. ZONE V....5 ZONE W....5 ZONE X

18 PRODUCT DOCUMENTATION, TOOLS AND SOFTWARE Refer to the following documents to aid your design process. Application Notes ANA: Field Effect Transistors in Theory and Practice AN5A: RF Small- Signal Design Using Two- Port Parameters AN7: Impedance Matching Networks Applied to RF Power Transistors AN5: Thermal Management and Mounting Method for the PLD.5 RF Power Surface Mount Package Engineering Bulletins EB: Using Data Sheet Impedances for RF LDMOS Devices Software Electromigration MTTF Calculator For Software and Tools, do a Part Number search at and select the Part Number link. Go to the Software & Tools tab on the part s Product Summary page to download the respective tool. The following table summarizes revisions to this document. REVISION HISTORY Revision Date Description June Changed Power Gain from.5 db to db in Functional Tests table on p. and corrected specified performance values for power gain and efficiency on p. to match typical performance values in the functional test. Past two years of production data shows Power Gain typical value at db. Added Product Documentation and Revision History, p. June 9 Modified data sheet to reflect MSL rating change from to as a result of the standardization of packing process as described in Product and Process Change Notification number, PCN5, p. Added Electromigration MTTF Calculator availability to Product Documentation, Tools and Software, p.

19 How to Reach Us: Home Page: Web Support: USA/Europe or Locations Not Listed:, Inc. Technical Information Center, EL5 East Elliot Road Tempe, Arizona or Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 9 Muenchen, Germany (English) + 5 (English) (German) (French) Japan: Japan Ltd. Headquarters ARCO Tower 5F --, Shimo-Meguro, Meguro-ku, Tokyo 5- Japan 9 or support.japan@freescale.com Asia/Pacific: China Ltd. Exchange Building F No. Jianguo Road Chaoyang District Beijing China support.asia@freescale.com For Literature Requests Only: Literature Distribution Center ---7 or Fax: LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. reserves the right to make changes without further notice to any products herein. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals, must be validated for each customer application by customer s technical experts. does not convey any license under its patent rights nor the rights of others. products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should Buyer purchase or use products for any such unintended or unauthorized application, Buyer shall indemnify and hold and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale and the Freescale logo are trademarks of, Inc. All other product or service names are the property of their respective owners., Inc. -9. All rights reserved. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. For further information, see or contact your Freescale sales representative. For information on Freescale s Environmental Products program, go to RF Document Device Number: Data MRF5N Freescale Rev., /9 Semiconductor 9