P D Storage Temperature Range T stg - 65 to +150 C Operating Junction Temperature T J 200 C

Transcription

1 Technical Data Document Number: MRF1535T1 Rev. 8, 5/06 Replaced by MRF1535NT1/FNT1. There are no form, fit or function changes with this part replacement. N suffix added to part number to indicate transition to lead-free terminations. RF Power Field Effect Transistors N-Channel Enhancement-Mode Lateral MOSFETs Designed for broadband commercial and industrial applications with frequencies to 5 MHz. The high gain and broadband performance of these devices make them ideal for large-signal, common source amplifier applications in 12.5 volt mobile FM equipment. Specified 5 MHz, 12.5 Volts Output Power 35 Watts Power Gain.0 db Efficiency % Capable of Handling : Vdc, 5 MHz, 2 db Overdrive Excellent Thermal Stability Characterized with Series Equivalent Large- Signal Impedance Parameters Broadband -Full Power Across the Band: MHz 0-4 MHz 4-5 MHz Broadband UHF/VHF Demonstration Amplifier Information Available Upon Request 0 C Capable Plastic Package In Tape and Reel. T1 Suffix = 0 Units per 44 mm, 13 inch Reel. Table 1. Maximum Ratings Rating Symbol Value Unit Drain-Source Voltage V DSS -0.5, + Vdc Gate-Source Voltage V GS ± Vdc Drain Current Continuous I D 6 Adc Total Device T C = 25 C (1) Derate above 25 C P D Storage Temperature Range T stg - 65 to +1 C Operating Junction Temperature T J 0 C Table 2. Thermal Characteristics MRF1535T1 MRF1535FT1 5 MHz, 35 W, 12.5 V LATERAL N- CHANNEL BROADBAND RF POWER MOSFETs CASE , STYLE 1 TO WRAP PLASTIC MRF1535T1 CASE 1264A-02, STYLE 1 TO PLASTIC MRF1535FT1 W W/ C Characteristic Symbol Value Unit Thermal Resistance, Junction to Case R θjc 0.90 C/W Table 3. Moisture Sensitivity Level Test Methodology Rating Package Peak Temperature Unit Per JESD 22-A113, IPC/JEDEC J-STD C TJ TC 1. Calculated based on the formula P D = RθJC NOTE - CAUTION - MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and packaging MOS devices should be observed., Inc., 06. All rights reserved. 1

2 Table 4. Electrical Characteristics (T C = 25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Off Characteristics Drain-Source Breakdown Voltage (V GS = 0 Vdc, I D = 0 μadc) Zero Gate Voltage Drain Current (V DS = Vdc, V GS = 0 Vdc) Gate-Source Leakage Current (V GS = Vdc, V DS = 0 Vdc) On Characteristics Gate Threshold Voltage (V DS = 12.5 Vdc, I D = 0 μa) Drain-Source On-Voltage (V GS = 5 Vdc, I D = 0.6 A) Drain-Source On-Voltage (V GS = Vdc, I D = 2.0 Adc) Dynamic Characteristics Input Capacitance (Includes Input Matching Capacitance) (V DS = 12.5 Vdc, V GS = 0 V, f = 1 MHz) Output Capacitance (V DS = 12.5 Vdc, V GS = 0 V, f = 1 MHz) Reverse Transfer Capacitance (V DS = 12.5 Vdc, V GS = 0 V, f = 1 MHz) RF Characteristics (In Freescale Test Fixture) Common-Source Amplifier Power Gain (, P out = 35 Watts, I DQ = 0 ma) f = 5 MHz Drain Efficiency (, P out = 35 Watts, I DQ = 0 ma) f = 5 MHz V (BR)DSS Vdc I DSS 1 μadc I GSS 0.3 μadc V GS(th) Vdc R DS(on) 0.7 Ω V DS(on) 1 Vdc C iss 2 pf C oss 1 pf C rss pf G ps db η % 2

3 V GG C11 + C R4 R3 C23 B1 C22 + C21 V DD L5 RF INPUT N1 C1 Z1 L1 C9 R2 R1 DUT Z2 Z3 L2 Z4 Z5 Z6 Z7 Z8 Z9 L3 L4 Z RF OUTPUT N2 C C2 C3 C4 C5 C6 C7 C8 C12 C13 C14 C15 C16 C17 C18 C19, OUTPUT POWER (WATTS) Pout 0 0 B1 Ferroxcube #VK0 C1, C9, C, C23 3 pf, 0 mil Chip Capacitors C2, C5 0 to pf Trimmer Capacitors C3, C15 33 pf, 0 mil Chip Capacitors C4, C6, C19 18 pf, 0 mil Chip Capacitors C7 1 pf, 0 mil Chip Capacitor C8 2 pf, 0 mil Chip Capacitor C, C21 μf, V Electrolytic Capacitors C11, C22 4 pf, 0 mil Chip Capacitors C12, C13 1 pf, 0 mil Chip Capacitors C14 1 pf, 0 mil Chip Capacitor C16 68 pf, 0 mil Chip Capacitor C17 1 pf, 0 mil Chip Capacitor C18 51 pf, 0 mil Chip Capacitor L nh, Coilcraft #A05T L2 5 nh, Coilcraft #A02T L3 1 Turn, #26 AWG, 0.2 ID 1 2 Figure MHz Broadband Test Circuit TYPICAL CHARACTERISTICS, MHz MHz 135 MHz 175 MHz 4 IRL, INPUT RETURN LOSS (db) L4 1 Turn, #26 AWG, 0.2 ID L5 4 Turn, #24 AWG, ID N1, N2 Type N Flange Mounts R1 6.5 Ω, 1/4 W Chip Resistor R2 39 Ω Chip Resistor (0805) R3 1.2 kω, 1/8 W Chip Resistor R4 33 kω, 1/4 W Chip Resistor Z1 0.9 x Microstrip Z x Microstrip Z x Microstrip Z4 0.1 x Microstrip Z5, Z6 0.1 x 0.0 Microstrip Z x Microstrip Z8 0.2 x Microstrip Z9 0.3 x Microstrip Z 0.2 x Microstrip Board Glass Teflon, 31 mils 155 MHz 135 MHz 175 MHz P in, INPUT POWER (WATTS) Figure 2. Output Power versus Input Power P out, OUTPUT POWER (WATTS) Figure 3. Input Return Loss versus Output Power 3

4 TYPICAL CHARACTERISTICS, MHz GAIN (db), OUTPUT POWER (WATTS) Pout, OUTPUT POWER (WATTS) P out P out, OUTPUT POWER (WATTS) Figure 4. Gain versus Output Power 0 I DQ, BIASING CURRENT (ma) Figure 6. Output Power versus Biasing Current MHz 175 MHz 135 MHz MHz 175 MHz MHz 135 MHz P in = dbm 155 MHz 135 MHz I DQ = 2 ma P in = dbm , DRAIN EFFICIENCY (%), DRAIN EFFICIENCY (%), DRAIN EFFICIENCY (%) P out, OUTPUT POWER (WATTS) Figure 5. Drain Efficiency versus Output Power I DQ, BIASING CURRENT (ma) Figure 7. Drain Efficiency versus Biasing Current MHz 175 MHz MHz 175 MHz 135 MHz 135 MHz 175 MHz 155 MHz MHz P in = dbm I DQ = 2 ma P in = dbm V DD, SUPPLY VOLTAGE (VOLTS) Figure 8. Output Power versus Supply Voltage V DD, SUPPLY VOLTAGE (VOLTS) Figure 9. Drain Efficiency versus Supply Voltage 4

5 V GG B1 V DD C14 C13 C12 + C11 R3 R2 C25 L1 C24 C23 + C22 RF INPUT N1 C1 R1 C Z1 Z2 Z3 Z4 Z5 Z6 C2 C3 C4 C5 C6 C7 C8 C9 DUT Z7 C15 C16 Z8 C17 Z9 C18 C19 C Z C21 N2 RF OUTPUT, OUTPUT POWER (WATTS) Pout B1 Ferroxcube VK0 C1 1 pf, 0 mil Chip Capacitor C2 3 pf, 0 mil Chip Capacitor C3 3.6 pf, 0 mil Chip Capacitor C4 2.2 pf, 0 mil Chip Capacitor C5 pf, 0 mil Chip Capacitor C6, C7 16 pf, 0 mil Chip Capacitors C8, C15, C16 27 pf, 0 mil Chip Capacitors C9 43 pf, 0 mil Chip Capacitor C, C14, C25 1 pf, 0 mil Chip Capacitors C11, C22 μf, V Electrolytic Capacitors C12, C24 1,0 pf, 0 mil Chip Capacitors C13, C μf, 0 mil Chip Capacitors C17, C18 24 pf, 0 mil Chip Capacitors C19 1 pf, 0 mil Chip Capacitor C 8.2 pf, 0 mil Chip Capacitor P in, INPUT POWER (WATTS) Figure 11. Output Power versus Input Power Figure. 4-5 MHz Broadband Test Circuit TYPICAL CHARACTERISTICS, 4-5 MHz 4 MHz 4 MHz 0 MHz 5 MHz IRL, INPUT RETURN LOSS (db) C pf, 0 mil Chip Capacitor L nh, 5 Turn, Coilcraft N1, N2 Type N Flange Mounts R1 0 Ω Chip Resistor (0805) R2 1 kω Chip Resistor (0805) R3 33 kω, 1/8 W Chip Resistor Z x Microstrip Z2 1.0 x Microstrip Z x Microstrip Z4 0.1 x Microstrip Z5, Z8 0.1 x Microstrip Z6, Z7 0.1 x Microstrip Z x Microstrip Z x Microstrip Board Glass Teflon, 31 mils MHz 4 MHz 5 MHz 0 MHz 15 0 P out, OUTPUT POWER (WATTS) Figure 12. Input Return Loss versus Output Power 5

6 TYPICAL CHARACTERISTICS, 4-5 MHz GAIN (db), OUTPUT POWER (WATTS) Pout, OUTPUT POWER (WATTS) P out MHz 4 MHz P out, OUTPUT POWER (WATTS) Figure 13. Gain versus Output Power I DQ, BIASING CURRENT (ma) Figure 15. Output Power versus Biasing Current 0 4 MHz 5 MHz MHz 4 MHz 0 MHz 5 MHz 5 MHz MHz 0 MHz 12 V DD, SUPPLY VOLTAGE (VOLTS) Figure 17. Output Power versus Supply Voltage 13 0 MHz P in = 34 dbm 00 I DQ = 2 ma P in = 34 dbm , DRAIN EFFICIENCY (%), DRAIN EFFICIENCY (%), DRAIN EFFICIENCY (%) MHz 5 MHz P out, OUTPUT POWER (WATTS) Figure 14. Drain Efficiency versus Output Power 5 MHz 4 MHz 0 0 MHz I DQ, BIASING CURRENT (ma) Figure 16. Drain Efficiency versus Biasing Current MHz 4 MHz V DD, SUPPLY VOLTAGE (VOLTS) Figure 18. Drain Efficiency versus Supply Voltage 4 MHz 4 MHz 13 0 MHz 4 MHz P in = 34 dbm 00 0 MHz I DQ = 2 ma P in = 34 dbm

7 Z o = Ω f = 175 MHz Z OL * f = 4 MHz f MHz Z in Ω Z OL * Ω j j0.2 Z in = Complex conjugate of source impedance. Z OL * = Z OL * Z in f = 135 MHz f = 5 MHz f = 4 MHz f = 5 MHz f = 175 MHz Z in f = 135 MHz V DD = 12.5 V, I DQ = 2 ma, P out = 35 W j j j j0.1 Complex conjugate of the load impedance at given output power, voltage, frequency, and η D > %. Z in = Complex conjugate of source impedance. Z OL * = V DD = 12.5 V, I DQ = 0 ma, P out = 35 W f MHz Complex conjugate of the load impedance at given output power, voltage, frequency, and η D > %. Note: Z OL * was chosen based on tradeoffs between gain, drain efficiency, and device stability. Z in Ω Z OL * Ω j j j j j j j j0.5 Input Matching Network Device Under Test Output Matching Network Z in Z OL * Figure 19. Series Equivalent Input and Output Impedance 7

8 Table 5. Common Source Scattering Parameters () I DQ = 2 ma f S 11 S 21 S 12 S 22 MHz S 11 φ S 21 φ S 12 φ S 22 φ I DQ = 1.0 A f S 11 S 21 S 12 S 22 MHz S 11 φ S 21 φ S 12 φ S 22 φ I DQ = 2.0 A f S 11 S 21 S 12 S 22 MHz S 11 φ S 21 φ S 12 φ S 22 φ

9 APPLICATIONS INFORMATION DESIGN CONSIDERATIONS This device is a common-source, RF power, N-Channel enhancement mode, Lateral Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET). Freescale Application Note AN211A, FETs in Theory and Practice, is suggested reading for those not familiar with the construction and characteristics of FETs. This surface mount packaged device was designed primarily for VHF and UHF mobile power amplifier applications. Manufacturability is improved by utilizing the tape and reel capability for fully automated pick and placement of parts. However, care should be taken in the design process to insure proper heat sinking of the device. The major advantages of Lateral RF power MOSFETs include high gain, simple bias systems, relative immunity from thermal runaway, and the ability to withstand severely mismatched loads without suffering damage. MOSFET CAPACITANCES The physical structure of a MOSFET results in capacitors between all three terminals. The metal oxide gate structure determines the capacitors from gate-to-drain (C gd ), and gate-to-source (C gs ). The PN junction formed during fabrication of the RF MOSFET results in a junction capacitance from drain-to-source (C ds ). These capacitances are characterized as input (C iss ), output (C oss ) and reverse transfer (C rss ) capacitances on data sheets. The relationships between the inter- terminal capacitances and those given on data sheets are shown below. The C iss can be specified in two ways: 1. Drain shorted to source and positive voltage at the gate. 2. Positive voltage of the drain in respect to source and zero volts at the gate. In the latter case, the numbers are lower. However, neither method represents the actual operating conditions in RF applications. Gate C gd C gs Drain C ds Source C iss = C gd + C gs C oss = C gd + C ds C rss = C gd DRAIN CHARACTERISTICS One critical figure of merit for a FET is its static resistance in the full-on condition. This on-resistance, R DS(on), occurs in the linear region of the output characteristic and is specified at a specific gate- source voltage and drain current. The drain-source voltage under these conditions is termed V DS(on). For MOSFETs, V DS(on) has a positive temperature coefficient at high temperatures because it contributes to the power dissipation within the device. BV DSS values for this device are higher than normally required for typical applications. Measurement of BV DSS is not recommended and may result in possible damage to the device. GATE CHARACTERISTICS The gate of the RF MOSFET is a polysilicon material, and is electrically isolated from the source by a layer of oxide. The DC input resistance is very high - on the order of 9 Ω resulting in a leakage current of a few nanoamperes. Gate control is achieved by applying a positive voltage to the gate greater than the gate- to- source threshold voltage, V GS(th). Gate Voltage Rating Never exceed the gate voltage rating. Exceeding the rated V GS can result in permanent damage to the oxide layer in the gate region. Gate Termination The gates of these devices are essentially capacitors. Circuits that leave the gate open- circuited or floating should be avoided. These conditions can result in turn-on of the devices due to voltage build-up on the input capacitor due to leakage currents or pickup. Gate Protection These devices do not have an internal monolithic zener diode from gate- to- source. If gate protection is required, an external zener diode is recommended. Using a resistor to keep the gate-to-source impedance low also helps dampen transients and serves another important function. Voltage transients on the drain can be coupled to the gate through the parasitic gate- drain capacitance. If the gate-to-source impedance and the rate of voltage change on the drain are both high, then the signal coupled to the gate may be large enough to exceed the gate-threshold voltage and turn the device on. DC BIAS Since this device is an enhancement mode FET, drain current flows only when the gate is at a higher potential than the source. RF power FETs operate optimally with a quiescent drain current (I DQ ), whose value is application dependent. This device was characterized at I DQ = 1 ma, which is the suggested value of bias current for typical applications. For special applications such as linear amplification, I DQ may have to be selected to optimize the critical parameters. The gate is a dc open circuit and draws no current. Therefore, the gate bias circuit may generally be just a simple resistive divider network. Some special applications may require a more elaborate bias system. GAIN CONTROL Power output of this device may be controlled to some degree with a low power dc control signal applied to the gate, thus facilitating applications such as manual gain control, ALC/AGC and modulation systems. This characteristic is very dependent on frequency and load line. 9

10 MOUNTING The specified maximum thermal resistance of 0.9 C/W assumes a majority of the 0.1 x 0.8 source contact on the back side of the package is in good contact with an appropriate heat sink. As with all RF power devices, the goal of the thermal design should be to minimize the temperature at the back side of the package. AMPLIFIER DESIGN Impedance matching networks similar to those used with bipolar transistors are suitable for this device. For examples see Freescale Application Note AN721, Impedance Matching Networks Applied to RF Power Transistors. Large- signal impedances are provided, and will yield a good first pass approximation. Since RF power MOSFETs are triode devices, they are not unilateral. This coupled with the very high gain of this device yields a device capable of self oscillation. Stability may be achieved by techniques such as drain loading, input shunt resistive loading, or output to input feedback. The RF test fixture implements a parallel resistor and capacitor in series with the gate, and has a load line selected for a higher efficiency, lower gain, and more stable operating region. Two-port stability analysis with this device s S- parameters provides a useful tool for selection of loading or feedback circuitry to assure stable operation. See Freescale Application Note AN215A, RF Small- Signal Design Using Two- Port Parameters for a discussion of two port network theory and stability.

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14 PACKAGE DIMENSIONS B E1 A aaa D1 M 4X b2 D A aaa M 2X b1 aaa M r1 4 D A 5 D A DRAIN ID 4X e D DRAIN ID NOTE X b3 DATUM PLANE H Y E E2 Y A C D SEATING PLANE SEATING PLANE E2 VIEW Y-Y NOTES: 1. CONTROLLING DIMENSION: INCH. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, DATUM PLANE H IS LOCATED AT TOP OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE TOP OF THE PARTING LINE. 4. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS PER SIDE. DIMENSION D AND E1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 5. DIMENSIONS b1 AND b3 DO NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE TOTAL IN EXCESS OF THE b1 AND b2 DIMENSIONS AT MAXIMUM MATERIAL CONDITION. 6. CROSSHATCHING REPRESENTS THE EXPOSED AREA OF THE HEAT SLUG. L c1 A1 A2 STYLE 1: PIN 1. SOURCE (COMMON) 2. DRAIN 3. SOURCE (COMMON) 4. SOURCE (COMMON) 5. GATE 6. SOURCE (COMMON) CASE ISSUE K TO WRAP PLASTIC MRF1535T1 INCHES MILLIMETERS DIM MIN MAX MIN MAX A A A D D E E E L b b b c e BSC 4.90 BSC r aaa

15 B 2X P aaa M D A B E1 A E2 D1 aaa 4X b2 M aaa M D A 2X b1 aaa M D A D A 4X b DRAIN ID 4X e D D DRAIN ID NOTE bbb C A B E VIEW Y-Y c1 D SEATING PLANE Y F ZONE "J" Y A1 6 A2 A NOTES: 1. CONTROLLING DIMENSION: INCH. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, DIMENSIONS D AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS PER SIDE. DIMENSIONS D AND E1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS b1 AND b3 DO NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE TOTAL IN EXCESS OF THE b1 AND b2 DIMENSIONS AT MAXIMUM MATERIAL CONDITION. 5. CROSSHATCHING REPRESENTS THE EXPOSED AREA OF THE HEAT SLUG. 6. DIMENSION A2 APPLIES WITHIN ZONE J ONLY. STYLE 1: PIN 1. SOURCE (COMMON) 2. DRAIN 3. SOURCE (COMMON) 4. SOURCE (COMMON) 5. GATE 6. SOURCE (COMMON) CASE 1264A-02 ISSUE C TO PLASTIC MRF1535FT1 INCHES MILLIMETERS DIM MIN MAX MIN MAX A A A D D1 D2 0.8 BSC 0.8 BSC.57 BSC BSC E E E2 0.1 BSC 4.32 BSC F BSC 0.64 BSC P b b b c e BSC 4.90 BSC aaa bbb

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