RF Power Field Effect Transistor N--Channel Enhancement--Mode Lateral MOSFET

Transcription

1 Technical Data RF Power Field Effect Transistor N--Channel Enhancement--Mode Lateral MOSFET RF Power transistor designed for applications operating at frequencies between 960 and 400 MHz, % to 20% duty cycle. This device is suitable for use in pulsed applications. Typical Pulsed Performance: V DD =50Volts,I DQ =0mA,P out = 0 Watts Peak (2 W Avg.), f = 090 MHz, Pulse Width = 00 μsec, Duty Cycle = 20% Power Gain 25 db Drain Efficiency 69% Features Characterized with Series Equivalent Large--Signal Impedance Parameters Qualified Up to a Maximum of 50 V DD Operation Integrated ESD Protection Greater Negative Gate--Source Voltage Range for Improved Class C Operation RoHS Compliant In Tape and Reel. R4 Suffix = 00 Units per 2 mm, 7 inch Reel. Document Number: MRF6V000N Rev. 3, 7/ MHz, 0 W, 50 V PULSED LATERAL N -CHANNEL RF POWER MOSFET CASE , STYLE PLD -.5 PLASTIC Table. Maximum Ratings Rating Symbol Value Unit Drain--Source Voltage V DSS --0.5, +00 Vdc Gate--Source Voltage V GS --6.0, +0 Vdc Storage Temperature Range T stg to +50 C Case Operating Temperature T C 50 C Operating Junction Temperature T J 200 C Table 2. Thermal Characteristics Characteristic Symbol Value (,2) Unit Thermal Resistance, Junction to Case Case Temperature 79 C, 0 W Pulsed, 00 μsec Pulse Width, 20% Duty Cycle Z θjc.6 C/W. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. 2. Refer to AN955, Thermal Measurement Methodology of RF Power Amplifiers. Go to Select Documentation/Application Notes -- AN955., Inc., All rights reserved.

2 Table 3. ESD Protection Characteristics Test Methodology Class Human Body Model (per JESD22--A4) C (Minimum) Machine Model (per EIA/JESD22--A5) A (Minimum) Charge Device Model (per JESD22--C0) IV (Minimum) Table 4. Moisture Sensitivity Level Test Methodology Rating Package Peak Temperature Unit Per JESD22--A3, IPC/JEDEC J--STD C Table 5. Electrical Characteristics (T A =25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Off Characteristics Gate--Source Leakage Current (V GS =5Vdc,V DS =0Vdc) Drain--Source Breakdown Voltage (V GS =0Vdc,I D =7mA) Zero Gate Voltage Drain Leakage Current (V DS =50Vdc,V GS =0Vdc) Zero Gate Voltage Drain Leakage Current (V DS = 00 Vdc, V GS =0Vdc) On Characteristics Gate Threshold Voltage (V DS =0Vdc,I D =36μAdc) Gate Quiescent Voltage (V DD =50Vdc,I D = 0 madc, Measured in Functional Test) Drain--Source On--Voltage (V GS =0Vdc,I D =70mAdc) Dynamic Characteristics Reverse Transfer Capacitance (V DS =50Vdc± 30 MHz, V GS =0Vdc) Output Capacitance (V DS =50Vdc± 30 MHz, V GS =0Vdc) Input Capacitance (V DS =50Vdc,V GS =0Vdc± 30 MHz) I GSS 0 μadc V (BR)DSS 00 Vdc I DSS 50 μadc I DSS 2.5 ma V GS(th) Vdc V GS(Q) Vdc V DS(on) 0.2 Vdc C rss 0. pf C oss 3.38 pf C iss 9.55 pf Functional Tests (In Freescale Test Fixture, 50 ohm system) V DD =50Vdc,I DQ =0mA,P out = 0 W Peak (2 W Avg.), f = 090 MHz, Pulsed, 00 μsec Pulse Width, 20% Duty Cycle Power Gain G ps db Drain Efficiency η D % Input Return Loss IRL db 2

3 V BIAS + C2 L C3 C2 C9 C8 C7 C3 V SUPPLY RF INPUT Z C Z2 Z3 C5 C6 Z4 C6 C4 Z5 R Z6 R2 Z7 DUT Z8 C0 Z9 C5 L2 Z0 C Z C4 Z2 RF OUTPUT Z Z2 Z3 Z4 Z5 Z6 Z x Microstrip x 0.20 Microstrip x Microstrip x Microstrip x x 0.85 Taper 0.35 x Microstrip 0.74 x Microstrip Z x Microstrip Z x Microstrip Z x Microstip Z x Microstrip Z x Microstrip PCB Arlon CuClad 250GX , 0.030, ε r =2.55 Figure. MR6V000NR4 Test Circuit Schematic Table 6. MR6V000NR4 Test Circuit Component Designations and Values Part Description Part Number Manufacturer C, C9, C2 43 pf Chip Capacitors ATC00B430JT500XT ATC C2 0 μf, 35 V Tantalum Capacitor T49D06K035AT Kemet C3, C8 2.2 μf, 00 V Chip Capacitors GQM885C2A2R2CB0B Murata C4, C6 7.5 pf Chip Capacitors ATC00B7R5CT500XT ATC C5, C6 3.0 pf Chip Capacitors ATC00B3R0CT500XT ATC C7 0. μf Chip Capacitor C206C04K5RACTR Kemet C0, C5 0.3 pf Chip Capacitors ATC00B0R3BT500XT ATC C 5.6 pf Chip Capacitor ATC00B5R6CT500XT ATC C3 470 μf, 63 V Chip Capacitor 477KXM063M Illlinois Capacitor C4 47 pf Chip Capacitor ATC00B470JT500XT ATC L 8 nh Inductor A03TKLC Coilcraft L2 5 nh Inductor A02TKLC Coilcraft R 3300 Ω, /4 W Chip Resistor CRCW206330FKEA Vishay R2 0 Ω, /4 W Chip Resistor CRCW2060R0FKEA Vishay 3

4 C2 L C3 R C2 C8 C7 C9 C3 C C6 C5 C4 C6 R2 C5 C0 L2 C C4 MRF6V000N Rev. 3 Figure 2. Test Circuit Component Layout 4

5 TYPICAL CHARACTERISTICS 00 Measured with ±30 MHz V GS =0Vdc 0 C, CAPACITANCE (pf) 0 C iss C oss I D, DRAIN CURRENT (AMPS) T J = 200 C T J = 50 C T J = 75 C 0. C rss T C =25 C 0 00 V DS, DRAIN--SOURCE VOLTAGE (VOLTS) V DS, DRAIN--SOURCE VOLTAGE (VOLTS) Figure 3. Capacitance versus Drain -Source Voltage Figure 4. DC Safe Operating Area G ps, POWER GAIN (db) G ps η D V DD =50Vdc,I DQ = 0 ma, f = 090 MHz Pulse Width = 00 μsec, Duty Cycle = 20% P out, OUTPUT POWER (WATTS) PULSED Figure 5. Pulsed Power Gain and Drain Efficiency versus Output Power 70 η D, DRAIN EFFICIENCY (%) P out, OUTPUT POWER (dbm) PULSED P3dB = dbm (.65 W) PdB = 40.8 dbm (0.42 W) Ideal Actual V DD =50Vdc,I DQ = 0 ma, f = 090 MHz Pulse Width = 00 μsec, Duty Cycle = 20% P in, INPUT POWER (dbm) PULSED Figure 6. Pulsed Output Power versus Input Power G ps, POWER GAIN (db) V DD =30V 35 V 40 V 45 V P out, OUTPUT POWER (WATTS) PULSED Figure 7. Pulsed Power Gain versus Output Power 50 V I DQ = 0 ma, f = 090 MHz Pulse Width = 00 μsec Duty Cycle = 20% P out, OUTPUT POWER (WATTS) PULSED T C =--30_C 25_C P in, INPUT POWER (WATTS) PULSED Figure 8. Pulsed Output Power versus Input Power 85_C V DD =50Vdc I DQ =0mA f = 090 MHz Pulse Width = 00 μsec Duty Cycle = 20%

6 TYPICAL CHARACTERISTICS η D G ps, POWER GAIN (db) _C 25_C V DD =50Vdc,I DQ = 0 ma, f = 090 MHz Pulse Width = 00 μsec, Duty Cycle = 20% P out, OUTPUT POWER (WATTS) PULSED T C =--30_C Figure 9. Pulsed Power Gain and Drain Efficiency versus Output Power G ps η D, DRAIN EFFICIENCY (%) MTTF (HOURS) T J, JUNCTION TEMPERATURE ( C) This above graph displays calculated MTTF in hours when the device is operated at V DD =50Vdc,P out = 0 W Peak, Pulse Width = 00 μsec, Duty Cycle = 20%, and η D = 69%. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. Figure 0. MTTF versus Junction Temperature 250 6

7 Z o =50Ω Z load f = 090 MHz Z source f = 090 MHz f MHz V DD =50Vdc,I DQ =0mA,P out = 0 W Peak Z source Ω Z load Ω j j34.32 Z source = Test circuit impedance as measured from gate to ground. Z load = Test circuit impedance as measured from drain to ground. Input Matching Network Device Under Test Output Matching Network Z source Z load Figure. Series Equivalent Source and Load Impedance 7

8 PACKAGE DIMENSIONS A F B D 2 R L ZONE V ZONE W G Q 4 N K H 4 3 ZONE X VIEW Y--Y S (0.89) X 45_ 5_ U C P Y NOTES:. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y4.5M, CONTROLLING DIMENSION: INCH 3. RESIN BLEED/FLASH ALLOWABLE IN ZONE V, W, AND X. STYLE : PIN. DRAIN 2. GATE 3. SOURCE 4. SOURCE CASE ISSUE D PLD -.5 PLASTIC Y 0_ DRAFT E inches mm SOLDER FOOTPRINT INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D E F G H J K L N P Q R S U ZONE V ZONE W ZONE X

9 PRODUCT DOCUMENTATION AND SOFTWARE Refer to the following documents to aid your design process. Application Notes AN955: Thermal Measurement Methodology of RF Power Amplifiers Engineering Bulletins EB22: Using Data Sheet Impedances for RF LDMOS Devices Software Electromigration MTTF Calculator For Software, do a Part Number search at and select the Part Number link. Go to the Software & Tools tab on the part s Product Summary page to download the respective tool. The following table summarizes revisions to this document. REVISION HISTORY Revision Date Description 0 June 2008 Initial Release of Data Sheet Feb Corrected Z source, j7.33 to.5 + j8.96 and Z load, j34.77 to j34.32 in Fig., Series Equivalent Source and Load Impedance data table and replotted data, p. 7 2 June 2009 Modified data sheet to reflect MSL rating change from to 3 as a result of the standardization of packing process as described in Product and Process Change Notification number, PCN356, p. 2 Added Electromigration MTTF Calculator availability to Product Documentation, Tools and Software, p. 9 3 July 200 Reporting of pulsed thermal data now shown using the Z θjc symbol, Table 2, Thermal Characteristics, p. Corrected errors made in the translation of the printed circuit board to the schematic, Fig., Test Circuit Schematic and Z list, p. 3 9

10 How to Reach Us: Home Page: Web Support: USA/Europe or Locations Not Listed:, Inc. Technical Information Center, EL East Elliot Road Tempe, Arizona or Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen Muenchen, Germany (English) (English) (German) (French) Japan: Japan Ltd. Headquarters ARCO Tower 5F --8--, Shimo--Meguro, Meguro--ku, Tokyo Japan or support.japan@freescale.com Asia/Pacific: China Ltd. Exchange Building 23F No. 8 Jianguo Road Chaoyang District Beijing China support.asia@freescale.com For Literature Requests Only: Literature Distribution Center or Fax: LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. reserves the right to make changes without further notice to any products herein. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals, must be validated for each customer application by customer s technical experts. does not convey any license under its patent rights nor the rights of others. products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should Buyer purchase or use products for any such unintended or unauthorized application, Buyer shall indemnify and hold and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescalet and the Freescale logo are trademarks of, Inc. All other product or service names are the property of their respective owners., Inc All rights reserved. Document Number: MRF6V000N 0 Rev. 3, 7/200