RF Power Field Effect Transistors N--Channel Enhancement--Mode Lateral MOSFETs

Transcription

1 Freescale Semiconductor Technical Data RF Power Field Effect Transistors N--Channel Enhancement--Mode Lateral MOSFETs RF power transistors designed for applications operating at frequencies from 900 to 1215 MHz. These devices are suitable for use in defense and commercial pulse applications, such as IFF and DME. Typical Pulse Performance: V DD =50Vdc,I DQ = 150 ma, P out = 00 W Peak (0 W Avg.), f = 30 MHz, Pulse Width = 128 sec, Duty Cycle = % Power Gain db Drain Efficiency 56% Capable of Handling 5:1 50 Vdc, 30 MHz, 00 W Peak Power Features Characterized with Series Equivalent Large--Signal Impedance Parameters Internally Matched for Ease of Use Qualified Up to a Maximum of 50 V DD Operation Integrated ESD Protection Designed for Push--Pull Operation Greater Negative Gate--Source Voltage Range for Improved Class C Operation In Tape and Reel. R5 Suffix = 50 Units, 56 mm Tape Width, 13--inch Reel. Document Number: MMRF07H Rev. 0, 12/13 MMRF07HR5 MMRF07HSR MHz, 00 W, 50 V LATERAL N -CHANNEL BROADBAND RF POWER MOSFETs NI -1230H -4S MMRF07HR5 NI -1230S -4S MMRF07HSR5 PARTS ARE PUSH -PULL RF ina /V GSA 3 1 RF outa /V DSA RF inb /V GSB 4 2 RF outb /V DSB (Top View) Figure 1. Pin Connections Table 1. Maximum Ratings Rating Symbol Value Unit Drain--Source Voltage V DSS --0.5, +1 Vdc Gate--Source Voltage V GS --6.0, + Vdc Storage Temperature Range T stg to +150 C Case Operating Temperature T C 150 C Operating Junction Temperature (1) T J 225 C 1. Continuous use at maximum temperature will affect MTTF., 13. All rights reserved. 1

2 Table 2. Thermal Characteristics Characteristic Symbol Value (1) Unit Thermal Resistance, Junction to Case Z JC C/W Case Temperature 67 C, 00 W Peak, 128 sec Pulse Width, % Duty Cycle, 50 Vdc, I DQ = 150 ma Case Temperature 62 C, Mode--S Pulse Train, 80 Pulses of 32 sec On, 18 sec Off, Repeated Every 40 msec, 6.4% Overall Duty Cycle, 50 Vdc, I DQ = 150 ma Table 3. ESD Protection Characteristics Human Body Model (per JESD22--A114) Machine Model (per EIA/JESD22--A115) Test Methodology Charge Device Model (per JESD22--C1) Table 4. Electrical Characteristics (T A =25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Off Characteristics (2) Gate--Source Leakage Current (V GS =5Vdc,V DS =0Vdc) Class I GSS Adc 1B B IV Drain--Source Breakdown Voltage (V GS =0Vdc,I D = 165 ma) Zero Gate Voltage Drain Leakage Current (V DS =50Vdc,V GS =0Vdc) Zero Gate Voltage Drain Leakage Current (V DS = 0 Vdc, V GS =0Vdc) On Characteristics Gate Threshold Voltage (2) (V DS =Vdc,I D = 00 Adc) Gate Quiescent Voltage (3) (V DD =50Vdc,I D = 150 madc, Measured in Functional Test) Drain--Source On--Voltage (2) (V GS =Vdc,I D =2.7Adc) Dynamic Characteristics (2) Reverse Transfer Capacitance (V DS =50Vdc 30 1 MHz, V GS =0Vdc) Output Capacitance (V DS =50Vdc 30 1 MHz, V GS =0Vdc) Input Capacitance (V DS =50Vdc,V GS =0Vdc 30 1 MHz) V (BR)DSS 1 Vdc I DSS Adc I DSS 0 Adc V GS(th) Vdc V GS(Q) Vdc V DS(on) 0.15 Vdc C rss 1.27 pf C oss 86.7 pf C iss 539 pf Functional Tests (3) (In Freescale Test Fixture, 50 ohm system) V DD =50Vdc,I DQ = 150 ma, P out = 00 W Peak (0 W Avg.), f = 30 MHz, 128 sec Pulse Width, % Duty Cycle Power Gain G ps db Drain Efficiency D % Input Return Loss IRL db 1. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to Select Documentation/Application Notes -- AN Each side of device measured separately. 3. Measurement made with device in push--pull configuration. (continued) 2

3 Table 4. Electrical Characteristics (T A =25 C unless otherwise noted) (continued) Characteristic Symbol Min Typ Max Unit Typical Performance 30 MHz (In Freescale 30 MHz Test Fixture, 50 ohm system) V DD =50Vdc,I DQ = 150 ma, P out = 00 W Peak (0 W Avg.), f = 30 MHz, Mode--S Pulse Train, 80 Pulses of 32 sec On, 18 sec Off, Repeated Every 40 msec, 6.4% Overall Duty Cycle Power Gain G ps 19.8 db Drain Efficiency D 59.0 % Burst Droop BD rp 0.21 db Typical Performance 90 MHz (In Freescale 90 MHz Test Fixture, 50 ohm system) V DD =50Vdc,I DQ = 150 ma, P out = 00 W Peak (0 W Avg.), f = 90 MHz, 128 sec Pulse Width, % Duty Cycle Power Gain G ps 21.4 db Drain Efficiency D 56.3 % Input Return Loss IRL db 3

4 V BIAS + C1 C2 C3 C4 L1 C21 C22 + C23 + C24 V SUPPLY BALUN 1 R1 Z11 C13 Z13 Z15 Z17 Z19 Z21 C17 RF INPUT Z1 C9 Z2 C Z3 Z4 Z5 Z6 Z7 Z8 Z9 C12 Z DUT C15 C16 C18 RF OUTPUT Z23 C11 Z12 Z14 Z16 Z18 Z Z22 V BIAS + R2 C14 L2 C19 C BALUN 2 C5 C6 C7 C8 + + V SUPPLY C25 C26 C27 C28 Z x Z x Z3, Z x 0.2 Z5, Z x Z7, Z x Z9, Z x Z11, Z x Z13, Z x Z15, Z x Z17, Z x Z19, Z x Z21, Z x Z x PCB Arlon CuClad 250GX , 0.030, r =2.55 Figure 2. MMRF07HR5(HSR5) Test Circuit Schematic Table 5. MMRF07HR5(HSR5) Test Circuit Component Designations and Values Part Description Manufacturer Part Number Balun 1, 2 Balun Anaren 3A412 Anaren C1, C5 22 F, 25 V Tantalum Capacitors TPSD226M025R AVX C2, C6 2.2 F, 50 V Chip Capacitors C1825C225J5RAC Kemet C3, C F, 0 V Chip Capacitors C12C224K1RAC Kemet C4, C8, C17, C18, C19, 36 pf Chip Capacitors ATC0B360JT500XT ATC C, C21, C25 C9 1.0 pf Chip Capacitor ATC0B1R0CT500XT ATC C12, C pf Variable Capacitors 27291SL Johanson C, C11, C13, C14, C pf Chip Capacitors ATC0B5R1CT500XT ATC C22, C F, 0 V Chip Capacitors C1825C223K1GAC Kemet C23, C24, C27, C F, 63 V Electrolytic Capacitors MCGPR63V477M13X26--RH Multicomp L1, L2 Inductors 3 Turn GA3094--AL Coilcraft R1, R2 00, 1/3 W Chip Resistors CRCW1201FKEA Vishay 4

5 C24 C1 C2 C3 C4 C21 C22 C23 -- BALUN 1 R1 C13 L1 BALUN 2 C C12 C15 C16 C17 C18 C9 C11 C6 R2 C8 C7 CUT OUT AREA C14 L2 C25 C26 C19 C C5 C27 -- C28 Figure 3. MMRF07HR5(HSR5) Test Circuit Component Layout 5

6 TYPICAL CHARACTERISTICS C, CAPACITANCE (pf) 00 0 C oss C rss C iss Measured with 30 1 MHz V GS =0Vdc G ps, POWER GAIN (db) V DD =50Vdc I DQ = 150 ma f = 30 MHz Pulse Width = 128 sec Duty Cycle = % G ps D D, DRAIN EFFICIENCY (%) V DS, DRAIN--SOURCE VOLTAGE (VOLTS) Note: Each side of device measured separately. Figure 4. Capacitance versus Drain -Source Voltage P out, OUTPUT POWER (WATTS) PEAK Figure 5. Power Gain and Drain Efficiency versus Output Power G ps, POWER GAIN (db) P1dB = 65 W (60.3 dbm) P3dB = 1182 W (60.7 dbm) Ideal 19.5 V DD =50Vdc 19 I DQ = 150 ma f = 30 MHz 18.5 Pulse Width = 128 sec Actual 18 Duty Cycle = % P out, OUTPUT POWER (WATTS) PEAK Figure 6. Power Gain versus Output Power G ps, POWER GAIN (db) I DQ = 6000 ma 3000 ma 1500 ma 750 ma 375 ma 150 ma 0 V DD =50Vdc f = 30 MHz Pulse Width = 128 sec Duty Cycle = % P out, OUTPUT POWER (WATTS) PEAK Figure 7. Power Gain versus Output Power G ps, POWER GAIN (db) I DQ = 150 ma, f = 30 MHz Pulse Width = 128 sec Duty Cycle = % V DD =30V 35 V 40 V 45 V P out, OUTPUT POWER (WATTS) PEAK 50 V Figure 8. Power Gain versus Output Power P out, OUTPUT POWER (dbm) _C 25_C 25 T C =--30_C P in, INPUT POWER (dbm) PEAK V DD =50Vdc I DQ = 150 ma f = 30 MHz Pulse Width = 128 sec Duty Cycle = % Figure 9. Output Power versus Input Power 45 6

7 TYPICAL CHARACTERISTICS G ps, POWER GAIN (db) V DD =50Vdc I DQ = 150 ma f = 30 MHz Pulse Width = 128 sec Duty Cycle = % 25_C 85_C T C =--30_C D 0 G ps P out, OUTPUT POWER (WATTS) PEAK Figure. Power Gain and Drain Efficiency versus Output Power D, DRAIN EFFICIENCY (%) MTTF (HOURS) 7 6 MTTF (HOURS) T J, JUNCTION TEMPERATURE ( C) This above graph displays calculated MTTF in hours when the device is operated at V DD =50Vdc,P out = 00 W Peak, Pulse Width = 128 sec, Duty Cycle = %, and D = 56%. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. Figure 11. MTTF versus Junction Temperature sec, % Duty Cycle T J, JUNCTION TEMPERATURE ( C) Figure 12. MTTF versus Junction Temperature - Mode -S 250 This above graph displays calculated MTTF in hours when the device is operated at V DD =50Vdc,P out = 00 W Peak, Mode--S Pulse Train, Pulse Width = 32 sec, Duty Cycle = 6.4%, and D = 59%. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. 7

8 Z o =5 f = 30 MHz Z load f = 30 MHz Z source V DD =50Vdc,I DQ = 150 ma, P out = 00 W Peak f MHz Z source Z load j j1.42 Z source = Test circuit impedance as measured from gate to gate, balanced configuration. Z load = Test circuit impedance as measured from drain to drain, balanced configuration. Input Matching Network + Device Under Test -- Output Matching Network -- + Z source Z load Figure 13. Series Equivalent Source and Load Impedance 8

9 -- C24 C1 C2 C3 C4 C21 C22 C23 -- BALUN 1 R1 C13 L1 BALUN 2 C C12 C29 C16 C15 C17 C18 C9 C11 C6 R2 C8 C7 CUT OUT AREA C14 L2 C25 C26 C19 C -- C5 C27 C28 Figure 14. MMRF07HR5(HSR5) Test Circuit Component Layout 90 MHz Table 6. MMRF07HR5(HSR5) Test Circuit Component Designations and Values 90 MHz Part Description Manufacturer Part Number Balun 1, 2 Balun Anaren 3A412 Anaren C1, C5 22 F, 25 V Tantalum Capacitors TPSD226M025R00 AVX C2, C6 2.2 F, 50 V 1825 Chip Capacitors C1825C225J5RAC--TU Kemet C3, C F, 0 V Chip Capacitors C12C224K1RAC--TU Kemet C4, C8, C17, C18, C19, 36 pf Chip Capacitors ATC0B360JT500XT ATC C, C21, C25 C9 1.0 pf Chip Capacitor ATC0B1R0BT500XT ATC C12, C pf Variable Capacitors 27291SL Johanson C, C11, C13, C14, C15, 5.1 pf Chip Capacitors ATC0B5R1CT500XT ATC C29 C22, C F, 0 V Chip Capacitors C1825C223K1GAC Kemet C23, C24, C27, C F, 63 V Electrolytic Capacitors MCGPR63V477M13X26--RH Multicomp L1, L2 Inductors 3 Turn GA3094--ALC Coilcraft R1, R2 00, 1/4 W Chip Resistors CRCW161K00FKEA Vishay PCB CuClad, 0.030, r = GX Arlon 9

10 TYPICAL CHARACTERISTICS 90 MHZ G ps, POWER GAIN (db) V DD =50Vdc I DQ = 150 ma f = 90 MHz Pulse Width = 128 sec Duty Cycle = % G ps D D, DRAIN EFFICIENCY (%) 16 0 P out, OUTPUT POWER (WATTS) PEAK Figure 15. Power Gain and Drain Efficiency versus Output Power

11 Z o =5 f = 90 MHz Z source f = 90 MHz Z load V DD =50Vdc,I DQ = 150 ma, P out = 00 W Peak f MHz Z source Z load j j2.02 Z source = Test circuit impedance as measured from gate to gate, balanced configuration. Z load = Test circuit impedance as measured from drain to drain, balanced configuration. Input Matching Network + Device Under Test -- Output Matching Network -- + Z source Z load Figure 16. Series Equivalent Source and Load Impedance 90 MHz 11

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16 PRODUCT DOCUMENTATION Refer to the following documents to aid your design process. Application Notes AN1955: Thermal Measurement Methodology of RF Power Amplifiers Engineering Bulletins EB212: Using Data Sheet Impedances for RF LDMOS Devices REVISION HISTORY The following table summarizes revisions to this document. Revision Date Description 0 Dec. 13 Initial Release of Data Sheet 16

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