RF LDMOS Wideband Integrated Power Amplifiers

Transcription

1 Technical Data RF LDMOS Wideband Integrated Power Amplifiers The MD7IC2250N wideband integrated circuit is designed with on--chip matching that makes it usable from 2000 to 2200 MHz. This multi--stage structure is rated for 24 to 32 Volt operation and covers all typical cellular base station modulation formats. Typical Single--Carrier W--CDMA Performance: V DD =28Volts, I DQ1(A+B) =80mA,I DQ2(A+B) = 520 ma, P out = 5.3 Watts Avg., IQ Magnitude Clipping, Channel Bandwidth = 3.84 MHz, Input Signal PAR = % Probability on CCDF. Frequency G ps (db) PAE (%) ACPR (dbc) 2110 MHz MHz MHz Capable of Handling 10:1 32 Vdc, 2140 MHz, 63 Watts CW Output Power (3 db Input Overdrive from Rated P out ) Typical P 1 db Compression Point 54 Watts CW Features Characterized with Series Equivalent Large--Signal Impedance Parameters and Common Source S--Parameters On--Chip Matching (50 Ohm Input, DC Blocked) Integrated Quiescent Current Temperature Compensation with Enable/Disable Function (1) Integrated ESD Protection Designed for Digital Predistortion Error Correction Systems Optimized for Doherty Applications 225 C Capable Plastic Package RoHS Compliant In Tape and Reel. R1 Suffix = 500 Units, 44 mm Tape Width, 13 inch Reel. Document Number: MD7IC2250N Rev. 0, 12/2010 MD7IC2250NR1 MD7IC2250GNR1 MD7IC2250NBR MHz, 5.3 W AVG., 28 V SINGLE W -CDMA RF LDMOS WIDEBAND INTEGRATED POWER AMPLIFIERS CASE TO -270 WB -14 PLASTIC MD7IC2250NR1 CASE TO -272 WB -14 PLASTIC MD7IC2250NBR1 CASE TO -270 WB -14 GULL PLASTIC MD7IC2250GNR1 V DS1A RF ina V GS1A V GS2A V GS1B V GS2B Quiescent Current Temperature Compensation (1) Quiescent Current Temperature Compensation (1) RF out1 /V DS2A V DS1A V GS2A 1 2 V GS1A 3 RF ina NC 4 5 NC 6 NC 7 NC 8 RF inb V GS1B 10 V GS2B 11 V DS1B RF out1 /V DS2A RF out2 /V DS2B RF inb V DS1B RF out2 /V DS2B (Top View) Note: Exposed backside of the package is the source terminal for the transistors. Figure 1. Functional Block Diagram Figure 2. Pin Connections 1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to Select Documentation/Application Notes -- AN1977 or AN1987., Inc., All rights reserved. 1

2 Table 1. Maximum Ratings Rating Symbol Value Unit Drain--Source Voltage V DSS --0.5, +65 Vdc Gate--Source Voltage V GS --0.5, +10 Vdc Operating Voltage V DD 32, +0 Vdc Storage Temperature Range T stg to +150 C Case Operating Temperature T C 150 C Operating Junction Temperature (1,2) T J 225 C Input Power P in 28 dbm Table 2. Thermal Characteristics Thermal Resistance, Junction to Case Case Temperature 74 C, 5.3 W CW, 2170 MHz Stage 1, 28 Vdc, I DQ1(A+B) =80mA Stage 2, 28 Vdc, I DQ2(A+B) = 520 ma Case Temperature 80 C, 50 W CW, 2170 MHz Stage 1, 28 Vdc, I DQ1(A+B) =80mA Stage 2, 28 Vdc, I DQ2(A+B) = 520 ma Table 3. ESD Protection Characteristics Human Body Model (per JESD22--A114) Machine Model (per EIA/JESD22--A115) Characteristic Symbol Value (2,3) Unit Test Methodology Charge Device Model (per JESD22--C101) Table 4. Moisture Sensitivity Level R θjc Class 1A (Minimum) A (Minimum) II (Minimum) Test Methodology Rating Package Peak Temperature Unit Per JESD22--A113, IPC/JEDEC J--STD C Table 5. Electrical Characteristics (T A =25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Stage 1 - Off Characteristics (4) Zero Gate Voltage Drain Leakage Current (V DS =65Vdc,V GS =0Vdc) I DSS 10 μadc Zero Gate Voltage Drain Leakage Current (V DS =28Vdc,V GS =0Vdc) Gate--Source Leakage Current (V GS =1.5Vdc,V DS =0Vdc) Stage 1 - On Characteristics Gate Threshold Voltage (4) (V DS =10Vdc,I D =23μAdc) Gate Quiescent Voltage (V DS =28Vdc,I DQ1(A+B) =80mA) Fixture Gate Quiescent Voltage (V DD =28Vdc,I DQ1(A+B) = 80 ma, Measured in Functional Test) C/W I DSS 1 μadc I GSS 1 μadc V GS(th) Vdc V GS(Q) 2.7 Vdc V GG(Q) Vdc 1. Continuous use at maximum temperature will affect MTTF. 2. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. 3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to Select Documentation/Application Notes -- AN Each side of device measured separately. (continued) 2

3 Table 5. Electrical Characteristics (T A =25 C unless otherwise noted) (continued) Stage 2 - Off Characteristics (1) Zero Gate Voltage Drain Leakage Current (V DS =65Vdc,V GS =0Vdc) Zero Gate Voltage Drain Leakage Current (V DS =28Vdc,V GS =0Vdc) Gate--Source Leakage Current (V GS =1.5Vdc,V DS =0Vdc) Characteristic Symbol Min Typ Max Unit I DSS 10 μadc I DSS 1 μadc I GSS 1 μadc Stage 2 - On Characteristics Gate Threshold Voltage (1) (V DS =10Vdc,I D = 150 μadc) Gate Quiescent Voltage (V DS =28Vdc,I DQ2(A+B) = 520 ma) Fixture Gate Quiescent Voltage (V DD =28Vdc,I DQ2(A+B) = 520 ma, Measured in Functional Test) Drain--Source On--Voltage (1) (V GS =10Vdc,I D =1Adc) V GS(th) Vdc V GS(Q) 2.7 Vdc V GG(Q) Vdc V DS(on) Vdc Functional Tests (2,3) (In Freescale Wideband Test Fixture, 50 ohm system) V DD =28Vdc,I DQ1(A+B) =80mA, I DQ2(A+B) = 520 ma, P out = 5.3 W Avg., f = 2170 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = % Probability on CCDF. ACPR measured in 3.84 MHz Channel ±5 MHzOffset. Power Gain G ps db Power Added Efficiency PAE % Adjacent Channel Power Ratio ACPR dbc Input Return Loss IRL db Typical Broadband Performance (In Freescale Test Fixture, 50 ohm system) V DD =28Vdc,I DQ1(A+B) =80mA,I DQ2(A+B) = 520 ma, P out = 5.3 W Avg., Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = % Probability on CCDF. ACPR measured in 3.84 MHz Channel ±5 MHzOffset. Frequency G ps (db) PAE (%) ACPR (dbc) 2110 MHz MHz MHz IRL (db) 1. Each side of device measured separately. 2. Part internally matched both on input and output. 3. Measurement made with device in straight lead configuration before any lead forming operation is applied. (continued) 3

4 Table 5. Electrical Characteristics (T A =25 C unless otherwise noted) (continued) Characteristic Symbol Min Typ Max Unit Typical Performance (In Freescale Test Fixture, 50 ohm system) V DD =28Vdc,I DQ1(A+B) =80mA,I DQ2(A+B) = 520 ma, MHz Bandwidth P 1 db Compression Point, CW P1dB 54 W IMD 50 W PEP, P out where IMD Third Order IMD sym MHz Intermodulation 30 dbc (Delta IMD Third Order Intermodulation between Upper and Lower Sidebands > 2 db) 16 VBW Resonance Point (IMD Third Order Intermodulation Inflection Point) Quiescent Current Accuracy over Temperature (1,2) with 4.7 kω Gate Feed Resistors (--30 to 85 C) Stage 1 Stage 2 VBW res 70 MHz I QT Gain Flatness in 60 MHz P out =5.3WAvg. G F 0.1 db Gain Variation over Temperature (--30 C to+85 C) G db/ C % Output Power Variation over Temperature (--30 C to+85 C) P1dB db/ C 1. Each side of device measured separately. 2. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to Documentation/Application Notes -- AN1977 or AN

5 V D1A V G1A R1 V G2A R2 C1 C12 C5 C7 C14 C3 V D2 C18 C9 R3 V G1B V G2B C16 C20 C17 C19 R4 C2 C13 C6 CUT OUT AREA C8 C10 C15 C21 C4 MD7IC2250N Rev. 2 V D2 C11 V D1B Figure 3. MD7IC2250NR1(GNR1)(NBR1) Test Circuit Component Layout Table 6. MD7IC2250NR1(GNR1)(NBR1) Test Circuit Component Designations and Values Part Description Part Number Manufacturer C1, C2, C3, C4 10 μf Chip Capacitors GRM55DR61H106KA88L Murata C5, C6, C7, C8 5.6 pf Chip Capacitors ATC600F5R6BT250XT ATC C9, C pf Chip Capacitors ATC600F2R0BT250XT ATC C11 33 pf Chip Capacitor ATC600F330JT250XT ATC C12, C μf Chip Capacitors GRM31MR71H105KA88L Murata C14, C15, C16, C17, C18, C μf Chip Capacitors GRM31CR71H475KA12L Murata C pf Chip Capacitor ATC600F1R8BT250XT ATC C pf Chip Capacitor ATC100B1R5BT500XT ATC R1, R2, R3, R4 4.7 kω Chip Resistors CRCW12064K70FKEA Vishay PCB 0.020, ε r =3.5 RF35A2 Taconic 5

6 Single--ended λ λ 4 4 Quadrature combined λ 4 Doherty λ 2 λ 2 Push--pull Figure 4. Possible Circuit Topologies 6

7 TYPICAL CHARACTERISTICS G ps, POWER GAIN (db) V DD =28Vdc,P out =5.3W(Avg.),I DQ1(A+B) =80mA I DQ2(A+B) = 520 ma ACPR f, FREQUENCY (MHz) Figure 5. Power Gain, Power Added Efficiency, IRL and ACPR Broadband P out = 5.3 Watts Avg. PAE Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth Input Signal PAR = % Probability on CCDF G ps IRL PAE, POWER ADDED EFFICIENCY (%) ACPR (dbc) IRL, INPUT RETURN LOSS (db) IMD, INTERMODULATION DISTORTION (dbc) V DD =28Vdc,P out = 50 W (PEP), I DQ1(A+B) =80mA I DQ2(A+B) = 520 ma, Two--Tone Measurements (f1 + f2)/2 = Center Frequency of 2140 MHz IM7--L IM7--U IM3--U IM5--L IM5--U IM3--L TWO--TONE SPACING (MHz) Figure 6. Intermodulation Distortion Products versus Two -Tone Spacing G ps, POWER GAIN (db) OUTPUT COMPRESSION AT 0.01% PROBABILITY ON CCDF (db) G ps PAE ACPR V DD =28Vdc,I DQ1(A+B) =80mA,I DQ2(A+B) = 520 ma f = 2140 MHz, Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth, Input Signal PAR = % Probability on CCDF --1 db = 13 W --2 db = 18 W PARC --3 db = 24 W PAE, POWER ADDED EFFICIENCY (%) ACPR (dbc) P out, OUTPUT POWER (WATTS) Figure 7. Output Peak -to -Average Ratio Compression (PARC) versus Output Power

8 TYPICAL CHARACTERISTICS G ps, POWER GAIN (db) V DD =28Vdc,I DQ1(A+B) =80mA,I DQ2(A+B) = 520 ma Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth Input Signal PAR = % Probability on CCDF 2140 MHz 2170 MHz 2110 MHz 2170 MHz 2140 MHz 2110 MHz PAE ACPR G ps PAE, POWER ADDED EFFICIENCY (%) ACPR (dbc) P out, OUTPUT POWER (WATTS) AVG. Figure 8. Single -Carrier W -CDMA Power Gain, Power Added Efficiency and ACPR versus Output Power Gain GAIN (db) V DD =28Vdc --30 P in =0dBm IRL I DQ1(A+B) =80mA I DQ2(A+B) = 520 ma --20 IRL (db) f, FREQUENCY (MHz) Figure 9. Broadband Frequency Response 8

9 W -CDMA TEST SIGNAL PROBABILITY (%) Input Signal W--CDMA. ACPR Measured in 3.84 MHz Channel ±5 MHzOffset. Input Signal PAR = % Probability on CCDF PEAK--TO--AVERAGE (db) Figure 10. CCDF W -CDMA IQ Magnitude Clipping, Single -Carrier Test Signal 10 (db) ACPR in 3.84 MHz Integrated BW 3.84 MHz Channel BW +ACPRin3.84MHz Integrated BW f, FREQUENCY (MHz) Figure 11. Single -Carrier W -CDMA Spectrum 9

10 V DD =28Vdc,I DQ1(A+B) = 80 ma,i DQ2(A+B) = 520 ma, P out =5.3WAvg. f MHz Z source Ω Z load Ω j j j j j j j j j j j j j j j j j j4.82 Z source = Test circuit impedance as measured from gate to ground. Z load = Test circuit impedance as measured from drain to ground. Input Matching Network Device Under Test Output Matching Network Z source Z load Figure 12. Series Equivalent Source and Load Impedance 10

11 ALTERNATIVE PEAK TUNE LOAD PULL CHARACTERISTICS P out, OUTPUT POWER (dbm) V DD =28Vdc, I DQ1A =40mA,I DQ2A = 260 ma, Pulsed CW, 10 μsec(on), 10% Duty Cycle Ideal Actual MHz 2110 MHz MHz MHz 2170 MHz 2110 MHz P in, INPUT POWER (dbm) NOTE: Load Pull Test Fixture Tuned for Peak P1dB Output 28 V f (MHz) P1dB P3dB Watts dbm Watts dbm f (MHz) Test Impedances per Compression Level Z source Ω Z load Ω 2110 P1dB j j P1dB j j P1dB j j14.5 Figure 13. Pulsed CW Output Power versus Input 28 V Note: Measurement made on a single path of the device under Class AB conditions. 11

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21 PRODUCT DOCUMENTATION, TOOLS AND SOFTWARE Refer to the following documents, tools and software to aid your design process. Application Notes AN1907: Solder Reflow Attach Method for High Power RF Devices in Plastic Packages AN1955: Thermal Measurement Methodology of RF Power Amplifiers AN1977: Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family AN3263: Bolt Down Mounting Method for High Power RF Transistors and RFICs in Over--Molded Plastic Packages AN3789: Clamping of High Power RF Transistors and RFICs in Over--Molded Plastic Packages Engineering Bulletins EB212: Using Data Sheet Impedances for RF LDMOS Devices Software Electromigration MTTF Calculator RF High Power Model.s2p File For Software and Tools, do a Part Number search at and select the Part Number link. Go to the Software & Tools tab on the part s Product Summary page to download the respective tool. The following table summarizes revisions to this document. REVISION HISTORY Revision Date Description 0 Dec Initial Release of Data Sheet 21

22 How to Reach Us: Home Page: Web Support: USA/Europe or Locations Not Listed:, Inc. Technical Information Center, EL East Elliot Road Tempe, Arizona or Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen Muenchen, Germany (English) (English) (German) (French) Japan: Japan Ltd. Headquarters ARCO Tower 15F , Shimo--Meguro, Meguro--ku, Tokyo Japan or support.japan@freescale.com Asia/Pacific: China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing China support.asia@freescale.com For Literature Requests Only: Literature Distribution Center or Fax: LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. reserves the right to make changes without further notice to any products herein. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals, must be validated for each customer application by customer s technical experts. does not convey any license under its patent rights nor the rights of others. products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should Buyer purchase or use products for any such unintended or unauthorized application, Buyer shall indemnify and hold and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescalet and the Freescale logo are trademarks of, Inc. All other product or service names are the property of their respective owners., Inc All rights reserved. Document Number: MD7IC2250N 22 Rev. 0, 12/2010