Characteristic Symbol Value (2,3) Unit. Test Methodology

Transcription

1 Freescale Semiconductor Technical Data RF LDMOS Wideband Integrated Power Amplifiers The MD7IC2251N wideband integrated circuit is designed with on--chip matching that makes it usable from MHz. This multi--stage structure is rated for 26 to 32 volt operation and covers all typical cellular base station modulation formats. Typical Doherty Single--Carrier W--CDMA Characterization Performance: V DD =28Volts,I DQ1(A+B) =80mA,I DQ2A = 260 ma, V GS2B =1.4Vdc, P out = 12 Watts Avg., IQ Magnitude Clipping, Channel Bandwidth = 3.84 MHz, Input Signal PAR = % Probability on CCDF. Frequency G ps (db) PAE (%) Output PAR (db) ACPR (dbc) 2110 MHz MHz MHz Document Number: MD7IC2251N Rev. 0, 5/2012 MD7IC2251NR1 MD7IC2251GNR MHz, 12 W AVG., 28 V SINGLE W -CDMA RF LDMOS WIDEBAND INTEGRATED POWER AMPLIFIERS TO -270 WB -14 PLASTIC MD7IC2251NR1 Capable of Handling 10:1 32 Vdc, 2140 MHz, 63 Watts CW Output Power (3 db Input Overdrive from Rated P out ) Typical P 3 db Compression Point 58 Watts (1) Features 100% PAR Tested for Guaranteed Output Power Capability Production Tested in a Symmetrical Doherty Configuration Characterized with Large--Signal Load--Pull Parameters and Common Source S--Parameters On--Chip Matching (50 Ohm Input, DC Blocked) Integrated Quiescent Current Temperature Compensation with Enable/Disable Function (2) Integrated ESD Protection 225 C Capable Plastic Package In Tape and Reel. R1 Suffix = 500 Units, 44 mm Tape Width, 13 inch Reel. TO -270 WB -14 GULL PLASTIC MD7IC2251GNR1 V DS1A RF ina V GS1A V GS2A V GS1B V GS2B RF inb V DS1B Quiescent Current Temperature Compensation (2) Quiescent Current Temperature Compensation (2) CARRIER (3) RF out1 /V DS2A PEAKING (3) RF out2 /V DS2B 9 Carrier V DS1A V GS2A 1 2 V GS1A 3 RF ina NC 4 5 NC 6 NC 7 NC 8 RF inb V GS1B 10 V GS2B 11 V DS1B 12 Peaking (Top View) RF out1 /V DS2A Note: Exposed backside of the package is the source terminal for the transistors RF out2 /V DS2B Figure 1. Functional Block Diagram Figure 2. Pin Connections 1. P3dB = P avg db where P avg is the average output power measured using an unclipped W--CDMA single--carrier input signal where output PAR is compressed to % probability on CCDF. 2. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to Select Documentation/Application Notes -- AN1977 or AN Peaking and Carrier orientation is determined by the test fixture design., All rights reserved. 1

2 Table 1. Maximum Ratings Rating Symbol Value Unit Drain--Source Voltage V DS --0.5, +65 Vdc Gate--Source Voltage V GS --0.5, +10 Vdc Operating Voltage V DD 32, +0 Vdc Storage Temperature Range T stg to +150 C Case Operating Temperature T C 150 C Operating Junction Temperature (1,2) T J 225 C Input Power P in 28 dbm Table 2. Thermal Characteristics Final Doherty Application Thermal Resistance, Junction to Case Case Temperature 78 C, P out =12WCW Stage 1, 28 Vdc, I DQ1(A+B) =80mA Stage 2, 28 Vdc, I DQ2A = 260 ma, V GS2B =1.4Vdc Case Temperature 89 C, P out =50WCW Stage 1, 28 Vdc, I DQ1(A+B) =80mA Stage 2, 28 Vdc, I DQ2A = 260 ma, V GS2B =1.4Vdc Table 3. ESD Protection Characteristics Human Body Model (per JESD22--A114) Machine Model (per EIA/JESD22--A115) Charge Device Model (per JESD22--C101) Table 4. Moisture Sensitivity Level Characteristic Symbol Value (2,3) Unit Test Methodology R θjc Class Test Methodology Rating Package Peak Temperature Unit Per JESD22--A113, IPC/JEDEC J--STD C Table 5. Electrical Characteristics (T A =25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Stage 1 - Off Characteristics (4) Zero Gate Voltage Drain Leakage Current (V DS =65Vdc,V GS =0Vdc) Zero Gate Voltage Drain Leakage Current (V DS =28Vdc,V GS =0Vdc) Gate--Source Leakage Current (V GS =1.5Vdc,V DS =0Vdc) Stage 1 - On Characteristics (4) Gate Threshold Voltage (V DS =10Vdc,I D =23μAdc) Gate Quiescent Voltage (V DS =28Vdc,I DQ1(A+B) =80mAdc) Fixture Gate Quiescent Voltage (V DD =28Vdc,I DQ1(A+B) = 80 madc, Measured in Functional Test) 1A A II C/W I DSS 10 μadc I DSS 1 μadc I GSS 1 μadc V GS(th) Vdc V GS(Q) 2.7 Vdc V GG(Q) Vdc 1. Continuous use at maximum temperature will affect MTTF. 2. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. 3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to Select Documentation/Application Notes -- AN Each side of device measured separately. (continued) 2

3 Table 5. Electrical Characteristics (T A =25 C unless otherwise noted) (continued) Stage 2 - Off Characteristics (1) Zero Gate Voltage Drain Leakage Current (V DS =65Vdc,V GS =0Vdc) Characteristic Symbol Min Typ Max Unit I DSS 10 μadc Zero Gate Voltage Drain Leakage Current (V DS =28Vdc,V GS =0Vdc) Gate--Source Leakage Current (V GS =1.5Vdc,V DS =0Vdc) Stage 2 - On Characteristics (1) Gate Threshold Voltage (V DS =10Vdc,I D = 150 μadc) Gate Quiescent Voltage (V DS =28Vdc,I DQ2A = 260 madc) Fixture Gate Quiescent Voltage (V DD =28Vdc,I DQ2A = 260 madc, Measured in Functional Test) Drain--Source On--Voltage (V GS =10Vdc,I D =1Adc) I DSS 1 μadc I GSS 1 μadc V GS(th) Vdc V GSA(Q) 2.7 Vdc V GGA(Q) Vdc V DS(on) Vdc Functional Tests (2,3,4) (In Freescale Doherty Production Test Fixture, 50 ohm system) V DD =28Vdc,I DQ1(A+B) =80mA,I DQ2A = 260 ma, V GS2B =1.4Vdc,P out = 12 W Avg., f = 2140 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = % Probability on CCDF. ACPR measured in 3.84 MHz Channel ±5 MHzOffset. Power Gain G ps db Power Added Efficiency PAE % Output Peak--to--Average 0.01% Probability on CCDF PAR db Adjacent Channel Power Ratio ACPR dbc Typical Broadband Performance (In Freescale Doherty Characterization Test Fixture, 50 ohm system) V DD =28Vdc,I DQ1(A+B) =80mA, I DQ2A = 260 ma, V GS2B =1.4Vdc,P out = 12 W Avg., Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = % Probability on CCDF. ACPR measured in 3.84 MHz Channel ±5 MHz Offset. Frequency G ps (db) PAE (%) Output PAR (db) ACPR (dbc) 2110 MHz MHz MHz Each side of device measured separately. 2. Part internally matched both on input and output. 3. Measurement made with device in a Symmetrical Doherty configuration. 4. Measurement made with device in straight lead configuration before any lead forming operation is applied. (continued) 3

4 Table 5. Electrical Characteristics (T A =25 C unless otherwise noted) (continued) Characteristic Symbol Min Typ Max Unit Typical Performances (1) (In Freescale Doherty Test Fixture, 50 ohm system) V DD =28Vdc,I DQ1(A+B) =80mA,I DQ2A = 260 ma, V GS2B = 1.4 Vdc, MHz Bandwidth P 1 db Compression Point, CW P1dB 40 W P 3 db Compression Point (2) P3dB 58 W IMD 18 W PEP, P out where IMD Third Order Intermodulation 30 dbc (Delta IMD Third Order Intermodulation between Upper and Lower Sidebands > 2 db) VBW Resonance Point (IMD Third Order Intermodulation Inflection Point) Quiescent Current Accuracy over Temperature with 4.7 kω Gate Feed Resistors (--30 to 85 C) (3) Stage 1 Stage 2 IMD sym 25 MHz VBW res 65 MHz I QT Gain Flatness in 60 MHz P out =12WAvg. G F 0.2 db Gain Variation over Temperature (--30 C to+85 C) G db/ C % Output Power Variation over Temperature (--30 C to+85 C) P1dB db/ C 1. Measurement made with device in a Symmetrical Doherty configuration. 2. P3dB = P avg db where P avg is the average output power measured using an unclipped W--CDMA single--carrier input signal where output PAR is compressed to % probability on CCDF. 3. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to Select Documentation/Application Notes -- AN1977 or AN

5 V GS1A V GS2A V DS1A C1 V DS2A R1 R2 C23 C19 C15 C7 C16 C9 C13 C11 C3 C4 R5 Z1 CUT OUT AREA C P R3 R4 C17 C20 C22 C18 C8 C21 MD7IC2251N Rev. 1 C2 V GS1B V GS2B V V DS2B DS1B C10 C14 C12 C5 C6 Figure 3. MD7IC2251NR1(GNR1) Production Test Circuit Component Layout Table 6. MD7IC2251NR1(GNR1) Production Test Circuit Component Designations and Values Part Description Part Number Manufacturer C1, C2, C3, C4, C5, C6 10 μf Chip Capacitors GRM55DR61H106KA88L Murata C7, C8 4.7 pf Chip Capacitors ATC600F4R7BT250XT ATC C9, C pf Chip Capacitors ATC600F5R6BT250XT ATC C11, C12 39 pf Chip Capacitors ATC600F390JT250XT ATC C13, C14, C15, C16, C17, C μf Chip Capacitors GRM31CR71H475KA12L Murata C19, C pf Chip Capacitors ATC600F0R5BT250XT ATC C pf Chip Capacitor ATC600F0R9BT250XT ATC C22, C μf Chip Capacitors GRM31CR71H105KA12L Murata R1, R2, R3, R4 4.7 kω, 1/4 W Chip Resistors CRCW12064K70FKEA Vishay R5 50 Ω, 10 W, Termination RFP-06012A15Z50 Anaren Z MHz, 90, 3 db Chip Hybrid Coupler GSC355-HYB2150 Soshin PCB 0.020, ε r =3.5 RF-35A2 Taconic 5

6 V GS1A V GS2A V DS1A C1 V DS2A R1 R2 C23 C19 C15 C7 C16 C9 C13 C11 C3 C4 R5 Z1 CUT OUT AREA C P R3 R4 C17 C20 C22 C18 C8 C21 MD7IC2251N Rev. 1 C2 V GS1B V GS2B V V DS2B DS1B C10 C14 C12 C5 C6 Figure 4. MD7IC2251NR1(GNR1) Characterization Test Circuit Component Layout Table 7. MD7IC2251NR1(GNR1) Characterization Test Circuit Component Designations and Values Part Description Part Number Manufacturer C1, C2, C3, C4, C5, C6 10 μf Chip Capacitors GRM55DR61H106KA88L Murata C7, C8 4.7 pf Chip Capacitors ATC600F4R7BT250XT ATC C9, C pf Chip Capacitors ATC600F5R6BT250XT ATC C11, C12 39 pf Chip Capacitors ATC600F390JT250XT ATC C13, C14, C15, C16, C17, C μf Chip Capacitors GRM31CR71H475KA12L Murata C19, C pf Chip Capacitors ATC600F0R5BT250XT ATC C pf Chip Capacitor ATC600F0R9BT250XT ATC C22, C μf Chip Capacitors GRM31CR71H105KA12L Murata R1, R2, R3, R4 4.7 kω, 1/4 W Chip Resistors CRCW12064K70FKEA Vishay R5 50 Ω, 10 W, Termination RFP-06012A15Z50 Anaren Z MHz, 90, 3 db Chip Hybrid Coupler GSC355-HYB2150 Soshin PCB 0.020, ε r =3.5 RF-35A2 Taconic 6

7 TYPICAL CHARACTERISTICS G ps, POWER GAIN (db) V DD =28Vdc,P out =12W(Avg.) I DQ1(A+B) =80mA,I DQ2A = 260 ma V GS2B = 1.4 Vdc, Single--Carrier W--CDMA 3.84 MHz Channel Bandwidth Input Signal PAR = % Probability on CCDF f, FREQUENCY (MHz) ACPR Figure 5. Output Peak -to -Average Ratio Compression (PARC) Broadband P out = 12 Watts Avg. PAE G ps PARC PAE, POWER ADDED EFFICIENCY (%) ACPR (dbc) PARC (db) IMD, INTERMODULATION DISTORTION (dbc) V DD =28Vdc,P out = 18 W (PEP) I DQ1(A+B) =80mA,I DQ2A = 260 ma IM5--U V GS2B = 1.4 Vdc, Two--Tone Measurements (f1 + f2)/2 = Center Frequency of 2140 MHz IM3--U IM5--L IM3--L IM7--U IM7--L TWO--TONE SPACING (MHz) Figure 6. Intermodulation Distortion Products versus Two -Tone Spacing G ps, POWER GAIN (db) OUTPUT COMPRESSION AT 0.01% PROBABILITY ON CCDF (db) G ps --1dB=7.2W --2dB=9.9W --3dB=12.5W MHz Channel Bandwidth, Input Signal PAR = % Probability on CCDF PAE ACPR V DD =28Vdc,I DQ1(A+B) =80mA I DQ2A = 260 ma, V GS2B =1.4Vdc f = 2140 MHz, Single--Carrier W--CDMA PARC PAE, POWER ADDED EFFICIENCY (%) ACPR (dbc) P out, OUTPUT POWER (WATTS) Figure 7. Output Peak -to -Average Ratio Compression (PARC) versus Output Power 7

8 TYPICAL CHARACTERISTICS G ps, POWER GAIN (db) P out, OUTPUT POWER (WATTS) AVG. ACPR Figure 8. Single -Carrier W -CDMA Power Gain, Power Added Efficiency and ACPR versus Output Power 36 V DD =28Vdc,I DQ1(A+B) =80mA I DQ2A = 260 ma, V GS2B =1.4Vdc Single--Carrier W--CDMA 3.84 MHz Channel Bandwidth Input Signal PAR = % Probability on CCDF 2110 MHz 2140 MHz 2170 MHz PAE 2140 MHz 2110 MHz 2170 MHz G ps PAE, POWER ADDED EFFICIENCY (%) ACPR (dbc) Gain GAIN (db) V DD =28Vdc P in =0dBm I DQ1(A+B) =80mA 6 I DQ2A = 260 ma V GS2B =1.4Vdc f, FREQUENCY (MHz) Figure 9. Broadband Frequency Response W -CDMA TEST SIGNAL PROBABILITY (%) Input Signal W--CDMA. ACPR Measured in 3.84 MHz Channel ±5 MHzOffset. Input Signal PAR = % Probability on CCDF PEAK--TO--AVERAGE (db) Figure 10. CCDF W -CDMA IQ Magnitude Clipping, Single -Carrier Test Signal 12 (db) ACPR in 3.84 MHz Integrated BW 3.84 MHz Channel BW +ACPRin3.84MHz Integrated BW f, FREQUENCY (MHz) Figure 11. Single -Carrier W -CDMA Spectrum 8

9 f (MHz) Z in (Ω) V DD =28Vdc,I DQ1(A+B) =80mA,I DQ2A = 260 ma, CW Z load (1) (Ω) P1dB Max Output Power P3dB (dbm) (W) PAE (%) (dbm) (W) PAE (%) j j j j j j (1) Load impedance for optimum P1dB power. Z in = Impedance as measured from input contact to ground. Z load = Impedance as measured from drain contact to ground. Device Under Test Output Load Pull Tuner Z in Z load Figure 12. Carrier Side Load Pull Performance Maximum P1dB Tuning f (MHz) Z in (Ω) V DD =28Vdc,I DQ1(A+B) =80mA,I DQ2A = 260 ma, CW Z load (1) (Ω) P1dB Max Power Added Efficiency P3dB (dbm) (W) PAE (%) (dbm) (W) PAE (%) j j j j j j (1) Load impedance for optimum P1dB efficiency. Z in = Impedance as measured from input contact to ground. Z load = Impedance as measured from drain contact to ground. Device Under Test Output Load Pull Tuner Z in Z load Figure 13. Carrier Side Load Pull Performance Maximum Power Added Efficiency Tuning 9

10 PACKAGE DIMENSIONS 10

11 11

12 12

13 13

14 14

15 15

16 PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS Refer to the following documents, software and tools to aid your design process. Application Notes AN1907: Solder Reflow Attach Method for High Power RF Devices in Over--Molded Plastic Packages AN1955: Thermal Measurement Methodology of RF Power Amplifiers AN1977: Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family AN1987: Quiescent Current Control for the RF Integrated Circuit Device Family AN3789: Clamping of High Power RF Transistors and RFICs in Over--Molded Plastic Packages Engineering Bulletins EB212: Using Data Sheet Impedances for RF LDMOS Devices Software Electromigration MTTF Calculator RF High Power Model.s2p File Development Tools Printed Circuit Boards For Software and Tools, do a Part Number search at and select the Part Number link. Go to the Software & Tools tab on the part s Product Summary page to download the respective tool. The following table summarizes revisions to this document. REVISION HISTORY Revision Date Description 0 May 2012 Initial Release of Data Sheet 16

17 How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including typicals, must be validated for each customer application by customer s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: Freescale, the Freescale logo, AltiVec, C--5, CodeTest, CodeWarrior, ColdFire, C--Ware, Energy Efficient Solutions logo, Kinetis, mobilegt, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of, Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of All other product or service names are the property of their respective owners. E 2012 RF Document DeviceNumber: Data MD7IC2251N Freescale Rev. 0, 5/2012 Semiconductor, Inc. 17