Figure 4. MMG15241H Driving MD7IC2250N Board Layout. Table 1. MMG15241H Driving MD7IC2250N Test Circuit Component Designations and Values

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1 Freescale Semiconductor Technical Data RF Power Reference Design RF Power Amplifier Lineup GaAs E--pHEMT Driving RF LDMOS Amplifier Lineup Characteristics This reference design provides a prepared high-gain amplifier solution, specifically tuned for W--CDMA base--station applications occupying the 21 to frequency band. Typical Single--Carrier W--CDMA Performance Input Signal PAR = 7.5 Probability on CCDF (Refer to page 2 for test conditions.) Frequency G ps PAE (%) Output PAR ACPR (dbc) MD7IC225N Capable of Handling :1 32 Vdc,, 63 Watts CW Output Power (3 db Input Overdrive from Rated P out ) Designed for Digital Predistortion Error Correction Systems Integrated Quiescent Current Temperature Compensation with Enable/Disable Function (1) Available at > Design Support > Reference Designs Rev., 2/212 MMG15241H Driving MD7IC225N W -CDMA 21 -, 4. W AVG., 28 V W -CDMA SMART DEMO REFERENCE DESIGN MMG15241H/MD7IC225N REFERENCE DESIGN The amplifier lineup consists of a GaAs phemt pre--driver and an LDMOS wideband power amplifier in a Class AB configuration. It is tuned for optimal gain, efficiency and linearity with 4. watts average output power. Performance characteristics of the reference design are provided in this document. Contact your local Freescale sales office or authorized Freescale distributor for additional information on evaluation kit availability for hands--on assessment and customization. MD7IC225N V CC V DS1A V DS2A RF INPUT Input Matching MMG15241H Interstage Matching V GS1A V GS2A V GS1B V GS2B Quiescent Current Temperature Compensation Quiescent Current Temperature Compensation Output Matching Circuit RF OUTPUT V DS1B V DS2B Figure 1. Functional Block Diagram 1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to Select Documentation/Application Notes -- AN1977 or AN1987., 212. All rights reserved. MMG15241H Driving MD7IC225N W -CDMA 1

2 AMPLIFIER LINEUP TEST CONDITIONS GaAs Pre--driver Supply Voltage: V CC =5Volts,I CC = 85 ma LDMOS PA Drain Supply Voltage: V DD =28Volts I DQ1A =I DQ1B =4mA,I DQ2A =I DQ2B = 26 ma Output Power: 4. Watts Avg. IQ Magnitude Clipping ACPR measured in 3.84 MHz Channel ±5 MHz Offset Note: Test conditions apply to both 7.5 and 9.9 db Input Signal PAR AMPLIFIER LINEUP ALTERNATE CHARACTERISTICS Typical Single--Carrier W--CDMA Performance Input Signal PAR = 9.9 Probability on CCDF Frequency G ps PAE (%) Output PAR ACPR (dbc) SMART DEMO HARDWARE Figure 2. Performance Optimized Hardware Figure 3. EMI Shield Cover Applied HEATSINKING When operating this fixture it is important that adequate heatsinking is provided for the device. Excessive heating of the device may prevent duplication of the included measurements and/or destruction of the device. 2

3 V CC R1 C23 C16 R5 C18 R3 R7 C5 C13 C1 V DD C3 RF IN1 :GPA+IC C22 C26 C25 Q2 C24 L1 C14 C2 C15 Q1 C9 C7 C11 C21 MD7IC2x5N Rev. 1 AT RF OUT1 : Direct output RF IN2 : IC only C C8 RF OUT2 : With isolator C17 R6 R8 C6 C12 C2 V DD C4 R2 C19 R4 Figure 4. MMG15241H Driving MD7IC225N Board Layout Table 1. MMG15241H Driving MD7IC225N Test Circuit Component Designations and Values Part Description Part Number Manufacturer AT1 Isolator ESI--7SG Hitachi Metals, Ltd. C1, C2, C3, C4 μf Chip Capacitors GRM55DR61H6KA88L Murata C5, C6, C7, C8 5.6 pf Chip Capacitors ATC6F5R6BT25XT ATC C9, C, C26 2. pf Chip Capacitors ATC6F2RBT25XT ATC C11, C14, C22 33 pf Chip Capacitors ATC6F33JT25XT ATC C12, C13 1. μf Chip Capacitors GRM31CR71H5KA12L Murata C15, C2 1.8 pf Chip Capacitors ATC6F1R8BT25XT ATC C16, C17, C18, C μf Chip Capacitors GRM31CR71H475KA12L Murata C pf Chip Capacitor ATC6F1R5BT25XT ATC C23.1 μf Chip Capacitor C63C4J5RAC Kemet C μf Chip Capacitor C85C225J4RAC Kemet C pf Chip Capacitor ATC6F1R1BT25XT ATC L1 15 nh Chip Capacitor HK16815NJ--T Taiyo Yuden Q1 RF LDMOS Wideband IC MD7IC225NR1 Freescale Q2 Broadband GPA MMG15241HT1 Freescale R1, R2, R3, R4 kω, 1/4 W Chip Resistors CRCW126KFKEA Vishay R5, R6, R7, R8 5kΩ, Potentiometer, Surface Mount 3224W E Bourns PCB.2, ε r =3.5 RO435B Rogers 3

4 TYPICAL CHARACTERISTICS 7.5 db Input PAR Test Signal (Single--Carrier W--CDMA, 3GPP Test Model 1, 64 DPCH, PAR = 7.5 Probability on CCDF) G ps, POWER GAIN PAE, POWER ADDED EFFICIENCY (%) Figure 5. Power Gain versus Output Power 9 Figure 6. Power Added Efficiency versus Output Power ACP, ADJACENT CHANNEL POWER (dbc) PAR, PEAK--TO--AVERAGE RATIO Figure 7. Adjacent Channel Power versus Output Power Figure 8. Output Peak -to -Average Ratio (PAR) versus Output Power PROBABILITY (%) Input Signal W--CDMA. ACPR Measured in 3.84 MHz Channel ±5 MHz Offset. Input Signal PAR = 7.5 Probability on CCDF PEAK--TO--AVERAGE Figure 9. CCDF W -CDMA IQ Magnitude Clipping, Single -Carrier Test Signal 7.5 db W -CDMA TEST SIGNAL ACPR in 3.84 MHz Integrated BW 3.84 MHz Channel BW +ACPRin3.84MHz Integrated BW f, FREQUENCY (MHz) Figure. Single -Carrier W -CDMA Spectrum

5 TYPICAL CHARACTERISTICS 9.9 db Input PAR Test Signal (Single--Carrier W--CDMA, 3GPP Test Model 1, 64 DPCH, PAR = 9.9 Probability on CCDF) 47 2 G ps, POWER GAIN ACP, ADJACENT CHANNEL POWER (dbc) PROBABILITY (%) Figure 11. Power Gain versus Output Power Figure 13. Adjacent Channel Power versus Output Power Input Signal W--CDMA. ACPR Measured in 3.84 MHz Channel ±5 MHz Offset. Input Signal PAR = 9.9 Probability on CCDF PEAK--TO--AVERAGE Figure 15. CCDF W -CDMA IQ Magnitude Clipping, Single -Carrier Test Signal PAE, POWER ADDED EFFICIENCY (%) PAR, PEAK--TO--AVERAGE RATIO Figure 12. Power Added Efficiency versus Output Power 9.9 db W -CDMA TEST SIGNAL Figure 14. Output Peak -to -Average Ratio (PAR) versus Output Power --ACPR in 3.84 MHz Integrated BW 3.84 MHz Channel BW +ACPRin3.84MHz Integrated BW f, FREQUENCY (MHz) Figure 16. Single -Carrier W -CDMA Spectrum 5

6 TYPICAL CHARACTERISTICS CW Test Signal GAIN IRL Gain IRL f, FREQUENCY (MHz) Figure 17. Power Gain versus Input Return Loss versus Fequency 5 45 GAIN Gain IRL IRL G ps, POWER GAIN f, FREQUENCY (MHz) Figure 18. Power Gain and Input Return Loss versus Fequency with Smart Demo Shielded Enclosure Closed Figure 19. Gain Compression (AM/AM Conversion) versus Output Power RELATIVE PHASE (DEGREES, RELATIVE TO PHASE AT P out =37dBm) Figure 2. Phase Distortion (AM/PM Conversion) versus Output Power IMD, INTERMODULATION DISTORTION (dbc) V CC =28Vdc f = P out =38W IM3--U IM3--L IM7--L IM5--U IM7--U IM5--L TWO--TONE SPACING (MHz) Figure 21. Intermodulation Distortion Products versus Two -Tone Spacing 6

7 APPENDIX A Power -Up Sequence The Smart Demo board is equipped with four potentiometers which allow adjustment of DC bias to each of the four amplifier stages. Apply bias as follows: 1. Terminate the RF input and output with 5 Ω impedances: no RF signal applied. 2. Dial all four potentiometers for minimum supply current from V DD. 3. Apply 28 Vdc supply across the V DD and GND terminals. 4. Slowly dial--up each potentiometer until the expected portion of I DQ is seen flowing from V DD. The order of adjustment is not important. 5. Bias MMG15241H pre--driver up with +5 V applied to V DD terminal: I DD should be around 85 ma. 6. Apply RF signal and load. Potentiometer Adjusts I DD R5 I DQ1A +4 ma R6 I DQ1B +4 ma R7 I DQ2A +26 ma R8 I DQ2B +26 ma I DD (total) = I DQ1A +I DQ1B +I DQ2A +I DQ2B 6 ma total Power -Down Sequence 1. Remove RF signal from input terminal. 2. Remove V CC and V DD. 7

8 APPENDIX B Tuning Tips Adjusting the value or location of C21 will have significant effect on ACPR, PAE and gain flatness. Adjusting the values or locations of C5 C will have minor effects on ACPR, efficiency and gain. ACPR performance can be optimized further than described in this reference design, but ACPR performance comes at the expense of P1dB. To optimize ACPR performance: -- Remove C9 and C. -- Change C21 to 2.2 pf and place it 3.9 from the PA output toward the load. Adjusting the values or locations of C25 and C26 will have significant effect on IRL. 8

9 APPENDIX C Mounting The Freescale Smart Demo holds the MD7IC225N in--place with a hold--down clamp (1) for quick replacement. Permanent installation will provide superior RF and thermal performance than a socketed fixture. Refer to the following Freescale application notes for details on installation of the LDMOS power amplifier: 1. Clamping of High Power RF Transistors and RFICs in Over--Molded Plastic Packages. (Document Number: AN3789) Application Note, Solder Reflow Attach Method for High Power RF Devices in Over--Molded Plastic Packages. (Document Number: AN197) Application Note, Bolt Down Mounting Method for High Power RF Transistors and RFICs in Over--Molded Plastic Packages. (Document Number: AN3263, Application Note, 26. Technical documentation for Freescale RF Power products, including data sheets and application notes, can be found at: Enter the applicable Document Number into Keyword search for quickest results. 9

10 APPENDIX D Simulation Models Download simulation models of MMG15241H and MD7IC225N from: (click on the Design Support tab)

11 How to Reach Us: Home Page: Web Support: USA/Europe or Locations Not Listed: Technical Information Center, EL516 2 East Elliot Road Tempe, Arizona or Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen Muenchen, Germany (English) (English) (German) (French) Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F , Shimo--Meguro, Meguro--ku, Tokyo Japan or support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 22 China support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center or Fax: LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals, must be validated for each customer application by customer s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescalet and the Freescale logo are trademarks of All other product or service names are the property of their respective owners All rights reserved. Available at > Design Support > Reference Designs RF Rev. Reference, 2/212 Design Data 11