RF LDMOS Wideband Integrated Power Amplifiers

Transcription

1 Technical Data RF LDMOS Wideband Integrated Power Amplifiers The MD7IC2755N wideband integrated circuit is designed with on--chip matching that makes it usable from MHz. This multi--stage structure is rated for 26 to 32 Volt operation and covers all typical cellular base station modulations. Typical Doherty WiMAX Performance: V DD =28Volts,I DQ1A =I DQ1B = 80 ma, I DQ2B = 275 ma, V G2A =1.7Vdc,P out = 10 Watts Avg., f = 2700 MHz, OFDM d, 64 QAM 3 / 4, 4 Bursts, 10 MHz Channel Bandwidth, Input Signal PAR = % Probability on CCDF. Power Gain 25 db Power Added Efficiency 25% Device Output Signal PAR % Probability on CCDF 8.5 MHz Offset --37 dbc in 1 MHz Channel Bandwidth Capable of Handling 10:1 32 Vdc, 2600 MHz, 90 Watts CW Output Power (3 db Input Overdrive from Rated P out ) Stable into a 10:1 VSWR. All Spurs Below mw to 10 Watts CW P out Typical P 1 db Compression Point 30 Watts CW Features Production Tested in a Symmetrical Doherty Configuration 100% PAR Tested for Guaranteed Output Power Capability Characterized with Series Equivalent Large--Signal Impedance Parameters and Common Source S--Parameters On--Chip Matching (50 Ohm Input, DC Blocked) Integrated Quiescent Current Temperature Compensation with Enable/Disable Function (1) Integrated ESD Protection 225 C Capable Plastic Package RoHS Compliant In Tape and Reel. R1 Suffix = 500 Units per 44 mm, 13 inch Reel. Document Number: MD7IC2755N Rev. 3, 9/2010 MD7IC2755NR1 MD7IC2755GNR MHz, 10 W AVG., 28 V WiMAX RF LDMOS WIDEBAND INTEGRATED POWER AMPLIFIERS CASE TO -270 WB -14 PLASTIC MD7IC2755NR1 CASE TO -270 WB -14 GULL PLASTIC MD7IC2755GNR1 V DS1A RF ina V GS1A V GS2A V GS1B V GS2B Quiescent Current Temperature Compensation (1) Quiescent Current Temperature Compensation (1) PEAKING (2) RF out1 /V DS2A CARRIER (2) V DS1A V GS2A 1 2 V GS1A 3 RF ina NC 4 5 NC 6 NC 7 NC 8 RF inb V GS1B 10 V GS2B 11 V DS1B RF out1 /V DS2A RF out2 /V DS2B RF inb V DS1B RF out2 /V DS2B (Top View) Note: Exposed backside of the package is the source terminal for the transistors. Figure 1. Functional Block Diagram Figure 2. Pin Connections 1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to Select Documentation/Application Notes -- AN1977 or AN Peaking and Carrier orientation is determined by the test fixture design., Inc., All rights reserved. 1

2 Table 1. Maximum Ratings Rating Symbol Value Unit Drain--Source Voltage V DS --0.5, +65 Vdc Gate--Source Voltage V GS --0.5, +10 Vdc Operating Voltage V DD 32, +0 Vdc Storage Temperature Range T stg --65 to +150 C Case Operating Temperature T C 150 C Operating Junction Temperature (1,2) T J 225 C Input Power P in 30 dbm Table 2. Thermal Characteristics Final Doherty Application Thermal Resistance, Junction to Case Case Temperature 72 C, P out = 10 W CW, 2600 MHz Stage 1A, 1B, 28 Vdc, I DQ1A =I DQ1B =80mA Stage 2A, 2B, 28 Vdc, I DQ2B = 275 ma, V G2A =1.7Vdc Case Temperature 90 C, P out = 55 W CW, 2600 MHz Stage 1A, 1B, 28 Vdc, I DQ1A =I DQ1B =80mA Stage 2A, 2B, 28 Vdc, I DQ2B = 275 ma, V G2A =1.7Vdc Table 3. ESD Protection Characteristics Human Body Model (per JESD22--A114) Machine Model (per EIA/JESD22--A115) Characteristic Symbol Value (2,3) Unit Test Methodology Charge Device Model (per JESD22--C101) Table 4. Moisture Sensitivity Level R θjc Class 1C (Minimum) A (Minimum) III (Minimum) Test Methodology Rating Package Peak Temperature Unit Per JESD22--A113, IPC/JEDEC J--STD C 1. Continuous use at maximum temperature will affect MTTF. 2. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. 3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to Select Documentation/Application Notes -- AN1955. C/W 2

3 Table 5. Electrical Characteristics (T A =25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Stage 1 Off Characteristics (1) Zero Gate Voltage Drain Leakage Current (V DS =65Vdc,V GS =0Vdc) I DSS 10 μadc Zero Gate Voltage Drain Leakage Current (V DS =28Vdc,V GS =0Vdc) Gate--Source Leakage Current (V GS =1.5Vdc,V DS =0Vdc) Stage 1 On Characteristics Gate Threshold Voltage (1) (V DS =10Vdc,I D =46μAdc) Gate Quiescent Voltage (1) (V DS =28Vdc,I DQ1A =I DQ1B =80mAdc) Fixture Gate Quiescent Voltage (2) (V DD =28Vdc,I DQ1A =I DQ1B = 80 madc, Measured in Functional Test) Stage 2 Off Characteristics (1) Zero Gate Voltage Drain Leakage Current (V DS =65Vdc,V GS =0Vdc) Zero Gate Voltage Drain Leakage Current (V DS =28Vdc,V GS =0Vdc) Gate--Source Leakage Current (V GS =1.5Vdc,V DS =0Vdc) Stage 2 On Characteristics Gate Threshold Voltage (1) (V DS =10Vdc,I D = 185 μadc) Gate Quiescent Voltage (1) (V DS =28Vdc,I DQ2B = 275 madc) Fixture Gate Quiescent Voltage (2) (V DD =28Vdc,I DQ2B = 275 madc, Measured in Functional Test) Drain--Source On--Voltage (1) (V GS =10Vdc,I D =1A) Stage 2 - Dynamic Characteristics (2,3) Output Capacitance (V DS =28Vdc± 30 1 MHz, V in =0Vdc) I DSS 1 μadc I GSS 1 μadc V GS(th) Vdc V GS(Q) 2.7 Vdc V GG(Q) Vdc I DSS 10 μadc I DSS 1 μadc I GSS 1 μadc V GS(th) Vdc V GS(Q) 2.7 Vdc V GG(Q) Vdc V DS(on) Vdc C oss 111 pf Functional Tests (4,5) (In Freescale Doherty Test Fixture, 50 ohm system) V DD =28Vdc,I DQ1A =I DQ1B =80mA,I DQ2B = 275 ma, V G2A =1.7Vdc,P out = 10 W Avg., f = 2700 MHz, WiMAX, OFDM d, 64 QAM 3 / 4, 4 Bursts, 10 MHz Channel Bandwidth, Input Signal PAR = % Probability on CCDF. ACPR measured in 1 MHz Channel ±8.5 MHz Offset. Power Gain G ps db Power Added Efficiency PAE % Output Peak--to--Average 0.01% Probability on CCDF PAR db Adjacent Channel Power Ratio ACPR dbc 1. Side A and Side B are tied together for this measurement. 2. Each side of device measured separately. 3. Part internally matched both on input and output. 4. Measurement made with device in a Symmetrical Doherty configuration. 5. Measurement made with device in straight lead configuration before any lead forming operation is applied. (continued) 3

4 Table 5. Electrical Characteristics (T A =25 C unless otherwise noted) (continued) Characteristic Symbol Min Typ Max Unit Typical Performances (In Freescale Doherty Test Fixture, 50 ohm system) V DD =28Vdc,I DQ1A =I DQ1B =80mA,I DQ2B = 275 ma, V G2A = 1.7 Vdc, MHz Bandwidth P 1 db Compression Point, CW P1dB 30 W IMD 12 W PEP, P out where IMD Third Order Intermodulation 30 dbc (Delta IMD Third Order Intermodulation between Upper and Lower Sidebands > 2 db) VBW Resonance Point (IMD Third Order Intermodulation Inflection Point) IMD sym 70 MHz VBW res 85 MHz Gain Flatness in 200 MHz P out =10WAvg. G F 1.6 db Average Deviation from Linear Phase in 200 MHz out =30WCW Φ 2 Average Group P out = 30 W CW, f = 2600 MHz Delay 2.7 ns Part--to--Part Insertion Phase P out =30WCW, f = 2600 MHz, Six Sigma Window Gain Variation over Temperature (--30 C to+85 C) Output Power Variation over Temperature (--30 C to+85 C) Φ 3.6 G db/ C P1dB 0.03 dbm/ C 4

5 V D1A V D2A V DD L2 C17 V G2A R1 R2 R3 C7 C15 V G1A R4 R5 R6 C3 C5 SIDE A C13 RF INPUT R13 Z in COUPLER 1 C1 Z1 Z2 C C6 DUT Quiescent Current Temperature Compensation Quiescent Current Temperature Compensation SIDE B Z3 Z4 C10 C9 C11 Z5 Z6 C12 Z7 C21 Z9 Z10 C22 Z8 C14 C23 Z11 C19 Z12 C20 C24 Z14 Z13 Z out RF OUTPUT V G1B R7 R8 R9 C4 C8 C16 V G2B R10 R11 R12 L1 C18 V D1B Z1, Z x Microstrip Z3, Z x Microstrip Z5, Z x Microstrip Z7, Z x Microstrip Z9, Z x Microstrip Z11, Z x Microstrip V D2B Z x Microstrip Z x Microstrip Z in x Microstrip Z out x Microstrip PCB Rogers RO4350B, 0.020, ε r =3.5 Figure 3. MD7IC2755NR1(GNR1) Test Circuit Schematic Table 6. MD7IC2755NR1(GNR1) Test Circuit Component Designations and Values Part Description Part Number Manufacturer C1, C2, C3, C4, C5, C6, C13, 6.8 pf Chip Capacitors ATC600S6R8BT250XT ATC C14, C19, C20 C7, C8, C17, C18 10 μf Chip Capacitors GRM55DR61H106KA88 Murata C15, C pf Chip Capacitors GRM1885C2A152JA01 Murata C9, C10, C11, C12, C21, C22, 0.5 pf Chip Capacitors ATC600S0R5BT250XT ATC C23, C24 Coupler Hybrid 3 db Coupler GSC356 Soshin L1, L2 Jumper Wires R4, R5, R7, R8 75 Ω, 1/8 W Chip Resistors RK73B2ATTD750G KOA Speer R1, R Ω, 1/8 W Chip Resistors RK73B2ATTD301G KOA Speer R2, R11 2kΩ, 1/8 W Chip Resistors RK73B2ATTD202G KOA Speer R3, R6, R9, R12 12 kω, 1/8 W Chip Resistors RK73B2ATTD123G KOA Speer R13 51 Ω, 1/8 W Chip Resistor RK73B2ATTD510G KOA Speer 5

6 V D1A MD7IC2755N Rev. 2 L2 V D2A V G2A R1 R2 R3 C7 C9 C13 C11 C15 V G1A R4 R5 R6 C3 C5 C17 COUPLER 1 R13 C1 P C21 C23 C19 C2 C C24 C22 C20 V G1B R7 R8 R9 C4 C6 C18 V G2B R10 R11 R12 C8 C10 C12 C16 C14 V D1B L1 V D2B Figure 4. MD7IC2755NR1(GNR1) Test Circuit Component Layout Single--ended λ λ 4 4 Quadrature combined λ 4 Doherty λ 2 λ 2 Push--pull Figure 5. Possible Circuit Topologies 6

7 TYPICAL CHARACTERISTICS G ps, POWER GAIN (db) V DD =28Vdc P out =10W(Avg.) I DQ1A =I DQ1B =80mA,I DQ2B = 275 ma V G2A = 1.7 Vdc, OFDM d, 64 QAM 3 / 4 4 Bursts, 10 MHz Channel Bandwidth, Input Signal PAR = % Probability on CCDF PARC f, FREQUENCY (MHz) ACPR Figure 6. WiMAX Broadband P out = 10 Watts Avg. G ps PAE IRL PAE, POWER ADDED EFFICIENCY (%) ACPR (dbc) IRL, INPUT RETURN LOSS (db) PARC (db) 32 I DQ1A =I DQ1B = 120 ma 32 I DQ2B = 413 ma G ps, POWER GAIN (db) ma 80 ma 60 ma 40 ma 1 V DD =28Vdc I DQ2B = 275 ma V G2A =1.7Vdc f = 2600 MHz P out, OUTPUT POWER (WATTS) CW Figure 7. Power Gain versus Output Power Stage 1, Class AB G ps, POWER GAIN (db) ma 275 ma 143 ma 95 ma 1 V DD =28Vdc I DQ1A =I DQ1B =80mA V G2A =1.7Vdc f = 2600 MHz P out, OUTPUT POWER (WATTS) CW Figure 8. Power Gain versus Output Power Stage 2, Class AB V V G ps, POWER GAIN (db) V G2A =1.7Vdc V 1.6 V V DD =28Vdc I DQ1A =I DQ1B =80mA I DQ2B = 275 ma f = 2600 MHz P out, OUTPUT POWER (WATTS) CW Figure 9. Power Gain versus Output Power Stage 2, Class C 7

8 TYPICAL CHARACTERISTICS IMD, INTERMODULATION DISTORTION (dbc) V DD =28Vdc,P out = 12 W (PEP), I DQ1A =I DQ1B =80mA I DQ2B = 275 ma, V G2A = 1.7 Vdc, Two--Tone Measurements (f1 + f2)/2 = Center Frequency of 2600 MHz IM7--L IM5--L IM5--U IM7--U IM3--U IM3--L 10 TWO--TONE SPACING (MHz) Figure 10. Intermodulation Distortion Products versus Two -Tone Spacing 100 G ps, POWER GAIN (db) OUTPUT COMPRESSION AT 0.01% PROBABILITY ON CCDF (db) G ps PARC --1 db = 5.65 W V DD =28Vdc,I DQ1A =I DQ1B =80mA I DQ2B = 275 ma, V G2A =1.7Vdc PAE --2dB=11.92W --3 db = W f = 2600 MHz, OFDM d QAM 3 / 4, 4 Bursts, 10 MHz Channel Bandwidth, Input Signal PAR = % 16 Probability on CCDF P out, OUTPUT POWER (WATTS) ACPR Figure 11. Output Peak -to -Average Ratio Compression (PARC) versus Output Power PAE, POWER ADDED EFFICIENCY (%) ACPR (dbc) PAE, POWER ADDED EFFICIENCY (%), G ps, POWER GAIN (db) V DD =28Vdc,I DQ1A =I DQ1B =80mA 25_C 45 I --30_C DQ2B = 275 ma, V G2A = 1.7 Vdc, f = 2600 MHz OFDM d, 64 QAM 3 / 4,4Bursts T C =--30_C 25_C _C G 85_C --35 ps 25_C _C PAE MHz Channel Bandwidth --50 ACPR Input Signal PAR = % 5 Probability on CCDF P out, OUTPUT POWER (WATTS) AVG. WiMAX Figure 12. WiMAX, ACPR, Power Gain and Power Added Efficiency versus Output Power ACPR (dbc) 8

9 TYPICAL CHARACTERISTICS Gain --13 GAIN (db) IRL f, FREQUENCY (MHz) Figure 13. Broadband Frequency Response V DD =28Vdc P out =19dBm I DQ1A =I DQ1B =80mA --22 I DQ2B = 275 ma V G2A =1.7Vdc IRL (db) Stage 2A MTTF (HOURS) Stage 2B Stage 1A 10 6 Stage 1B T J, JUNCTION TEMPERATURE ( C) This above graph displays calculated MTTF in hours when the device is operated at V DD =28Vdc,P out = 10 W Avg., and PAE = 25%. MTTF calculator available at Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. Figure 14. MTTF versus Junction Temperature 250 9

10 WIMAX TEST SIGNAL PROBABILITY (%) OFDM d, 64 QAM 3 / 4,4Bursts 10 MHz Channel Bandwidth, Input Signal PAR = % Probability on CCDF Input Signal PEAK--TO--AVERAGE (db) Figure 15. OFDM d Test Signal 10 (db) ACPR in 1 MHz Integrated BW MHz Channel BW 0 ACPR in 1 MHz Integrated BW f, FREQUENCY (MHz) Figure 16. WiMAX Spectrum Mask Specifications 10

11 Z o =50Ω Z o =10Ω Z in -- 1B f = 2700 MHz f = 2700 MHz f = 2500 MHz Z load -- 2B f = 2500 MHz SIDE 1B Measured Data V DD =28Vdc,I DQ1A =I DQ1B =80mA,I DQ2B = 275 ma, V G2A =1.7Vdc,P out =10WAvg. f MHz Z in Ω j j j j j j j j j23.55 Z in = Device input impedance as measured from gate to ground. Z load = Test circuit impedance as measured from drain to ground. SIDE 2B Simulated Data V DD =28Vdc,I DQ1A =I DQ1B =80mA,I DQ2B = 275 ma, V G2A =1.7Vdc,P out =10WAvg. f MHz Z load Ω j j j j j j j j j0.57 Z in = Device input impedance as measured rom gate to ground. Z load = Test circuit impedance as measured from drain to ground. Device Under Test Output Matching Network Device Under Test Output Matching Network Z in Z load Figure 17. Series Equivalent Input and Load Impedance 11

12 ALTERNATIVE PEAK TUNE LOAD PULL CHARACTERISTICS CLASS AB P3dB = dbm (36 W) Ideal P3dB = dbm (34 W) Ideal P out, OUTPUT POWER (dbm) P1dB = dbm (30 W) 9 Actual V DD =28Vdc,I DQ1B =80mA I DQ2B = 275 ma, Pulsed CW, 10 μsec(on) 10% Duty Cycle, f = 2500 MHz P out, OUTPUT POWER (dbm) P1dB = dbm (27 W) Actual V DD =28Vdc,I DQ1B =80mA I DQ2B = 275 ma, Pulsed CW, 10 μsec(on) 10% Duty Cycle, f = 2700 MHz P in, INPUT POWER (dbm) P in, INPUT POWER (dbm) NOTE: Load Pull Test Fixture Tuned for Peak P1dB Output 28 V NOTE: Load Pull Test Fixture Tuned for Peak P1dB Output 28 V Test Impedances per Compression Level Test Impedances per Compression Level Z source Ω Z load Ω Z source Ω Z load Ω P1dB j j3.44 P1dB j j3.66 Figure 18. Pulsed CW Output Power versus Input MHz Figure 19. Pulsed CW Output Power versus Input MHz NOTE: Measurement made on the Class AB, carrier side of the device. 12

13 Table 7. Class AB Common Source S -Parameters (V DD =28V,I DQ1B =80mA,I DQ2B = 275 ma, T A =25 C, 50 Ohm System) Measurement made on the Class AB, carrier side of the device. f MHz S 11 S 21 S 12 S 22 S 11 φ S 21 φ S 12 φ S 22 φ (continued) 13

14 Table 7. Class AB Common Source S -Parameters (V DD =28V,I DQ1B =80mA,I DQ2B = 275 ma, T A =25 C, 50 Ohm System) Measurement made on the Class AB, carrier side of the device. (continued) f MHz S 11 S 21 S 12 S 22 S 11 φ S 21 φ S 12 φ S 22 φ

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21 PRODUCT DOCUMENTATION, TOOLS AND SOFTWARE Refer to the following documents to aid your design process. Application Notes AN1907: Solder Reflow Attach Method for High Power RF Devices in Plastic Packages AN1955: Thermal Measurement Methodology of RF Power Amplifiers AN1977: Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family AN1987: Quiescent Current Control for the RF Integrated Circuit Device Family AN3263: Bolt Down Mounting Method for High Power RF Transistors and RFICs in Over--Molded Plastic Packages AN3789: Clamping of High Power RF Transistors and RFICs in Over--Molded Plastic Packages Engineering Bulletins EB212: Using Data Sheet Impedances for RF LDMOS Devices Software Electromigration MTTF Calculator For Software and Tools, do a Part Number search at and select the Part Number link. Go to the Software & Tools tab on the part s Product Summary page to download the respective tool. The following table summarizes revisions to this document. REVISION HISTORY Revision Date Description 0 Jan Initial Release of Data Sheet 1 July 2009 Test Conditions clarified for Fig. 18, Pulsed CW Output Power versus Input MHz, and Fig. 19, Pulsed CW Output Power versus Input MHz, p. 12 Added Electromigration MTTF Calculator availability to Product Software, p Sept For P out = 10 W CW, changed Stage 1A, Stage 1B thermal resistance values from 4.0 (Stage 1A), 5.0 (Stage 1B) to 2.6 C/W and Stage 2A, Stage 2B thermal resistance values from 0.9 (Stage 2A), 2.1 (Stage 2B) to 1.8 in Thermal Characteristics table. For P out = 55 W CW, changed Stage 1A, Stage 1B thermal resistance values from 4.6 (Stage 1A), 4.2 (Stage 1B) to 2.3 C/W and Stage 2A, Stage 2B thermal resistance values from 1.2 (Stage 2A), 2.0 (Stage 2B) to 1.1 in Thermal Characteristics table. Thermal value now reflects the use of the combined dissipated power from the carrier amplifier and peaking amplifier, p. 2. Fig. 4, Test Circuit Component Layout, added labels to distinguish Carrier and Peaking side of amplifier, p. 6 3 Sept Fig. 3, Test Circuit Schematic, corrected labeling of C9 and C pf Chip Capacitors, p. 5 21

22 How to Reach Us: Home Page: Web Support: USA/Europe or Locations Not Listed:, Inc. Technical Information Center, EL East Elliot Road Tempe, Arizona or Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen Muenchen, Germany (English) (English) (German) (French) Japan: Japan Ltd. Headquarters ARCO Tower 15F , Shimo--Meguro, Meguro--ku, Tokyo Japan or support.japan@freescale.com Asia/Pacific: China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing China support.asia@freescale.com For Literature Requests Only: Literature Distribution Center or Fax: LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. reserves the right to make changes without further notice to any products herein. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters that may be provided in data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals, must be validated for each customer application by customer s technical experts. does not convey any license under its patent rights nor the rights of others. products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. Should Buyer purchase or use products for any such unintended or unauthorized application, Buyer shall indemnify and hold and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescalet and the Freescale logo are trademarks of, Inc. All other product or service names are the property of their respective owners., Inc All rights reserved. Document Number: MD7IC2755N 22 Rev. 3, 9/2010