Single Stage Amplifier

Transcription

1 CHAPTE 3 Sle Stae Aplifier Analo IC Analysis and esin 3- Chih-Chen Hsieh

2 Outle. Coon-Source Aplifier. Coon-Source Ap with Source eeneration 3. Coon-ra Aplifier 4. Coon-Gate Aplifier 5. Cascode Aplifier Analo IC Analysis and esin 3- Chih-Chen Hsieh

3 ision An iportant part of a desiner s job is to use proper approxiations so as to create a siple ental picture of a coplicated circuit. The tuition thus aed akes it possible to forulate the behavior of ost circuits by spection rather than by lenthy calculations Analo IC Analysis and esin 3-3 Chih-Chen Hsieh

4 Basic Concepts The put-put characteristic of an aplifier is enerally a nonlear function y n ( t) 0 x( t) x ( t) nx ( t) x x x For a sufficiently narrow rane of x y ( t ) x ( t ), : operation pot, :sall sinal a 0 0 As x(t) creases anitude, hiher order ters anifest theselves, lead to nonlear distortion. Input-put characteristic of a nonlear syste Analo IC Analysis and esin 3- Chih-Chen Hsieh 4

5 Analo esin Octaon Analo desin octaon Analo IC Analysis and esin 3- Chih-Chen Hsieh 5

6 Coon Source Stae (I) M off M the saturation reion To fd TH M the triode reion TH et TH TH nc nc ox Analo IC Analysis and esin 3- Chih-Chen Hsieh W 6 ox W TH TH

7 Coon Source Aplifier (II) Sce the transconductance drops the triode reion, (the r o also becoes saller), we usually ensure that TH As A v Sce itself varies with the put sinal, the a of the circuit chanes substantially if the sinal sw is lare. Analo IC Analysis and esin 3- Chih-Chen Hsieh 7 n C nc ox W ox W TH TH

8 Coon Source Aplifier (III) To take channel lenth odulation effect to account : We have As I W ncox TH Analo IC Analysis and esin 3- Chih-Chen Hsieh 8 W ox TH nc C n ox W C TH A v I n ox A O I Av ro ro ro r v W A v TH I

9 esin Trade-off To axiize a A v W ncox I I C n ox W I Increase W/ reater device capacitance ( Ga BW ) Hiher saller voltae sw ( Ga oltae sw ) educe I while is constant larer C tie constant at the put node ( Ga BW ) Analo IC Analysis and esin 3- Chih-Chen Hsieh 9

10 iode Connected oad In any CMOS technoloies, it is difficult to fabricate resistors with tihtly controlled values or a reasonable size. eplace with a MOS transistor. iode connected : ate and dra shorted S = GS > GS TH the transistor always saturation reion. Analo IC Analysis and esin 3- Chih-Chen Hsieh 0 ( I X X b ) X r b b X O r r O O I X b

11 Analo IC Analysis and esin 3- Chih-Chen Hsieh CS Stae + iode Connected oad If the variation of η with the put voltae is nelected, the a is dependent of the bias current and voltaes (so lon as M stays saturation). Input-put characteristics of a CS stae with diode connected load. Operated at pot A. ) / ( ) / ( ) / ( ) / ( W W I W C I W C A A ox n ox n v b b v

12 CS Stae + iode-connected PMOS The circuit is free fro body effect. A v n( W ( W p / ) / ) A v GS TH GS TH W n Exaple : GS TH p W GS If A v = 0, GS - TH = 00, GS - TH =, TH = 0.7 GS =.7 oax = GS Trade-off between a and put sw To take the effect of channel lenth odulation effect to account TH A v ro ro Analo IC Analysis and esin 3- Chih-Chen Hsieh

13 CS Stae + Current Source oad For resistor or diode connected load, creas the load resistance liits the put voltae sw CS stae with current source load. A v r r O O S, GS TH The put bias voltae of the circuit needs a feedback loop to force to a known value. If A v W (for constant I) C load Ga- Bandwidth Trade-off Keep W constant, S,sw Analo IC Analysis and esin 3- Chih-Chen Hsieh 3 / r / O I

14 CS Stae + Triode oad The ate of M is biased at a sufficiently low level, ensur the load is deep triode reion for all put voltae sws. b on TH C p ox ( W / ) ( b THP TH ) b Consue less voltae headroo than diode connected devices. rawback on depends on μ p C ox, b, and THP, which vary with process and Tep. ifficult to use. Analo IC Analysis and esin 3- Chih-Chen Hsieh 4

15 Outle. Coon-Source Aplifier. Coon-Source Ap with Source eeneration 3. Coon-ra Aplifier 4. Coon-Gate Aplifier 5. Cascode Aplifier Analo IC Analysis and esin 3-5 Chih-Chen Hsieh

16 CS Stae + Source eeneration (I) Coon source Ga I Iprove the learity of the a aplifier Hiher learity, ower a G A v I G : equivalent transconductance of circuit : transconductance of MOS I f et I f ( GS ) G GS For I Analo IC Analysis and esin 3- Chih-Chen Hsieh 6 I f G S SG G GS S A G For / G / S / S ear! GS GS GS S S v S S I

17 CS Stae + Source eeneration (II) To take the body effect and channel lenth odulation effect to account X I bx ( IS ) b ( IS ) r G I ( ) / r b S S O O I r O S Coon source ap Coon source ap + source deeneration Analo IC Analysis and esin 3- Chih-Chen Hsieh 7

18 Forulate Ga by Inspection Manitude of a as the resistance seen at the dra node divided by the total resistance the source path A v / S A v / / Analo IC Analysis and esin 3- Chih-Chen Hsieh 8

19 CS Stae + Source eeneration (III) of CS + Source deeneration By Inspection ( ) ( ) ( ) r r r b S O S b O S O r b S O S b S S, I [ ] S r r O b I X S r [ I ( ) I ] I O X b S X X S X ( ) r I S b S O S b S O S Analo IC Analysis and esin 3- Chih-Chen Hsieh 9

20 CS Stae + Source eeneration (I) oltae a with r o & b I ( ) S S ro b bs b S S Ir ro S ro b ro O ro r ( ) r S O b S O Analo IC Analysis and esin 3- Chih-Chen Hsieh 0 ( ) r S ro O b S ro r ( ) r r ( ) r S O b S O S O b S O G G { r ( ) r } eff O eff S O b S O S

21 CS Stae + Source eeneration () I 0 = constant, I( S ) = constant, sall-sinal voltae drop across S = 0 ro Av { S [ ( b ) S ] ro } [ ( ) ] r S b S O r O trsic a, dependent of S Analo IC Analysis and esin 3- Chih-Chen Hsieh

22 Outle. Coon-Source Aplifier. Coon-Source Ap with Source eeneration 3. Coon-ra Aplifier 4. Coon-Gate Aplifier 5. Cascode Aplifier Analo IC Analysis and esin 3- Chih-Chen Hsieh

23 C Stae: Source Follower (I) The source follower can operate as a voltae buffer Hih put ipedance, low put ipedance. Ga, but not equal to even with S = fity. W ox TH nc ncox W ncox W ( ) TH S TH S S A v W ncox S ( b ) S TH Analo IC Analysis and esin 3- Chih-Chen Hsieh 3

24 C: Sall-sinal equivalent circuit Calculate the voltae a by sall-sinal equivalent circuit of source follower with body effect,, / bs b S A v S ( ) b S I Av b Analo IC Analysis and esin 3- Chih-Chen Hsieh 4

25 of Source Follower Body effect decrease of source follower b I X X b X 0 ess-than-unity voltae a of source follower with body effect S A v / b / / b b Analo IC Analysis and esin 3- Chih-Chen Hsieh 5

26 Source Follower with r o Source follower with fite channel-lenth odulation A v ro r b ro ro b O Analo IC Analysis and esin 3- Chih-Chen Hsieh 6

27 Source Follower rawback oltae headroo consuption due to level shift. Nonlearity Nonlear dependence of TH upon the source potential. r O of the transistor also chanes substantially with S. PMOS source follower with no body effect Hiher put ipedance us PMOS source follower. Analo IC Analysis and esin 3- Chih-Chen Hsieh 7

28 Outle. Coon-Source Aplifier. Coon-Source Ap with Source eeneration 3. Coon-ra Aplifier 4. Coon-Gate Aplifier 5. Cascode Aplifier Analo IC Analysis and esin 3-8 Chih-Chen Hsieh

29 CG: Coon-Gate Stae If M is saturated, the can be expressed as C C n n ox nc ox For W W ox W b TH TH b TH TH Body effect creases the equivalent of the stae. Body effect deceases the put ipedance of CG. Z TH SB Analo IC Analysis and esin 3- Chih-Chen Hsieh 9 b TH ( ) b ( )

30 CG Stae- Input Ipedance By tak to account both the put ipedance of the transistor r o, fd the put ipedance Z : I X O I X ( b X X r ) For = 0, sae as source follower Z For =, Z = Z I X X ( r O b ) r O ( X ro ro I ( ) r / r X b O b O b b ) r O b Analo IC Analysis and esin 3- Chih-Chen Hsieh 30

31 CG Stae- Output Ipedance The put ipedance is siilar to that of a coon source a stae with source deeneration. S is the ipedance of sinal source. {[ ( ) r ] r } b O S O Analo IC Analysis and esin 3- Chih-Chen Hsieh 3

32 CG Stae- oltae a oltae a is siilar to CS + Source deeneration, it s slihtly hiher due to body effect S 0 r O b S ro ( b ) S S ( ) r ( ) r [ r ( ) r ] r ( ) r r ( ) r r ( ) r b O b O O b O S S O b O S S O b O S S O b O S S ( b) ro r ( ) r O b O S S r [ r ( ) r ] r ( ) r r ( ) r O O b O S S CS S O b O S S O b O S S Analo IC Analysis and esin 3- Chih-Chen Hsieh 3

33 Outle. Coon-Source Aplifier. Coon-Source Ap with Source eeneration 3. Coon-ra Aplifier 4. Coon-Gate Aplifier 5. Cascode Aplifier Analo IC Analysis and esin 3-33 Chih-Chen Hsieh

34 CAS: Cascode Stae (I) Cascade of a CS stae and a CG stae a hih put ipedance. () S( sat) S ( sat) A ( r ) v o With consideration of r o, The voltae a is dependent of the transconductance and body effect of M. Analo IC Analysis and esin 3- Chih-Chen Hsieh 34

35 CAS: Cascode Stae (II) If both M and M operate saturation. G [ ( ) r ] r r b O O O ( ) r r b O O A ( ) r r v b O O The axiu voltae a is rouhly equal to the square of the trsic a of the transistors Analo IC Analysis and esin 3- Chih-Chen Hsieh 35

36 NMOS CAS Ap + PMOS CAS oad Cascode as a constant current source with hih put ipedance The axiu put sw is equal to, sw S S S3 S4 { b ro r O ro } v { ( ) r r r } A 3 b3 O3 O4 O3 r r ( 3rO 3r 4) O O O Analo IC Analysis and esin 3- Chih-Chen Hsieh 36

37 Folded Cascode A PMOS-NMOS cobation. The total bias current this case ust be hiher to achieve coparable perforance. Analo IC Analysis and esin 3- Chih-Chen Hsieh 37

38 of Folded-Cascode r ( r r ) r b O O O3 O Analo IC Analysis and esin 3- Chih-Chen Hsieh 38

39 esiner s Intuition Siulation is essential because the behavior of short-channel MOSFET can t be predicted accurately by hand calculations. on t avoids a siple and tuitive analysis of the circuit and skip the task of a side, you can t terpret the siulate results telliently. on t let the coputer thk for you! Analo IC Analysis and esin 3- Chih-Chen Hsieh 39