Lecture 34: MOSFET Common Gate Amplifier.

Transcription

1 Whites, EE 320 Lecture 34 Page 1 of 10 Lecture 34: MOSFET Coon Gate Aplifier. We ll continue our discussion of discrete MOSFET aplifiers we began with the coon source aplifier in Lectures 31 and 32. Here we ll cover the coon gate aplifier, which is shown in Fig It has a grounded gate terinal, a signal input at the source terinal, and the output taken at the drain. We ve augented Fig below in Fig. 1 with additional biasing circuitry and a load resistance to give a ore coplete exaple of the CG aplifier: V DD R D C C2 v o R L R sig i i C C1 i o v sig + - I R in -V SS (Fig. 1) 2017 Keith W. Whites

2 Whites, EE 320 Lecture 34 Page 2 of 10 Sall-Signal Aplifier Characteristics As we ve done with previous aplifiers in this course, we ll calculate the following sall-signal quantities for this MOSFET coon gate aplifier: R in, A v, A vo, G v, G i, A is, and R out. To begin, we construct the sall-signal equivalent circuit: (Fig. 2) (Sedra and Sith, 5 th ed.) The T odel was used since we ignored r o while R sig appears in series with 1/g. Input resistance, R in. Because the gate is grounded, we can see directly fro this sall-signal equivalent circuit that 1 Rin (7.116),(1) g

3 Whites, EE 320 Lecture 34 Page 3 of 10 Actually, this result ay not be that readily apparent to you since while the gate is grounded, the current in the gate is zero ( ig 0). To verify this result in (1), we can apply a voltage source v x at the source terinal and calculate the ratio of this voltage to the current directed into the source terinal, which we ll define as i x : v o i g v gs At the input to this circuit v x 0 ix 1/ g i x g v x This current i x doesn t flow through the gate terinal! Instead, i x flows entirely through the dependent source, then to ground. Indeed, we see that i g v i x gs

4 Whites, EE 320 Lecture 34 Page 4 of 10 Tricky! In any event, the input resistance in (1) has been verified since v i 1 g. x x In the case that r o is included in the analysis, the text shows that ro RL 1 RL Rin (8.53),(8.54) g r g g r 1 o o g r 1 o Partial sall-signal voltage gains, A v and A vo. At the output side of the sall-signal circuit v g v R R (2) o gs D L At the input, we can see that because the gate is grounded v v (3) i gs Substituting (3) into (2), gives the partial sall-signal AC voltage gain to be vo Av grd RL (4) v i In the case of an open circuit load ( RL ), the sall-signal voltage gain becoes A A g R (7.117),(5) vo v R D L Overall sall-signal voltage gain, G v. Using voltage division at the input to the sall-signal equivalent circuit Rin vi vsig (6) R R in sig

5 Whites, EE 320 Lecture 34 Page 5 of 10 Substituting this into vo vi vo vi Gv vsig vsig v i vsig Av (7) gives the overall sall-signal voltage gain of this coon gate aplifier to be vo Rin Gv grd RL (8) v R R A sig in sig More specifically, using (1) in this expression grd RL Gv 1 g R v sig (7.120),(9) Overall sall-signal current gain, G i. Using current division at the output in the sall-signal circuit above RD io gvgs (10) RD RL Because ig 0, then at the input we see that ii gvgs (11) Substituting (11) into (10) gives the overall sall-signal AC current gain to be io RD Gi (12) i R R i D L Short-circuit sall-signal current gain, A is. The short circuit sall-signal AC current gain can be easily deterined fro (12) with RL 0 as

6 Whites, EE 320 Lecture 34 Page 6 of 10 A G 1 (13) 0 is i R L Output resistance, R out. Fro the sall-signal circuit above with vsig 0 we find that i 0 since the gate is grounded. Consequently, R R (7.118),(14) out D Suary In suary, we find for the CG sall-signal aplifier: o A non-inverting aplifier. o Moderate input resistance [see (1)]. o Moderately large sall-signal voltage gain [see (9)], but saller than CS aplifier. o Sall-signal current gain less than one [see (12)]. o Potentially large output resistance (dependent on R D ) [see (14)]. Siilar to the BJT CB aplifier we discussed in Lecture 20, the CG aplifier finds use as a current buffer aplifier. It has the relatively sall input resistance, relatively large output resistance, and G i less than (and potentially near) one characteristics of such aplifiers. (Does this aplifier provide any power gain for a signal?)

7 Whites, EE 320 Lecture 34 Page 7 of 10 Exaple N34.1 Use the DC biasing circuit of Fig. 3 to design a coon gate aplifier. Find R in, R out, A vo, A v, G v, and G i for RL 15 k and Rsig 50. What will the overall voltage gain becoe for Rsig 1 k? 10 k? 100 k? The DC analysis results are shown in Fig. 3: (Fig. 3) (Sedra and Sith, 5 th ed.) Using (7.42) g 2I D S V 1 OV Based on this DC biasing, the corresponding coon gate aplifier circuit is:

8 Whites, EE 320 Lecture 34 Page 8 of 10 v O The sall-signal equivalent circuit for this aplifier is: v o g v gs The 4.7-M resistor functions to force the gate to ground potential. But since ig 0, it will have no other ipact on the circuit.

9 Whites, EE 320 Lecture 34 Page 9 of Fro (1), Rin 1 k. 3 g 10 Fro (14), Rout R D 15 k. Fro (5), A g R V vo D 3 3 V 10 15k 15k 7.5 V Fro (4), A g R R v D L 3 V Fro (9), G v g R R A D L v 3 grsig grsig V 7.14 V 4 (15) Fro (12), G RD 15 1 A i R R A D L What is the overall voltage gain when: o Rsig 1 k? Fro (15), Av 7.5 V Gv gRsig V 7.5 V o Rsig 10 k? Gv V

10 Whites, EE 320 Lecture 34 Page 10 of V o Rsig 100 k? Gv V We see fro these calculations that the overall voltage gain decreases substantially as R sig increases. Can you explain what is physically happening to cause this to occur?