Differential Amplifier with Active Load

Transcription

1 EEEB73 Electronics nalysis & Desin (7) Differential plifier with ctive Loa Learnin Outcoe ble to: Describe active loas. Desin a iff-ap with an active loa to yiel a specifie ifferential-oe voltae ain. Reference: Neaen, Chapter 7.0) ctive Loas ctive loas are essentially transistor current sources use in place of the resistive loas in the iff-ap circuits to increase ifferential-oe ain. BJTs {MOSFETs} in the active loa circuit are biase at -point in forwar-active {saturation} oe. Diff-pair inuces a chane in C { D }, which in turn, prouces a chane in V EC {V SD }. Refer to Fiure.7 for BJT. 7.0) ctive Loas (Cont) Fiure.7: Current-voltae characteristics of active loa evice usin BJT. V EC {V SD } is proportional to r o (sall-sinal output resistance) of the transistor. Value of r o is uch larer than resistive loas, so the sall-sinal voltae ain will be larer with the active loa. 5.) Basic BJT Differential Pair Fiure. shows the basic BJT ifferentialpair confiuration usin npn transistors. 7.) BJT Diff-p with ctive Loa Fiure.8 shows a iff-ap with active loa. Fiure.: Basic BJT ifferential-pair usin npn transistors. Fiure.8: BJT iffap with active loa. Fiure. Lecturer: Dr Jaaluin Bin Oar 7-

2 EEEB73 Electronics nalysis & Desin 7.) BJT Diff-p with ctive Loa (Cont) Fiure.8: BJT iffap with active loa. an are iff pair biase with a constant current, an 3 an for the loa circuit. Fro the collectors of an, obtain a one-sie output v O. 7.) BJT Diff-p with ctive Loa (Cont) DEL CSE: ll s are atche: v B v B v CM splits evenly between an Nelectin base currents: 3 [throuh current-source circuit] 3 / with no loa connecte at output. CTUL CSE: Base currents are non-zero. secon aplifier stae is connecte at the iff-ap output. 7.) BJT Diff-p with ctive Loa (Cont) Fiure.9 shows a iff-ap with an active loa, corresponin to a 3-transistor current source, as well as a secon aplifyin stae (ain stae). Fiure.9: BJT iff ap with 3-transistor active loa an secon stae ain. 7.) BJT Diff-p with ctive Loa (Cont) Fiure.9: BJT iff ap with 3- transistor active loa an secon stae ain. For siplicity, assue all s current ain () are equal. Current O is the c bias current fro the ain stae. ssuin all s are atche an v B v B v CM, current splits evenly an To ensure that an are biase in forwar-active oe, c currents ust be balance, or 3 7.) BJT Diff-p with ctive Loa (Cont) Fro Fiure.9 E5 E5 3 Then B5 (.9) β β ( β ) 3 (.93) β β ( β ) f base currents an O are sall, then 3 B3 B Therefore, B5 (.96) β 7.) BJT Diff-p with ctive Loa (Cont) For the circuit to be balance, i.e. for an 3, ust have O B5 ( ) β β (.97) Equation (.97) iplies that n aplifyin stae ust be esine an biase such that the irection of the c bias current is as shown in Fiure.9 an its value is equal to the result of Equation (.97). Lecturer: Dr Jaaluin Bin Oar 7-

3 EEEB73 Electronics nalysis & Desin 7.) Sall-Sinal nalysis of BJT ctive Loa Fiure.30 shows a ifferential aplifier with a 3- transistor active loa circuit. 7.) Sall-Sinal nalysis of BJT ctive Loa (Cont) The resistance R L represents sall-sinal input resistance of the ain stae. pure iff-oe input voltae is applie as inicate. Fiure.30: BJT iff-aplifier with 3-transistor active loa, showin the sinal currents. Fiure.30: BJT iff ap with 3-transistor active loa, showin the sinal currents. Sinal voltae at base of prouces a sinal collector current i ( v ) / where is transconuctance for both an 7.) Sall-Sinal nalysis of BJT ctive Loa (Cont) ssue the base currents are neliible, a sinal current i 3 i is inuce in 3, an the current irror prouces a sinal current i equal to i 3. 7.) Sall-Sinal nalysis of BJT ctive Loa (Cont) The two sinal currents transistors are biase at the sae quiescent current, i an i, a to prouce a sinal current in the loa resistance R L. Sinal voltae at the base of prouces a sinal collector current i ( v ) /, with irection shown. The iscussion is a first-orer evaluation of circuit operation know the inuce currents in an To ore accurately eterine the output voltae, nee to consier equivalent sall-sinal collector-eitter output circuit of the transistors. 7.) Sall-Sinal nalysis of BJT ctive Loa (Cont) Fiure.3(a) shows the sall-sinal equivalent circuit at collector noes of an. The circuit can be rearrane to cobine sinal rouns at a coon point, as in Fiure.3(b). Fiure.3: (a) Sall-sinal equivalent circuit BJT iff ap with active loa an (b) rearraneent of sall-sinal equivalent circuit. 7.) Sall-Sinal nalysis of BJT ctive Loa (Cont) Fro Fiure.3(b), the Output Voltae is v vo o o ( r r R ) o o an the sall-sinal iff-oe voltae ain is vo ( ro ro RL ) (.99) v L L (.98) Equation (.99) can be rewritten in the for (.00) o o GL r r R Lecturer: Dr Jaaluin Bin Oar 7-3

4 EEEB73 Electronics nalysis & Desin 7.) Sall-Sinal nalysis of BJT ctive Loa (Cont) Recall that V T o VT V R L o Equation (.00) can be rewritten in the for / V, r / V /, r V / The paraeters 0, 0, an G L are the corresponin conuctances. ssuin (.0) 7.) Sall-Sinal nalysis of BJT ctive Loa (Cont) The Output Resistance lookin back into the coon collector noe is R r o r o o To iniize loain effects, nee R L > R o. However, since R o is enerally lare for active loas, this conition ay not be able to be satisfie. The severity of the loain effect can be eterine by coparin R L an R o. Next 7.) Sall-Sinal nalysis of BJT ctive Loa (Cont) Exaple.0 Objective: Deterine the ifferential-oe ain of a iff-ap with an active loa, takin loain effects into account. 7.) Sall-Sinal nalysis of BJT ctive Loa (Cont) Solution: Exaple.0 (Cont) Fro Equation (.0), the open-circuit voltae ain becoes Consier the iff-ap in Fiure.30, biase with O 0.0. ssue an Early voltae of V 00 V for all transistors. Deterine the open-circuit (R L ) ifferential-oe voltae ain, as well as the ifferential-oe voltae ain when R L 00 k. V VT V 0. (00) 0. (0.06) 0. (00) 93 7.) Sall-Sinal nalysis of BJT ctive Loa (Cont) Exaple.0 (Cont) Solution: (Cont) When R L 00 k, the voltae ain is V 0. (00) VT V R L 0. (0.06) 0. (00) 00k 3 6.) Basic MOSFET Differential Pair Fiure.9 shows the basic MOSFET iff-pair confiuration usin N-MOSFET. Fiure.9: Basic MOSFET ifferential-pair confiuration. Lecturer: Dr Jaaluin Bin Oar 7-

5 EEEB73 Electronics nalysis & Desin 7.3) MOSFET Diff-p with ctive Loa Fiure.3 shows a MOSFET iff-ap with an active loa. 7.3) MOSFET Diff-p with ctive Loa (Cont) M an M are n-channel evices an for the iff pair biase with. The loa circuit consists of M 3 an M, both p-channel evices, connecte in a current-irror confiuration. Fiure.3: MOSFET iff-ap with active loa. Fiure.3: MOSFET iff ap with active loa. one-sie output v O is taken fro the coon rains of M an M. 7.3) MOSFET Diff-p with ctive Loa (Cont) When a coon-oe voltae v v v CM 7.3) MOSFET Diff-p with ctive Loa (Cont) f a sall iff-oe input voltae v v v is applie, then fro (.66) an (.67): is applie: the current splits evenly between transistors M an M, an i D i D /. i D ( / ) i (.0(a)) i D ( / ) - i (.0(b)) where i is the sinal current. There are no ate currents, therefore i D3 i D an i D i D For sall values of v, i ( v ) / 7.3) MOSFET Diff-p with ctive Loa (Cont) Since M an M are in series, can be seen that 7.) Sall-Sinal nalysis of MOSFET ctive Loa Fiure.33 is ac equivalent circuit of the iff-ap with active loa circuit, showin the sinal currents. i D3 i D ( / ) i (.03) Finally, the current irror consistin of M 3 an M prouces i D i D3 ( / ) i (.0) Fiure.33: The ac equivalent circuit, MOSFET iff ap with active loa. Lecturer: Dr Jaaluin Bin Oar 7-5

6 EEEB73 Electronics nalysis & Desin 7.) Sall-Sinal nalysis of MOSFET ctive Loa (Cont) The neative sin for i D in (.0(b)) shows up as a chane in current irection in M, as inicate in the fiure. 7.) Sall-Sinal nalysis of MOSFET ctive Loa (Cont) Therefore, the circuit can be rearrane by cobinin the sinal rouns at a coon point, as shown in Fiure.3(b). Fiure.3(a) shows the sall-sinal equivalent circuit at rain noes of M an M. Fiure.33: The ac equivalent circuit, MOSFET iff ap with active loa. By connectin the output to ate of another MOSFET (i.e. equivalent to ipeance at low frequency), output terinal is effectively an open circuit. Fiure.3: (a) Sall-sinal equivalent circuit, MOSFET iff ap with active loa an (b) rearrane sall-sinal equivalent circuit. 7.) Sall-Sinal nalysis of MOSFET ctive Loa (Cont) Fro Fiure.3(b), the Output Voltae is v vo o o ( r r ) o o (.05) an the sall-sinal iff-oe voltae ain is vo ( ro ro ) (.06) v Equation (.06) can be rewritten in the for (.07) o o r r 7.) Sall-Sinal nalysis of MOSFET ctive Loa (Cont) Recall that o o λ λ D D K n D ( λ ( λ K K n ( λ λ ) n ) / ) / then Equation (.07) becoes K n. λ λ (.08) 7.5) MOSFET Diff-p with Cascoe ctive Loa The ifferential-oe voltae ain is proportional to the output resistance (R o ) lookin into the active loa transistor. The voltae ain can be increase, therefore, if R o can be increase. n increase in R o can be achieve by usin, for exaple, a cascoe active loa. 7.5) MOSFET Diff-p with Cascoe ctive Loa (Cont) Fiure.36 shows a MOSFET ifferential aplifier with cascoe active loa. Fiure.36: MOSFET iff ap with cascoe active loa. R o for the circuit, as iscusse in the cascoe current source, is iven by R o r o r o6 ( r o ) R o r o r o6 (.09) Therefore, the sall-sinal iffoe voltae ain is v o / v (r o R o ) (.0) Next Lecturer: Dr Jaaluin Bin Oar 7-6

7 EEEB73 Electronics nalysis & Desin 7.5) MOSFET Diff-p with Cascoe ctive Loa (Cont) Exaple. Objective: Calculate the ifferential-oe ain of a MOSFET iff-ap with a cascoe active loa. Consier the iff-ap in Fiure.36. ssue that NMOS evices are available with the followin paraeters: V TN 0.5 V, k n 80 µ/v, n 0.0 V -, an (W/L) n 0. ssue that PMOS evices are available with the followin paraeters: V TP -.0 V, k p 0 µ/v, an p 0.0 V -. Choose supply voltaes of 5 V an choose a bias current of approxiately 00 µ. 7.5) MOSFET Diff-p with Cascoe ctive Loa (Cont) Exaple. (Cont) Solution: The transistor transconuctance is K n (0)( ) 0.0/V D The output resistance of iniviual transistor is ro λ D 500k 00 (0.0)( ) 7.5) MOSFET Diff-p with Cascoe ctive Loa (Cont) Exaple. (Cont) Solution: (Cont) The output resistance of the cascoe active loa is then Ro ro ro 6( ro ) R 500k 500k[ (0.0)(500k)] 0M o 7.5) MOSFET Diff-p with Cascoe ctive Loa (Cont) Ex. Do! Help yourself. The ifferential-oe voltae ain is then foun to be ( r R ) (0.0)(500k 0M) 00 o o 7.5) MOSFET Diff-p with Cascoe ctive Loa (Cont) The iff-oe voltae ain can be further increase by usin a cascoe confiuration in the ifferential pair as well as in the active loa, Fiure.37. M 3 an M are the cascoe for the ifferential pair M an M Diff-oe voltae ain is now v o / v (R o R o6 ) Larer circuits where an R o r o r o R o6 r o6 r o8 Fiure.37: MOSFET cascoe iff ap with a cascoe active loa. The sall-sinal of this type of aplifier can be in the orer of 0,000. Lecturer: Dr Jaaluin Bin Oar 7-7

8 EEEB73 Electronics nalysis & Desin 7.) BJT Diff-p with ctive Loa 7.) BJT Diff-p with ctive Loa (Cont) Fiure.8: BJT iff ap with active loa. Fiure.9: BJT iff ap with 3-transistor active loa an secon stae ain 7.) Sall-Sinal nalysis of BJT ctive Loa 7.) Sall-Sinal nalysis of BJT ctive Loa (Cont) Fiure.30: BJT iff ap with 3-transistor active loa, showin the sinal currents. Fiure.3: (a) Sall-sinal equivalent circuit BJT iff ap with active loa an (b) rearraneent of sall-sinal equivalent circuit. 7.3) MOSFET Diff-p with ctive Loa 7.) Sall-Sinal nalysis of MOSFET ctive Loa Fiure.3: MOSFET iff-ap with active loa. Fiure.33: The ac equivalent circuit, MOSFET iff ap with active loa. Lecturer: Dr Jaaluin Bin Oar 7-8

9 EEEB73 Electronics nalysis & Desin 7.) Sall-Sinal nalysis of MOSFET ctive Loa (Cont) 7.5) MOSFET Diff-p with Cascoe ctive Loa (Cont) Fiure.3: (a) Sall-sinal equivalent circuit, MOSFET iff ap with active loa an (b) rearrane sall-sinal equivalent circuit. Fiure.36: MOSFET iff ap with cascoe active loa. Lecturer: Dr Jaaluin Bin Oar 7-9