A SINUSOIDAL PWM SCHEME FOR NEUTRAL POINT CLAMPED FIVE LEVEL INVERTER

Transcription

1 International Electrical Enineerin Journal (IEEJ) Vol. 4 (3) No., pp ISSN A SINUSOIDAL PWM SCHEME FOR NEUTRAL POINT CLAMPED FIVE LEVEL INVERTER SRIHARIRAO NAMBALLA Power Electronics, Departent of Electrical & Electrical Enineerin, Visakha institute of En& Tech, Visakhapatna,(A.P), India. E-ail: srihari63@ail.co Abstract: A power electronics device which converts DC power to AC power at required output voltae and frequency level is known as an inverter. Two cateories into which inverters can be broadly classified are two level inverters and ultilevel inverters. Soe advantaes that ultilevel inverters have copared to two level inverters are iniu haronic distortion, reduced EMI/RFI eneration, and operation on several voltae levels. A ultilevel inverter can be utilized for ultipurpose applications, such as an active power filter, a static VAR copensator and a achine drive for sinusoidal and trapezoidal current applications. Soe drawbacks to the ultilevel inverters are the need for isolated power supplies for each one of the staes, the fact that they are a lot harder to build, they are ore expensive, and they are ore difficult to control in software. This focus of the siulation is on study of three phase, three-level, and five-level inverters. Full analysis for three-level and five-level inverter is included.software packaes MATLAB/SIMULINK is used to study and siulate inverter wavefors. Firstly, three phase inverters are odeled with resistive load and inductive load and their wavefors are observed. Secondly, a three-level inverter is odeled by different ways and suitable switchin control strateies (PWM technique) to carry out haronic eliination. Thirdly, a five-level inverter is odeled by different ways and suitable switchin control strateies (PWM technique) to carry out haronic eliination. Finally, all inverters odels are odeled and run in by usin MATLAB/SIMULINK. Three level and five level inverters both threephase are odeled, run and copared. Index Ters Multilevel inverter, neutral point claped (NPC), sine pulse width odulation (SPWM), switchin state, five-level inverter.introduction: The power electronics device which converts DC power to AC power at required output voltae and frequency level is known as an inverter. Two cateories into which inverters can be broadly classified are two level inverters and ultilevel inverters. One advantae that ultilevel inverters have copared to two level inverters is iniu haronic distortion. A ultilevel inverter can be utilized for ultipurpose applications, such as an active power filter, a static VAR copensator and achine drive for sinusoidal and trapezoidal current applications. Soe drawbacks to the ultilevel inverters are the need for isolated power supplies for each one of the staes, they are ore expensive, and they are ore difficult to control in software. This paper focuses on the analysis of a threelevel inverter of desirable voltae and frequency has been achieved; however, haronics distortion should be investiated durin operation. The pulse width odulation (PWM) strateies are the ost effective to control ultilevel inverters. Even thouh sine pulse width odulation (SPWM) is coplicated, it is the preferred ethod to reduce power losses by decreasin the power electronics devices switchin frequency, which can be liited by pulse width odulation. Different aspects of the threelevel NPC inverter will be discussed includin the inverter topoloy. The operation theory will be discussed with the aspect of sine pulse width odulation.. Five level NPC inverter: 98

2 International Electrical Enineerin Journal (IEEJ) Vol. 4 (3) No., pp ISSN Multilevel topoloies and odulation techniques have been developed and applied in hih power syste. With the requireent of quality and efficiency in hih power systes with the liitation of hih power device switchin speed, low total haronic distortion (THD) and low switchin frequency are desirable. MULTILEVEL conversion structures represent a solution to iprove the perforances iven by the classical structures with two voltae levels. Multilevel structures offer a reduction of the voltae stress that copensates the increased nuber of devices. Also these structures offer the advantae of reducin the size of the output filter by reducin the total haronic content. An iportant structure is the Active Neutral Point Claped Converter (ANPC) developed in. It presents the advantae of an increased nuber of derees of freedo. Also it allows the cobination with other concepts in order to create structures with hiher nuber of voltae levels and output paraeters. Another class of ultilevel converters introduces the coupled inductor concept. This type of converters offers an increased nuber of voltae levels, lower current stress in the seiconductor devices and better output voltae properties. The ost coonly used topoloies are neutral-point-claped (NPC). In neutral-pointclaped inverter the dc-link is split into nuber of saller voltae levels usin a bank of series connected bulk capacitors. The inverter structure allows the connections of the inverter poles to any of these voltae levels, thus eneratin a ulti-level voltae wavefor at the output. A three-phase five-level diode-claped inverter is shown in Fiure. Each of the three phases of the inverter shares a coon dc bus, which has been subdivided by four capacitors into six levels. The voltae across each capacitor is V dc, and the voltae stress across each switchin device is liited to V dc throuh the clapin diodes. Table lists the output voltae levels possible for one phase of the inverter with the neative dc rail voltae V as a reference. State condition eans the switch is on, and eans the switch is off. Each phase has five copleentary switch pairs such that turnin on one of the switches of the pair require that the other copleentary switch be turned off. The copleentary switch pairs for phase le a are (S a, S a ), (S a, S a ), (S a3, S a 3 ) and (S a4, S a 4 ). Table also shows that in a diode-claped inverter, the switches that are on for a particular phase le is always adjacent and in series. Fi..Three-phase five-level structure of a neutral point claped inverter. Voltae Vao Switchin state Sa4 Sa3 Sa Sa Sa 4 Sa 3 Sa Sa V4 = 4Vdc V3 = 3Vdc V = Vdc 99

3 International Electrical Enineerin Journal (IEEJ) Vol. 4 (3) No., pp ISSN V = Vdc V = Table: output voltae levels with switchin states The advantaes of NPC inverter are: (i) All of the phases share a coon dc bus, which iniizes the capacitance requireents of the inverter. For this reason, a back-to-back topoloy is not only possible but also practical for uses such as a hih-voltae back-to-back inter-connection or an adjustable speed drive. (ii)the capacitors can be prechared as a roup. (iii)efficiency is hih for fundaental frequency switchin. 3.Sinusoidal pulse width odulation (SPWM): In sinusoidal PWM instead of aintainin the width of all pulses the sae as in the case of ultiple PWM, the width of each is varied in proportion to the aplitude of a sine wave evaluated at the sae pulse. The distortion is reduced sinificantly copared to ultiple PWM (Fiure). Fi. Spw eneratin ate pulses A hih frequency trianular wave, called the carrier wave, is copared to a sinusoidal sinal representin the desired output, called the reference wave. Usually, ordinary sinal enerators produce these sinals. Whenever 9

4 International Electrical Enineerin Journal (IEEJ) Vol. 4 (3) No., pp ISSN the carrier wave is less than the reference, a coparator produces a hih output sinal, which turns the upper transistor in one le of the inverter on the lower switch off. In the other case the coparator sets the firin sinal low, which turns the lower switch ON and upper switch OFF. The nuber of pulses per half cycle depends on the carrier frequency. Within the constraint that two transistors of the sae ar cannot conduct at sae tie, the instantaneous output voltae is shown in Fiure the sae atin sinals can be enerated by usin unidirectional trianular carrier wave as in Fiure-5 this ethod is preferable and easier to ipleent. The output voltae can be varied by varyin the odulation index. The area of each pulse corresponds approxiately to the area under the sine wave between the adjacent id points of off-periods on the atin sinals. The SPWM, which is ost coonly used, suffers fro certain drawbacks like low fundaental output voltae. Advantaes of SPWM: The output voltae control is easier with PWM than other schees and can be achieved without any additional coponents. The lower order haronics are either iniized or eliinated altoether. The filterin requireents are iniized as lower order haronics are eliinated and hiher order haronics are filtered easily. It has very low power consuption. The entire control circuit can be diitized which reduces the susceptibility of the circuit to interference. Sinusoidal Pulse Width Modulation (SPWM) technique is used to enerate the ate pulses. SPWM technique is widely used in industries. Neutral point claped Three Level Inverter is the odified version of Three Level Inverter also discussed in this paper. FFT is used for haronic analysis of output of Three Level Inverter. Siple Block Diara of whole syste is iven in Fi.3 Fi.3 Block Diara 4.Siulation results: Siulation of various inverters usin sinusoidal pulse width odulation was carried out with the help of MATLAB 6.5. Siulation was carried out to observe the iproveent in the line voltae THD and Line Current THD as the inverter level increases fro 3-level and 5- level. The fi.4 and fi.5 shows final siulation diara and correspondin siulation results of line voltaes and THD results are shown in fi.6, fi.7 and also fi. 8 shows THD analysis of 3-level inverter 9

5 International Electrical Enineerin Journal (IEEJ) Vol. 4 (3) No., pp ISSN ate pulses ate pulses ate pulses ate pulses 3 ph wave od Voltae Subsyste ate pulses ate pulses3 ate pulses Pulse Circuit Scope ate pulses 3 Discrete, Ts = 5e-5 s npc inverter powerui Fi.4 five level siulation diara with spw In In In3 3 In8 4 In9 5 In 6 In 7 In 8 In3 9 In4 In5 In6 In7 3 In8 4 In v v Vab Vbc In 6 In 7 In v 3 Vca In3 9 In4 In5 In6 In7 3 In8 4 Fi.5 five level NPC inverter 9

6 Ma (% of Fundaental) vca vbc Ma (% of Fundaental) vab Selected sinal: 5 cycles. FFT window (in red): cycles International Electrical Enineerin Journal (IEEJ) Vol. 4 (3) No., pp ISSN Tie (s) Fundaental (5Hz) = 84.7, THD= 4.5% t t Haronic order t Fi6 Line to line voltaes of five level inverter Fundaental (5Hz) = 89., THD= 7.95% Haronic order Fi7 THD results for 5level inverter Fi8 THD results for 3level inverter 5. Perforance Coparison Of Three & five Level Inverters: As we know that the output obtained fro a three-level inverter is not a pure sinusoidal wavefor. It is due to the presence of haronics in the inverter output voltae which ay cause heavy losses and ay lead to low efficiency or any other applications which ay take the supply fro the inverter. So, there is a need for us to reduce these haronics. The haronics in a three level inverter is reduced by increasin the switchin frequency. But the switchin frequency is restricted by the switchin losses in hih power applications. In such applications ultilevel inverters have been widely used in recent years for the advantae of low haronic output at low switchin frequency. At the sae tie low blockin in the switchin devices can be achieved. The ore the nuber of levels of the output voltae the lesser will be the haronic content. Multi level inverters have advantaes of ood power quality, ood electroanetic copatibility, low switchin losses, hih voltae capability. These ulti level inverters are used in the active rectifiers and the FACTS applications. The ulti level inverters synthesize several voltae levels fro the various levels of the DC input. A near sinusoidal voltae wavefor can be enerated 93

7 International Electrical Enineerin Journal (IEEJ) Vol. 4 (3) No., pp ISSN fro the various levels of the DC input. They have becoe attractive in the hih power and hih voltae applications. By usin the ultilevel inverters the stress on each device is reduced proportional to the nuber of the output levels present. With several levels in the output wavefor the switchin dv/dt stresses are reduced, and hence the lifetie of otor and cables are increased. By usin a ultilevel inverter the power ratin of the equipent can enhanced without any danerous consequences. Fro the siulation results, I can say that the total haronic distortion reduces by increasin the nuber of levels in the output voltae and by the sinusoidal pulse width odulation technique the total haronic distortion reduces. Fro the wavefors obtained I can say that the output peak voltae also increases with SPWM technique. The switchin losses also reduce with the SPWM technique. The THD for the three-level SPWM is obtained as 4.5% and five-level SPWM are obtained as 7.95% shown in fi8&7 respectively. It can be observed that the control stratey has operated at a satisfactory level. 6.Conclusions: The followin conclusions have been ade on five level NPC inverter. A nuber of issues were investiated, includin the inverter confiuration, operatin principle, sinusoidal odulation (SM) techniques, and neutral point voltae control. The perforance of the threephase five-level twenty four switch inverter has been explained and observed that perforance of the inverter is iproved by eployin SPWM control schee. Sinusoidal pulse width odulation alorith has been described and applied to three-level, five-level inverter. Copared with conventional ethods, this ethod has the advantae of ease ipleentin, especially for the inverters with ore levels. Fro siulation results it is observed that the enerated voltae spectru is very uch iproved with increase the level of inverter. The use of five-level inverters reduces the haronic coponents of the output voltae copared with the three-level inverter at the sae switchin frequency. The total haronic distortion (THD) is hihly reduced as the level of the inverter is increases. So no need additional reactors or transforers to reduce the haronic coponents. Then, it is suitable for hih voltae and hih power applications. 7.References: [] A.Nabae, I. Takahashi, H.Akai A new Neutral-Point Claped PWM Inverter IEEE Trans. On Ind. App. Vol. IA- 7, No.5, Septeber/October 98, pp [] A. Kocalis, Modellin and Siulation of A Multilevel Inverter Usin SVPWM, MSc Thesis, Institute of Science, Firat University, 5. [3] S.K., Mondal, B.K., Bose, V., Oleschuk, J.O.P., Pinto, Space vector pulse width odulation of three-level inverter extendin operation into over odulation reion, IEEE Transactions on Power Electronics, Vol.8, pp.64 6, March 3. [4] A. Kocalis, and S. Sunter, Modelin and siulation of a ultilevel inverter usin space vector odulation technique, 3rd Int. Conf. on Technical and Physical Probles in Power Enineerin (TPE-6) Ankara-Turkey, pp , 9-3 May, 6. [5] A. Kocalis, Modellin and siulation of a ultilevel inverter usin SVPWM, MSc Thesis, Institute of Science, Firat University, 5. [6]B. Harira and N. S. Mariuthu. 5. Space vector switchin patterns for different applications- A coparative analysis. Proceedins of IEEE conference. pp [7] B.K. Bose Power electronics and ac drives. Prentice hall Inc., Enlewood Cliffs, New Jersey. [8] Jun Hu and Jie Chan, Rockwell Science Center, 49 Caino Dos Rios Thousand 94

8 International Electrical Enineerin Journal (IEEJ) Vol. 4 (3) No., pp ISSN Oaks, CA 936, and Fan Z. Pen Oak Ride National Laboratory Oak Ride, TN , Modular Desin of Soft-Switchin Circuit for Two-Level and Three-Level Inverters. [9] Hind Djehloud, Hocine Benalla, Space Vector Pulse Width Modulation Applied to the Three-Level Voltae Inverter, Electrotechnic's Laboratory of Constantine, Mentouri- Constantine University, Constantine 5, Aleria. [] Ayşe Kocalış and Sedat Sünter, Siulation of a Space Vector PWM Controller for a Three-Level Voltae-Fed Inverter Motor Drive, Departent of Electrical and Electronic Enineerin, Firat University, 39, Elazi. 95