CHAPTER 3 SINGLE SOURCE MULTILEVEL INVERTER


 Prosper Bridges
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1 42 CHAPTER 3 SINGLE SOURCE MULTILEVEL INVERTER 3.1 INTRODUCTION The concept of multilevel inverter control has opened a new avenue that induction motors can be controlled to achieve dynamic performance equally well as that of DC motors. Multilevel inverters produce smaller common mode voltage, therefore, the stress in the bearings of a motor connected to a multilevel motor drive can be reduced. This chapter discusses about the single source multilevel inverter. It has only one DC source and remaining are the capacitors or clamping diodes. One of the multilevel structures that has gained much attention and widely used is the Neutral Point Clamped (NPC) multilevel inverter and is also known as Diode Clamped Multi Level Inverter (DCMLI). DCMLI synthesize the small step of staircase output voltage from several levels of DC capacitor voltages (Renge and Suryawanshi 2008). The other type of single source multilevel inverter is Flying Capacitor Multilevel Inverter (FCMLI). It requires large number of capacitors to clamp the device voltage at one capacitor voltage level. 3.2 BLOCK DIAGRAM The DC source is number of cells connected together as battery. The output of battery is given to a multilevel inverter and it converts DC voltage to variable AC voltage employing the PWM technique. The inverter
2 43 output is quasi sinusoidal stepped output. The performance of the inverter output is analyzed using a induction motor load as shown in Figure 3.1 Input DC Source Switching Devices Induction Motor Control Circuit Figure 3.1 Block Diagram of Multilevel Inverter fed Induction Motor 3.3 DIODE CLAMPED MULTILEVEL INVERTER Diode clamped multilevel inverters are one of the earliest designed topologies of multilevel inverters. Figure 3.2 shows a single phase five level diode clamped inverter circuit. The two capacitors connected in the circuit split the input voltage V dc to obtain the midpoint voltage of the input. In a three level topology, the common point of capacitors is connected to the ground. Therefore, this circuit can also be called the neutral point clamped inverter (Yuan 1999). Diodes D 1 and D 2 present in the circuit aid with clamping DC voltage V dc to obtain different output voltage levels. There are nine allowable switching states for the given circuit to obtain five different output voltage levels +V dc, +V dc /2, 0, V dc /2, and V dc as shown in Table 3.1. It is to be noted that switch pairs S a1 and S a1 and S a2 and S a2 are complementary to each other. Similarly, switch pairs S b1 and S b1, and S b2 and S b2 are complementary to each other.
3 44 Figure 3.2 Circuit Diagram of Five Level Diode Clamped Multilevel Inverter Table 3.1 Five Level DCMLI Output Voltage Levels and Switching States Output Voltage Levels and Switching States S a1 S a2 S a1 S a2 S b1 S b2 S b1 S b2 V load V dc / V dc / V dc V dc / V dc / V dc The number of switches, capacitors and diodes required in the circuit increases with the number of output voltage levels desired. For every additional level of voltage, it requires an extra pair of complementary switches in each limb of the circuit, additional capacitors and clamping diodes
4 45 (Nabae et al 1981). However, in such cases, voltage balancing of the capacitors and the cost of diodes become a practical problem. Another disadvantage of DCMLI is that they need high voltage rating diodes to block the reverse voltages. 3.4 FLYING CAPACITOR MULTILEVEL INVERTER Meynard and Foch introduced a flying capacitor based inverter in The structure of this inverter is similar to that of the diode clamped inverter except that instead of using clamping diodes, the inverter uses capacitors in their place. This topology has a ladder structure of DC side capacitors, where the voltage on each capacitor differs from that of the next capacitor. The voltage increment between two adjacent capacitor legs gives the size of the voltage steps in the output waveform. One advantage of the flying capacitor based inverter is that it has redundancies for inner voltage levels; in other words, two or more valid switch combinations can synthesize an output voltage. A flying capacitor multilevel inverter operation of seven level block diagram, modulation strategies, simulation model of different level inverter and experimental verification of seven level is described in this section Seven Level Flying Capacitor Multilevel Inverter The FCMLI requires a large number of capacitors to clamp the device (switch) voltage to one capacitor voltage level. All the capacitors are of equal value and an m level inverter will require a total of (m1) x (m2)/2 clamping capacitors per phase in addition to (m1) main DC bus capacitors. The size of the voltage increment between two consecutive legs of the clamping capacitors defines the size of voltage steps in the output waveform and the voltage of the main DC link capacitor is V dc. The voltage of the innermost capacitor will be Vdc/ (m1). The voltage of the next innermost
5 46 capacitor will be V dc / (m1) + V dc / (m1) = 2 V dc / (m1) and so on. Each next clamping capacitor will have the voltage increment of V dc / (m1) from its immediate inner one. The voltage level and the arrangements of the flying capacitors in the FCMLI structure assures that the voltage stress across each switching device is same and is equal to V dc /(m1) for an m level inverter. A three phase seven level FCMLI consists of 36 switching devices and 17 capacitors connected as shown the circuit diagram. SA6 SB6 Sc6 SA5 SB5 Sc5 SA4 SB4 Sc4 SA3 SB3 SC3 SA2 SB2 SC2 SA1 SB1 SC1 SA1 SB1 SC1 SA2 SB2 SC2 SA3 SB3 SC3 SA4 SB4 SC4 SA5 SB5 SC5 SA6 SB6 SC6 Figure 3.3 Circuit Diagram of Seven Level FCMLI Fed induction Motor Three phase of a seven level inverter FCMLI fed induction motor is shown in Figure 3.3 and single phase of a seven level inverter is shown in Figure 3.4. For a three phase inverter, two more legs of same construction are coupled to the same DC link battery V dc. The single phase of seven level FCMLI inverter switches is denoted as S A1 to S A6 and S A1 to S A6. IGBTs are acting as switching devices, and V c, V c1, V c2, V c3, V c4 and V c5 are the
6 47 respective capacitor voltages. The corresponding output voltages are V dc, 5/6 V dc, 2/3 V dc, V dc /2, V dc /3 and V dc /6. The switching combinations are used to synthesize the output voltage of phase A, with respect to the neutral point n. The main DC capacitor combination, C is the energy storage element, while capacitors C A1, C A2, C A3, C A4 and C A5 are the flying capacitors that provide the multilevel voltage ability to the inverter. Figure 3.4 Circuit Diagram of Single Phase of Seven Level FCMLI The pairs of the switches (S A1, S A1 ), (S A2, S A2 ), (S A3, S A3 ), (S A4, S A4 ), (S A5, S A5 ) and (S A6, S A6 ) are closed in complementary manner. Thus S A1 is ON, S A1 is OFF and vice versa. For any initial state of clamping voltage, the inverter output voltage phase A (V An ) is given by V An = S A1 (V C V c1 ) + S A2 (V c1  V c2 ) + S A3 (V c2  V c3 ) + S A4 (V c3  V c4 ) + S A5 (V c4 V c5 ) + S A6 V c5  Vc 2 (3.1)
7 48 where S A1  Switching device of leg A; V c  Input DC voltage; V cn  Voltage across the capacitor; n  Switching device number; V An  Output voltage of phase A. The output phase voltage from Equation (3.1), when all the upper switches are in ON condition is V =1 V 5 6 V V 2 3 V V V 2 +1 V 2 V 3 +1 V 3 V 3 +1 V 3 V 6 +1(V 6 V 2 ) V = (3.2) where, Voltages V c, V c1, V c2, V c3, V c4, and V c5 are V dc, 5/6 V dc, 2/3 V dc, V dc /2, V dc /3 and V dc /6 respectively Modulation strategies The various switching strategies that have been proposed for synthesizing output voltage with minimum distortion a Sinusoidal Pulse Width Modulation (SPWM) strategy is employed. In this method, a number of triangular waveforms are compared with a controlled sinusoidal modulating signal and the switching rules are decided by the intersection of the carrier waves with the modulating signal. For a seven level inverter, a modulating signal and six carrier waves are required for each phase of the inverter as shown in Figure 3.5.
8 49 The modulating signal of each phase is displaced from each other by 120. All the carriers have the same frequency of f c and the same amplitude of A c, while the modulating signal has a frequency of f m and amplitude of A m. The f c should be in the multiples of three times to that of f m. This is required in such a way that in all the three phases, the modulating signals are 120 apart. Figure 3.5 Modulation Scheme for FCMLI The carrier wave and the sine wave are compared through comparator; hence the comparator produces the switching pulse is shown in figure 3.5. The output of the comparator defines the output voltage waveform. It is assumed that the modulating signal varies from V to 0.75V. The amplitudes of the six carrier waves vary from 0V to 0.25V, 0.25V to 0.5V, 0.5V to 0.75V in the positive half cycle of the modulating signal and from 0V to 0.25V, 0.25V to 0.5V, 0.5V to 0.75V in the negative half cycle. In the positive half cycle the output will have V, if the amplitude of the modulating signals is greater than that of the carrier wave and zero otherwise. Similarly, for the negative half cycle in this way, seven output levels are obtained as per the switching scheme given in Table 3.2. The outputs of each comparator for each phase are combined to produce the corresponding decision signals for the switches to synthesize the output
9 50 voltage of that phase. The SPWM output reference signal resembles with the output voltage waveform of the inverter and decides the voltage level that is to be generated at a particular instant. Table 3.2 Switching Schemes for Single Phase of a Seven Level FCMLI S A6 S A5 S A4 S A3 S A2 S A1 C A1 C A2 C A3 C A4 C A5 V An ON ON ON ON ON ON NC NC NC NC NC V dc /2 ON ON ON ON ON OFF NC NC NC NC + V dc /3 ON ON ON ON OFF ON NC NC NC +  ON ON ON OFF ON ON NC NC +  NC ON ON OFF ON ON ON NC +  NC NC ON OFF ON ON ON ON +  NC NC NC OFF ON ON ON ON ON  NC NC NC NC OFF OFF ON ON ON ON NC  NC NC NC V dc /6 OFF ON OFF ON ON ON NC NC OFF ON ON OFF ON ON  NC +  NC OFF ON ON ON OFF ON  NC NC +  OFF ON ON ON ON OFF  NC NC NC + OFF ON ON ON OFF OFF  NC NC + NC 0 OFF OFF ON ON ON OFF NC  NC NC + OFF OFF OFF ON ON ON NC NC  NC NC ON OFF OFF OFF ON ON + NC NC  NC ON ON ON OFF OFF OFF NC NC + NC NC ON OFF OFF OFF OFF ON + NC NC NC  V dc /6 ON OFF OFF OFF ON OFF + NC NC  + ON OFF OFF ON OFF OFF + NC  + NC ON OFF ON OFF OFF OFF NC NC ON ON OFF OFF OFF OFF NC + NC NC NC ON OFF OFF OFF OFF OFF + NC NC NC NC V dc /3 OFF ON OFF OFF OFF OFF  + NC NC NC OFF OFF ON OFF OFF OFF NC  + NC NC OFF OFF OFF ON OFF OFF NC NC  + NC OFF OFF OFF OFF ON OFF NC NC NC  + OFF OFF OFF OFF OFF ON NC NC NC NC  OFF OFF OFF OFF OFF OFF NC NC NC NC NC V dc /2 Three phase nine level inverter fed induction motor is extension of a seven level inverter fed induction motor by increasing the switches and
10 51 clamping capacitors. In a nine level inverter fed induction motor, there are forty eight numbers of switches and twenty three numbers of capacitors. From these, an eleven level inverter can be further extended by using sixty numbers of switches and twenty nine numbers of capacitors Simulation Model of Three Phase FCMLI The simulation model of three phase seven level FCMLI fed induction motor is shown in Figure 3.6. It consists of two sub systems per phase. One sub system called as switching devices and other called as controlling sub system. The seven level FCMLI fed induction motor drive has been verified through MATLAB. Simulation model of seven level FCMLI control circuit and sub system modulation scheme is shown in Figure 3.7. It consists of six carrier wave generators and a sine wave generator. Six carrier wave generators produce carrier waves, the amplitude of which is 0.25V and frequency is 1000Hz. The sine wave generator produced sine wave, with amplitude of 1.5V and frequency 50 Hz. Figure 3.6 Simulation Model of Seven Level Inverter fed Induction Motor
11 52 The generation of switching pulses for FCMLI switching devices using a modulation scheme is shown in Figure 3.8. A carrier wave generator produces a carrier waveform, and it is lifted above the zero reference as per the circuit diagram by using positive clamping circuit. A clamped carrier waveform and sine waveform are compared through a comparator. The comparator compares magnitude of both waveforms, when the magnitude of sine waveform is greater than the carrier waveform, the comparator generate the switching pulse. S A1 >= S A1 >= S A2 S A2 >= S A3 5 S A3 6 S A4 S A4 8 >= S A5 S A5 >= S A6 S A6 >= Figure 3.7 Simulation Subsystem Model of Seven Level FCMLI Modulation Scheme
12 53 The switching pulse is given to switch S A1 and switch S A1. The switching pulse to switch S A1 is given through NOT gate as shown in Figure 3.9. Similarly, all the switching pulse generated such similar other carrier waves with a sine waveform. It consists of six upper switches and six lower switches, both upper and lower switches are complimentary function. The five capacitors are coupled between the switching devices as per the simulation diagram and all the capacitors are of equal value. Figure 3.8 Switching Pulse Using Modulation Scheme S A1 S A1 Figure 3.9 Simulation Model of Switching Pulse for S A1 and S A Seven level FCMLI simulation results and discussion The output of seven level FCMLI phase voltage is shown in Figure The phase voltage has seven levels and each level is V dc /6. It can
13 54 be achieved by using switching pattern selection method. The waveform is plotted with time in X axis and voltage in Yaxis. Voltage in Volts Time in Sec Figure 3.10 Phase to Ground Voltage of Seven Level FCMLI Single phase and three phase FCMLI line voltage are shown in Figures 3.11 and 3.12 respectively. The voltage is 400V and fundamental frequency is 50Hz. The line to line voltages have thirteen levels (2P1, Where P is the number of levels in phase voltage). The seven level FCMLI line voltage of each level is V dc /14. It can be achieved by using SPWM technique. Voltage in Volts Time in Sec Figure 3.11 Line to Line Voltage of Seven Level FCMLI
14 Voltage in Volts Voltage in volt Time in sec Time in Sec Figure 3.12 Three Phase Line to Line Voltage of Seven Level FCMLI The charging and discharging of capacitor voltages V C1, V C2, V C3, V C4 and V C5 are as shown in Figure The voltage across each individual capacitor is V dc /3. A filter circuit of RLC type tuned at the switching frequency and connected in parallel with the load is to achieve the natural balancing under all conditions. Another popular method of capacitor voltage balancing is to vary duty cycle of the switches to charge or discharge the corresponding capacitors. Voltage in Volts Time in Sec Figure 3.13 Capacitor Leg Voltages V C1, V C2, V C3, V C4 and V C5 Simulation result of seven level FCMLI fed three phase induction motor speed curve is shown in Figure The time is taken along X axis and speed in rpm recorded along Y axis. The induction motor reaches its rated speed at 0.15sec. Flying capacitor multilevel inverter output is fed to the
15 56 induction motor to verify the basic performance of the inverters like voltage fluctuation, frequency variation, etc. Since the induction motor is treated as the load to the multilevel inverter, any variation in the performance of multilevel inverter reflects on the performance of motor. The investigation of simulation results which are shown in Figures 3.14 and 3.15 reveals that the performance of induction motor is satisfactory. Therefore the performance of inverter is normal Speed in rpm Time in sec Figure 3.14 Speed Curve of Seven Level FCMLI Fed Induction Motor Simulation result of seven level FCMLI fed induction motor torque curve is shown in Figure The electromagnetic torque is high and after 0.17 sec torque attains its steady state. Figure 3.15 Torque Curve of Seven Level FCMLI fed Induction Motor
16 57 The simulation result of a seven level FCMLI fed induction motor stator current is shown in Figure Initially it has maximum starting current and then gets reduced to its rated value of 7 amperes with 0.15 sec. Figure 3.16 Stator Current of Seven Level FCMLI fed Induction Motor The THD of seven level FCMLI is shown in Figure The THD value is 16.10%. A substantial reduction of 10% is obtained when compared to the five level FCMLI (26.26%). Figure 3.17 Harmonic Spectrum (THD) of Seven Level FCMLI Nine level FCMLI simulation results and discussion The phase voltage of nine level FCMLI is 200V as shown in Figure The line voltage is about 400V as shown in Figure 3.19 and
17 58 finally three phase output phase and line voltages with minimum harmonics are obtained as shown in Figures 3.20 and 3.21 respectively. The nine level FCMLI line to line voltage has seventeen level. Time in msec Figure 3.18 Phase to Ground Voltage of Nine Level FCMLI Voltage in Volts Time in msec Figure 3.19 Line to Line Voltage of Nine Level FCMLI Voltage in Volts Voltage in Volts Time in msec Figure 3.20 Three Phase Output of Phase to Ground Voltage of Nine Level FCMLI
18 59 Voltage in Volts Time in msec Figure 3.21 Three Phase Output of Line to Line Voltage of Nine Level FCMLI The nine level FCMLI is fed to induction motor drive, the rating of induction motor is 5HP, 400V with supply frequency of 50Hz and speed of 1440rpm. A nine level FCMLI fed induction motor speed curve is shown in Figure The motor speed curve is to be obtained steady state at 0.7 msec. The stator current and electromagnetic torque of induction motor are shown in Figures 3.23 and 3.24 respectively. Initially, it has maximum starting current about 40 amperes then gets reduced to its rated value in 0.6 msec. Figure 3.22 Speed Curve of Induction Motor for Nine Level FCMLI
19 60 Figure 3.23 Stator Current of Nine Level FCMLI fed Induction Motor Figure 3.24 Torque Curve of Nine Level FCMLI fed Induction Motor THD value of nine level FCMLI is 13.22%, which is shown in Figure It is a marked improvement. Figure 3.25 Harmonic Spectrum (THD) of Nine Level FCMLI
20 Eleven level FCMLI simulation results and discussion The FCMLI output of three phase voltage is same as that of the previous case. Inverter outputs such as phase voltage, line voltage and three phase line voltage are shown in Figures 3.26 to 3.28 respectively. The line to line output voltage of eleven level FCMLI has twenty one level. Time in msec Figure 3.26 Phase to Ground Voltage of Eleven Level FCMLI Voltage in Volts Voltage in Volts Time in msec Figure 3.27 Line to Line Voltage of Eleven Level FCMLI
21 62 Voltage in Volts Time in msec Figure 3.28 Three Phase Line to Line Voltage of Eleven Level FCMLI The simulation result of induction motor speed curve is shown in Figure Its settling time is only 0.6 msec. Figure 3.29 Speed Curve of Eleven Level FCMLI fed Induction Motor Figure 3.30 Stator Current of Eleven Level FCMLI fed Induction Motor
22 63 Torque in nm Time in msec Figure 3.31 Torque Curve of Eleven Level FCMLI fed Induction Motor The stator current and torque curve of induction motor is shown in Figures 3.30 and 3.31 respectively. The motor has initially high starting current and starting torque, after that the stator current and the torque of induction motor get reduced to its steady state value. THD of eleven level FCMLI has 10.62% which is shown in Figure The eleven level FCMLI, THD value is highly reduced when compared to the conventional inverters. Figure 3.32 Harmonic Spectrum (THD) of Eleven Level FCMLI Experimental Verification of Seven Level FCMLI The experimental setup for seven level FCMLI is developed by the breadboard in laboratory. Seven level FCMLI hardware implementation block diagram is shown in Figure The block diagram consists of AC source
23 64 and bridge rectifier, input block, control block, switching block and output block. The input block is related to input DC voltage. The control block related to control technique to the switching devices. The output block is related to resistive load. The input DC voltage is connected to switching devices, which acts depending on the signals from control circuit to set the AC output voltage from inverter. The control circuit block consists of two waveform generators; one is sine wave generator and another triangular wave generator. The triangular generator waveform has lifted up and down by using clamping circuits. The comparator inputs are sine wave and clamped triangular waves. The comparator output is given to switching devices whose output voltage is fed to the load. In hardware implementation of seven level FCMLI, the applied input voltage is 24V and is known as V dc. The input voltage V dc is divided by capacitor dividing circuit. Using capacitor, V dc is divided into two levels that is V dc /2. Figure 3.33 Block Diagram of Seven Level FCMLI
24 Control circuits of seven level FCMLI The control circuit for seven level FCMLI is shown in Figure It consists of RC phase shift oscillator, triangular wave generator, positive clamping circuit, negative clamping circuit and comparator circuit. The RC phase shift oscillator produced sine waveform that is called as reference wave. The sine and triangular waves are given to comparator circuits as shown the circuit diagram. The carrier waveform lifted up and down using positive and negative clamping circuits. The clamped triangular waveform is one of the input to the comparator circuit. The comparator output is given to upper switches S A1 to S A6 and also is given to lower S A1 to S A6 through NOT gates. RC phase shift oscillator S A1 S A2 S A3 S A4 S A5 S A6 S A6 S A5 S A4 S A3 S A2 S A1 Figure 3.34 Control Circuit of Seven Level FCMLI Output of sine wave generator The experimental result of sine wave is shown in Figure Amplitude of sine waveform is 8V at 50 Hz. The waveforms measured through Digital Storage Oscilloscope (DSO).
25 66 Figure 3.35 Sine Waveform Output of triangular wave generator A triangular wave generator produces carrier wave. It is shown in Figure The amplitude of triangular waveform is 2V and frequency is 1000 Hz. The carrier frequency are selected depends on the harmonics elimination techniques. The SPWM eliminates the harmonics. In this work ten carrier waves compared with half sine wave, it eliminates the lower order harmonics. Figure 3.36 Triangular Waveform
26 Switching pulses The seven level FCMLI required six carrier waves and each carrier waveform is lifted up and down. The carrier wave lifted up and down from zero reference level by using positive and negative clamping circuit for Phase Disposition Pulse Width Modulation (PDPWM) generation illustrated in Figure 3.37 (a) to (f). Each carrier wave lifted up and down 1V, 3V and 5V respectively from the zero reference level. It consists of a capacitor, a diode and then a DC source is used for lift up or down the voltage level. The applied DC voltage is varied by using a potentiometer. (a) (b) (c) (d) Figure 3.37 Clamping Carrier Waveforms
27 68 (e) (f) Figure 3.37 (Continued) For improving the performance of FCMLI, a switching pattern selection scheme is implemented. This reduces capacitor voltage fluctuation without using voltage feedback and Resistance Inductance and Capacity (RLC) filter circuits connected in parallel with the load. The sinusoidal PWM technique has been used while making the proposals. The selected pattern has been shown to give superior performance in load voltage, THD and mean capacitor voltage fluctuation. Sinusoidal PWM based PD PWM methods are illustrated. Clamping carrier and sine waveforms are shown in Figure 3.38 (a) to (f). The reference waveform and clamping carrier waveforms are compared through a comparator. (a) (b) Figure 3.38 Clamping Carrier and Sine Waveforms
28 69 (c) (d) (e) Figure 3.38 (Continued) (f) The comparator produces the pulses depending upon reference wave and carrier waves. An example of pulse generation of switching device is illustrated in Figure Figure 3.39 Pulse Generation of Switching Device
29 70 The generated pulses are given to switching devices. If generated gate voltage is given to switch 1(S A1 ) in upper switches then the same switching voltage is given to lower switch 1 (S A1 ) through NOT gate. Similarly all the gate pulses are given to switching devices. All the generated gate pulses are illustrated in Figure 3.40 (a) to (l). (a) (b) (c) (d) (e) (f) Figure 3.40 Switching Pulses for MOSFET
30 71 (g) (h) (i) (j) (k) Figure 3.40 (Continued) (l)
31 Output phase voltage of FCMLI The seven level FCMLI output phase voltage is shown in Figure All the gate voltages are given as per modulation signal to switching devices and finally, seven level output voltage is obtained. The phase voltage of seven level FCMLI is 18V, with frequency of 50 Hz. The V dc of seven level FCMLI is 12V. Figure 3.41 Experimental Result of Seven Level FCMLI Single phase flying capacitor multilevel inverter experimental set up was developed using the bread board. The experimental set up of single phase flying capacitor multilevel inverter performance behavior has been verified using Resistive Load. The photography view of the experimental setup of flying capacitor multilevel inverter is shown in Figure 3.42.
32 73 Figure 3.42 Photography View of Seven Level FCMLI 3.5 SUMMARY In this chapter, single source multilevel inverter of FCMLI of seven, nine and eleven level are discussed to obtain sinusoidal waveform and THD values. The single source multilevel inverter fed induction motor has also been illustrated in simulation results by using MATLAB. In hardware implementation, the result of seven level FCMLI were discussed.
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