Comparison Of Seven Level Inverter With Reduced Number Of Switches And Their Thd's In PI Controller

Transcription

1 IOSR Journal of Electronics and Counication Enineerin (IOSR-JECE) e-issn: ,p- ISSN: PP Coparison Of Seven Level Inverter With Reduced Nuber Of Switches And Their Thd's In PI Controller Manivara.M, Suuna.J, Vial raj.p, Christ Collee of Enineerin and Technoloy,Pondicherry. Abstract This paper ives a description about a seven level inverter, which henceforth shows the coparison of their THD levels while coparin it with various nubers of switches. In addition to that a PI controller is siulated with RL and IM as its loads with their correspondin THD's are siulated in Matlab. The above entioned coparison is ipleented usin tie-doain siulation studies. Keywards PI-Proportional Interal controller, THD-Total Haronic Distortion, HVDC- Hih voltae DC transission, CSI- current source inverter, VSI-voltae source inverter, MLI - Multilevel Inverter, CHBcascaded H bride inverter, FCI-Flyin capacitor inverter, DCI-Diode claped inverter. I. INTRODUCTION Now a day's MLI has been reatly focused to the Industrial and Grid, since MLI have investiated in the field of odular ulti-level inverters have led to successful operation in HVDC systes. In recent ties, in the power transission era, for very lon distances, HVDC lines based on CSI and VSI are found to be offerin ore econoical and cost effective power transission. But, recently HVDC transission systes based on VSI have received increasin attention due to the any opportunities like the rid access of weak AC networks, independent control of active and reactive power, supply of passive networks and black start capability, hih dynaic perforance and sall space requireents. Switchin power converters are used in industrial application to convert and deliver their required enery to the otor or load because of advances in solid state power devices and icroprocessors. This paper is oranized into four sections. Section- describes the various structures of MLI. Section - II discusses the different PWM with reduced nuber of switches. Section III ipleented in seven-level in the RL load with PI controller, and Model Predictive Controller usin MATLAB / Siulink Section IV the conclusion is drawn. The MLI are structured into three different types based on diodes, capacitors and power seiconductor devices: A) Diode claped inverter (DCI), B) Flyin capacitor inverter (FCI) and C) Cascaded H bride inverter (CHB). A. Diode claped Inverter The ost coonly used MLI topoloy is DCI in which the diode is used as the clapin device to clap the DC bus voltae so as to achieve steps in the output voltae as discussed in [] and [4]. Thus, the ain concept of this inverter is to use diodes to liit the power devices voltae stress. The voltae over each capacitor and each switch is Vdc. A n level inverter needs (n-) voltae sources, (n-) switchin devices and (n-) (n-) diodes. Fiure. (a) shows three-level diode-claped converter in which the DC bus has two capacitors C, C. For DC-bus voltae V dc, the voltae across each capacitor is Vdc/ and each device voltae stress will be liited to one capacitor voltae level Vdc/ throuh clapin diodes. The staircase voltae is synthesized, the neutral point n is considered as the output phase voltae reference point there are three switch cobinations to synthesize three-level voltaes across a and n.. Voltae level Van= Vdc/, turn on the switches S and S.. Voltae level Van= 0, turn on the switches S and S '. 3. Voltae level Van= - Vdc/ turn on the switches S, S. Fiure.(b) shows a seven-level diode-claped converter in which the DC bus consists of four capacitors C, C, C 3, and C 4. For DC-bus voltae Vdc, the voltae across each capacitor is Vdc/4 and each device voltae stress will be liited to one capacitor voltae level Vdc/4 throuh clapin diodes. International Conference on Eerin Trend in Enineerin and Manaeent Research (ICETEMR-06) 3 Pae

2 Coparison Of Seven Level Inverter With Reduced Nuber Of Switches And Their Thd's In Fiure.: Diode-Claped Multilevel Inverter Circuit Topoloies. (A) Three-Level.(B) Five-Level. B. Flyin Capacitor ultilevel Inverter The structure of Flyin capacitor MLI is siilar to that of the diode-claped inverter except that instead of usin clapin diodes, the inverter utilizes capacitors in their place. The Multicarrier PWM was explained in Flyin capacitor structures which has a series connection of cells [6]. This topoloy has a ladder structure of dark side capacitors, where the voltae on each capacitor differs fro that of the next capacitor. The voltae increent between two adjacent capacitor les ives the size of the voltae steps in the output wavefor. Fi shows sinle phase n-level confiuration of the capacitor claped inverter. A n-level inverter will require a total of (n-) (n-) / clapin capacitors per phase le in addition to (n-) ain DC bus capacitors. The voltae levels and the arraneents of the flyin capacitors in the FCI structure assures that the voltae stress across each ain device is sae and is equal to Vdc/(n-), for a n-level inverter. The voltae synthesis in a five-level capacitor-claped converter has ore flexibility than a diode-claped converter. Usin Fiure.(b) the voltae of the five-level phase-le a output with respect to the neutral point n (i.e.van), can be synthesized by the followin switches cobinations.. Voltae level Van= Vdc/, turn on all upper switches S - S4.. Voltae level Van= Vdc/4, there are three cobinations. A. Turn on switches S, S, S3 and S.(Van= Vdc/ of upper C4's - Vdc/4 of C's). B. Turn on switches S, S3, S4 and S4.(Van= 3Vdc/4 of upper C3's - Vdc/ of C4's). C. Turn on switches S, S3, S4 and S3. (Van= Vdc/ of upper C4's - 3Vdc/4 or C3's + Vdc/ of upper C's). 3. Voltae level Van= 0, turn on upper switches S3, S4, and lower switch S, S. 4. Voltae level Van= -Vdc/4, turn on upper switch S and lower switches S, S and S3. 5. Voltae level Van= -Vdc/, turn on all lower switches S, S, S3 and S4. Fiure.: Capacitor-Claped Multilevel Inverter Circuit Topoloies, (A) 3-Level Inverter (B) 5- Level Inverter. International Conference on Eerin Trend in Enineerin and Manaeent Research (ICETEMR-06) 33 Pae

3 Coparison Of Seven Level Inverter With Reduced Nuber Of Switches And Their Thd's In B. Cascaded H bride inverter The Cascaded H bride inverter has ore advantaes than other two entioned. Cascaded H bride inverter does not have flyin capacitors and clapin diodes. The ain drawback of Cascaded H bride inverter is that the nuber of devices used increases with the nuber of levels and this increases the ate drive circuits at control stae itself causin hih cost and switchin losses.to overcoe above disadvantaes the choice is a hybrid ultilevel inverter which is derived fro cascaded H-bride inverter as in [0] and [8].. In order to control the MLI output voltae there are several control techniques. The ost efficient ethods are based on sinusoidal PWM techniques as in [6], because it leads to easy control of inverter fundaental voltae and as well as eliinatin the haronics. These are cascaded to et the ultilevel output as in [7]. For n level CHB inverter (n-) / nuber of independent sources are required. In eneral independent sources ay be renewable enery sources like sae rated solar panels or fuel cells or wind enery sources. Sinle Phase Structures Of Cascaded Inverter shown in Fiure.. The switchin anles can be chosen in such a way that the total haronic distortion is iniized. One of the advantaes of this type of MLI is that it needs less nuber of coponents copared to the Diode claped or the flyin capacitor as in [0], so the price and the weiht of the inverter is less than that of the two types. Fiure.3 shows the power circuit for one phase le of a three-level and five-level cascaded inverter.in a 3-level cascaded inverter each sinle-phase full-bride inverter enerates three voltaes at the output: +Vdc, 0, -Vdc (zero, positive DC voltae, and neative DC voltae). This is ade possible by connectin the capacitors.the resultin output AC voltae swins fro -Vdc to +Vdc with three levels, -Vdc to +Vdc. In this topoloy, the nuber of outputs-phase voltae levels are defined by M=N+, where M is the no of levels and N is the nuber of DC sources. So, for an exaple the output phase voltae of eleven level inverter is iven by Van= Va+Va+Va3+Va4+Va5. Fiure.3: Sinle Phase Structures Of Cascaded Inverter (A) 3-Level, (B)5-Level II. DIFFERENT PWM WITH REDUCED NUMBER OF SWITCHES The ost efficient ethod of controllin output voltae is to incorporate PWM control within inverters as described in [3] and [8]. In this ethod, a fixed DC voltae is supplied to inverter and a controlled AC output voltae is obtained by adjustin on-off period of inverter devices. Pulse Width Modulation variable speed drives are increasinly applied in any new industrial applications that require superior perforance. Recently, developents in power electronics and seiconductor technoloy have lead iproveents in power electronic systes. Hence, different circuit confiurations, naely PWM inverters have becoe popular and considerable interested by researcher are iven to the. A nuber of Pulse width odulation (PWM) schees are used to obtain variable voltae and frequency supply. The ost widely used PWM schee for voltae source inverters as in [], is sinusoidal PWM. The control of IM nuber as in [6], of Pulse width odulation (PWM) schees are used for variable voltae and frequency supply and ain objective of this paper is an analysis of an Induction otor with SVPWM fed inverter and haronic analysis of voltaes & current. There is an increasin trend of usin space vector PWM (SVPWM) because of it reduces the haronic content in voltae, Increase fundaental output voltae by 5% & sooth control of IM. A space vector PWM technique is also developed based on the vector space decoposition. The techniques developed in this paper can be eneralized for the control of an induction achine with an arbitrary nuber of phases. In space vector PWM ethod for a three-level inverter fed induction otor drive, a nuber of Pulse Width Modulation (PWM) schees are used to obtain variable voltae and frequency supply fro an inverter. There is an increasin trend of usin SVPWM because of their easier diital realization and better DC bus utilization. International Conference on Eerin Trend in Enineerin and Manaeent Research (ICETEMR-06) 34 Pae

4 Coparison Of Seven Level Inverter With Reduced Nuber Of Switches And Their Thd's In A. Pulse Width Modulation Technique Because of advances in solid state power devices and icroprocessors, switchin power converters are used in industrial application to convert and deliver their required enery to the otor or load. PWM sinals, pulse trains with fixed frequency and anitude and variable pulse width as in [4]. There is one pulse of fixed anitude in every PWM period. However, the width of the pulse chanes fro pulse to pulse accordin to a odulatin sinal. When a PWM sinal is applied to the ate of a power transistor, it causes the turn on and turns off intervals of the transistor to chane fro one PWM period to another PWM period accordin to the sae odulatin sinal. The frequency of a PWM sinal ust be uch hiher than that of the odulatin sinal, the fundaental frequency, such that the enery delivered to the otor and its load depends ostly on the odulatin sinal. Fiure 4: Syetric and Asyetric PWM Sinals Fiure.4 shows two types of PWM sinals, syetric and asyetric. The pulses of a syetric PWM sinal are always syetric with respect to the center of each PWM period. The pulses of an asyetric PWM sinal always have the sae side alined with one end of each PWM period. It has been shown that syetric PWM sinals enerate fewer haronics in the output currents and voltaes. This literature considers three popular PWM techniques for the ost used three phase voltae source power inverter applications. This is the ost popular ethod of controllin the output voltae and this ethod is tered as Pulse-Width Modulation (PWM) Control. The advantaes possessed by PWM techniques are Lower power dissipation, Easy to ipleent and control, No teperature variation and ain-caused driftin or deradation in linearity, Copatible with today s diital icro-processors, the output voltae control can be obtained without any additional coponents and with the ethod, lower order haronics can be eliinated or iniized alon with its output voltae control. As hiher order haronics can be filtered easily, the filterin requireents are iniized. The ain disadvantae of this ethod is that SCRs are expensive as they ust possess low turn-on and turn-off ties. B Sinle pulse width odulation In sinle pulse-width odulation control, there is only one pulse per half-cycle and the width of the pulse is varied to control the output voltae. Fiure 5 shows the eneration of atin sinals of sinle pulse width odulation. The atin sinals are enerated by: Fiure 5: The eneration of atin sinals of sinle pulse width odulation International Conference on Eerin Trend in Enineerin and Manaeent Research (ICETEMR-06) 35 Pae

5 Coparison Of Seven Level Inverter With Reduced Nuber Of Switches And Their Thd's In The sinle pulse-width odulation converts the reference sinal to the square wave sinal. This process is obtained by inter the reference sinal to the zero-crossin circuit which considers the positive part of the input sinal is positive part of the output sinal(square wave) and the neative part of the input sinal is neative part of the output sinal as shown in Fiure 5. C Multi-Pulse width odulation The haronic content can be reduced by usin several pulses in each half-cycle of output voltae. The eneration of atin sinals for turnin on and off transistors is shown in Fiure 6. The atin sinals are produced by coparin a reference sinal with a trianular carrier wave. The frequency of the reference sinal sets the output frequency (fo) and carrier frequency (fc) deterines the nuber of pulses per half cycle, p = fc/f0 Fiure 6: The eneration of atin sinals of ulti -pulse width odulation D The Carrier-Based Pulse Width Modulation (PWM) Technique As entioned earlier, it is desired that the AC output voltae Vo=VaN follow a iven wavefor (e.., sinusoidal) on a continuous basis by properly switchin the power valves. The carrier-based PWM technique fulfills such a requireent as it defines the on and off states of the switches of one le of a VSI by coparin a odulatin sinal Vc (desired AC output voltae) and a trianular wavefor VΔ (the carrier sinal). In practice, when Vc > VΔ the switch S+ is on and the switch S- is off; siilarly, when Vc < VΔ the switch S+ is off and the switch S- is on. Fiure 7: The eneration of atin sinals of Carrier-Based pulse width odulation Fiure 7 clearly shows that the AC output voltae Vo=VaN is basically a sinusoidal wavefor plus haronics. A special case is when the odulatin sinal Vc is a sinusoidal at frequency fc and aplitude, Ṽc and the trianular sinal VΔ is are bein at frequency fδ and aplitude ṼΔ. This is the Sinusoidal PWM (SPWM) schee. In this case, the odulation index a (also known as the aplitude-odulation ratio) is defined as; a = V c /V Δ And the noralized carrier frequency f (also known as the frequency-odulation ratio) is f= fδ/ fc International Conference on Eerin Trend in Enineerin and Manaeent Research (ICETEMR-06) 36 Pae

6 Coparison Of Seven Level Inverter With Reduced Nuber Of Switches And Their Thd's In III. SIMULATION RESULTS A Siulation study without controller Here the siulation studies are carried under tie-doain basis. We can use alorith and direct ethod for pulse eneration. For siulation purposes we can use any type of switches like MOSFET,IGBT., etc. Or any other fors, the MOSFET are ostly preferable. Here an alorith is carried out for pulse eneration and also direct pulses are also iven to the correspondin switches. The Fiure.8 shows that it consists of twelve switches to obtain a seven level output. Here a sortin alorith is used to decide which switch has to be turned ON and OFF correspondinly with their odulation indices. Basically here basically we use R or RL load throuh which we obtain the output. Both the current and voltae wavefors are easured and a saple is shown below. Fro the obtained output the THD is calculated and shown in the below fiure. The obtained THD for twelve switches, seven level inverter is 9.00% as shown in Fiure.9. Continuous Scope + - v Scope Scope Scope3 Fiure.8: Sinle phase seven level inverter with twelve switches Fiure.9: THD wavefor for twelve switches(thd=9.00%) The siulation for seven level inverter consistin of ten switches is shown in Fiure.0. This structure consists of ten switches which are connected in a Cascaded H bride anner, since it has the hiher priority. The first switch conducts for positive half cycle and a second switch conducts for the neative half cycle. The saple of the wavefor is shown in Fiure.6 and the THD is shown in Fiure.. The THD obtained here is 7.% International Conference on Eerin Trend in Enineerin and Manaeent Research (ICETEMR-06) 37 Pae

7 Coparison Of Seven Level Inverter With Reduced Nuber Of Switches And Their Thd's In Scope4 powerui <= Discrete, Ts = 5e-005 s <= Scope + - v >= >= Scope Fiure.0:Sinle phase seven level inverter with ten switches Fiure.: THD wavefor for ten switches(thd=7.%) The siulation for seven level inverter consistin of eiht switches is shown in Fiure.. It consists of eiht switches which are connected in a Cascaded H bride anner, since it has the hiher priority. In the separated brides the first bride conducts for positive half cycle and second bride conducts for the neative half cycle. The saple of the wavefor is shown in Fiure.6 and their correspondin THD is shown in Fiure.3. The THD obtained here is 6.66% Scope4 powerui <= Discrete, Ts = 5e-005 s Scope <= + - v >= >= Scope Fiure.:Sinle phase seven level inverter with eiht switches Fiure.3: THD wavefor for eiht switches (THD=6.66%) International Conference on Eerin Trend in Enineerin and Manaeent Research (ICETEMR-06) 38 Pae

8 S D D S Coparison Of Seven Level Inverter With Reduced Nuber Of Switches And Their Thd's In The siulation for seven level inverter consistin of five switches is shown in Fiure.4. It consists of five switches which are connected in a Cascaded H bride anner. Each set of switches consists of individual pulse production. Here sortin alorith is used to produce pulses. This construction shows a coplete view of the Cascaded Multi level Inverter. Like this anner we can build n nuber of H brides for various levels to obtain various THD's. The saple of the wavefor is shown in Fiure.6, which ives the output voltae and current wavefors for seven level inverter and their correspondin THD is shown in Fiure.5. The THD obtained here is 4.5% Discrete, s = 5e-005 s powerui DC Voltae Source Mosfet3 D S Mosfet i + - Display Current DC Voltae Source D S Mosfet Scope DC Voltae Source D S Mosfet v v + - Mosfet4 Zero-Order Hold Display Scope s io s DC Voltae Source3 fcn s3 Sine Wave Zero-Order Hold iref s4 s5 Ebedded MATLAB Function Scope Fiure.4:Sinle phase seven level inverter with the five switches Fiure.5:THD wavefor for five switches(thd=4.5%) B Fiure.6: Output Voltae and Current wavefors for seven level inverter Siulation study with controller (PI controller) In this section the coparison is carried out in a closed loop anner, i.e., a controller is introduced. It can be any type of controller, here we are usin a PI controller. The nuber of switches used here is five switches, their ate sinals are iven by eans of sortin alorith as shown in Fiure 3. The load used here is a RL load and their correspondin references are fed to the controller and throuh the controller it is fed to the alorith fro which ate sinals are enerated and fed to the inverter switches. The output voltae and current wavefors are shown in Fiure 8 and their correspondin THD obtained here are 6.00% as shown in Fiure 4. The THD is done in MATLAB by usin the FFT analysis to obtain is a particular value. International Conference on Eerin Trend in Enineerin and Manaeent Research (ICETEMR-06) 39 Pae

9 Coparison Of Seven Level Inverter With Reduced Nuber Of Switches And Their Thd's In Fiure 3: Sinle phase siulation of seven level inverter with PI controller and RL load Fiure.4:THD wavefor (THD=6.00%) In the second half of the syste consists of sae PI controller with IM as its load.here also the sae five switches are used, but only the load alone is varied.the IM used here is a noral asynchronous IM throuh which the followin easureents are carried out: rotor current, ain windin current, auxiliary windin current, rotor speed, electroanetic torque. The sae controller is fetched to the alorith and throuh which pulses are fed to switches as shown in Fiure 5. Their correspondin THD wavefor is shown in Fiure 6. The THD obtained here is 7.%. The output wavefor fro the IM is also shown with their separate currents as shown in Fiure 7. The output voltae and current wavefors of a seven level inverter is also shown in Fiure 8. Fiure 5: Sinle phase siulation of seven level inverter with PI controller and IM load International Conference on Eerin Trend in Enineerin and Manaeent Research (ICETEMR-06) 40 Pae

10 Coparison Of Seven Level Inverter With Reduced Nuber Of Switches And Their Thd's In Fiure.6: THD wavefor (THD=7.%) Fiure 7: Output wavefor of IM Fiure 8: Output current and voltae wavefor for seven level inverter. Table I Coparison of THD SWITCHES LEVEL THD % % % % IV. CONCLUSION The ost efficient ethod of controllin output voltae is to incorporate PWM control within inverters. In this ethod, a fixed d.c. voltae is supplied to inverter and a controlled a.c. output voltae is obtained by adjustin on-off period of inverter devices with Pulse Width Modulation that require superior perforance. There are so any techniques which are used for controllin of induction otor drives and PWM technique iproves the quality of the current and reduce the torque ripple in induction otor drive efficiently while aintainin the other perforance characteristics of the syste. Table shows the THD with seven level with reduced nuber of switches and lower switches has 4.5% International Conference on Eerin Trend in Enineerin and Manaeent Research (ICETEMR-06) 4 Pae

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