NEW ELECTRONICALLY TUNABLE GROUNDED INDUCTOR SIMULATOR EMPLOYING SINGLE VDTA AND ONE GROUNDED CAPACITOR

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1 Journal of Enineerin Science and Technoloy Vol., No. (7) 3-6 School of Enineerin, Taylor s University NEW ELECTRONICALLY TUNABLE GROUNDED INDUCTOR SIMULATOR EMPLOYING SINGLE VDTA AND ONE GROUNDED CAPACITOR MAYANK SRIVASTAVA, DINESH PRASAD, *, D. R. BHASKAR 3 Departent of Electronics and Counication Enineerin, ASET, Aity University, Sector-5, Noida (U.P.)-33, India,3 Departent of Electronics and Counication Enineerin, Faculty of Enineerin and Technoloy, Jaia Millia Islaia, New Delhi-5, India *Correspondin Author: dprasad@ji.ac.in Abstract In this paper a new rounded inductor siulator eployin sinle voltae differencin transconductance aplifier (VDTA) and one rounded capacitor has been proposed. The proposed circuit is electronically controllable and exhibits low parasitic effects. The perforance of proposed inductor siulator is deonstrated by SPICE siulations with TSMC CMOS.8 µ process paraeters. Keywords: Grounded inductor siulator, Electronic control, VDTA, Grounded capacitor, Active inductor.. Introduction The Inductor is an interal part of any analo circuits such as filters, oscillators, phase shifters etc. A conventional spiral inductor has several drawbacks such as lare sie and weiht, enerates unwanted haronics of the sinals due to saturation of its core, picks as well as radiates electroanetic waves etc. Its quality factor and liner diensions are directly proportional to each other. Hence, it is not possible to desin a sall sie inductor with hih quality factor. Therefore, in last three decades, attention is extensively focused on active siulation of inductors. Nuerous actively siulated rounded inductor confiurations eployin different active buildin blocks such as operational aplifiers (Op-ap)[-4], current conveyors (CC) [5], Op-aps[6], voltae current conveyors(dvcc)[7], CC[8], Op-ap[9], CCs [-6], Current feedback- 3

2 4 M. Srivastava et al. Noenclatures C A, C C, C, C C P C N C X+ C X- C Z,, I b, I b, I b3, I b4, I b I X+ I X- I Z L, L A, L GI, L eq R R, R A, R, R R P R N R X+ R X- R Z s V in (s) V out (s) V N V P V VN V VP V Z W/L Z in Equivalent capacitances, μf External capacitances, μf Parasitics capacitance at P port of VDTA, pf Parasitics capacitance at N port of VDTA, pf Parasitics capacitance at X+ port of VDTA, pf Parasitics capacitance at X- port of VDTA, pf Parasitics capacitance at Z port of VDTA, pf Transconductance ains of VDTA, μa/v Bias currents of VDTA, μa Current at X+ port of VDTA, A Current at X- port of VDTA, A Current at Z port of VDTA, A Equivalent inductances, μh External resistance, kω Equivalent resistances, kω Parasitics resistance at P port of VDTA, kω Parasitics resistance at N port of VDTA, kω Parasitics resistance at X+ port of VDTA, kω Parasitics resistance at X- port of VDTA, kω Parasitics resistance at Z port of VDTA, kω Laplace operator Input voltae, V Output voltae, V Voltae port N of VDTA Voltae port P of VDTA Voltae at N port of VDTA, V Voltae at P port of VDTA, V Voltae at Z port of VDTA, V Shape factor Input ipedance Greek Sybols β x+ Output stae trackin error (at por X+) of VDTA β x- Output stae trackin error (at port X-) of VDTA β Input stae trackin error (at port Z) of VDTA ω, ω Pole frequencies, MH τ, τ Tie delays, μs Abbreviations CC Current conveyors CDTA Current differencin transconductance aplifier CFOA Current feedback operational aplifiers CMOS Copleentary etal oxide seiconductor Journal of Enineerin Science and Technoloy January 7, Vol. ()

3 New Electronically Tunable Grounded Inductor Siulator Eployin DC DVCC FTFN MOS OP- AMP OTA OTRA SPICE TSMC VDTA Direct current Differential voltae current conveyors Four terinal floatin nullors Metal oxide seiconductor Operational aplifiers Operational transconductance aplifier Operational trans-resistance aplifier Siulation Prora with Interated Circuit Ephasis Taiwan Seiconductor Manufacturin Copany Voltae differencin transconductance aplifier operational aplifiers (CFOA)[7-9], current differencin trans-conductance aplifiers (CDTA)[], four terinal floatin nullors(ftfn)[], Current Follower transconductance aplifier (CFTA)[], Fully Differential Second-Generation Current Conveyor (FDCCII) )[3], Voltae differencin differential input buffered aplifiers(vddiba)[4]. Dual output Differential Difference current conveyor (DO-DDCC)[5], CFOA[6], Dual-X current conveyor (DX-CCII)[7-8], Operational trans-conductance aplifiers(ota)[9], Differential difference current conveyor(ddcc)[3],operational trans-resistance aplifiers(otra)[3], voltae differencin transconductance aplifiers (VDTA)[3], Voltae differencin buffered aplifiers(vdba) )[33] and Voltae differencin current conveyors(vdcc)[34] have been proposed in the literature. Unfortunately, all of the reported circuits suffer fro one or ore of followin drawbacks: (i) Excessive (ore than one) use of the active coponents [], [6], [7], [9], [], [4-6], [8], [], [], [4], [3]. (ii) Excessive(ore than one) use of the passive coponents [-3], [5], [6], [8- ], [3], [5], [7-9], [-3], [5-3], [33-34]. (iii) Partial utiliation of active coponent(s) [7], [9], [8], [3], [9], [3-34]. (iv) Use of floatin passive coponent(s) [-], [3], [5-9], [], [5-3], [33]. (v) Lack of electronic controllability [-6], [8-], [3-9], [], [3], [5-3]. (vi) Requireent(s) of external passive coponent atchin constraints [-3], [8], [-], [3], [], [7], [3-3]. (vii) Hih parasitic effects [4], [3-33]. Therefore, the purpose of this counication is to propose a new rounded inductor siulator circuit coposed of iniu active and passive coponents (sinle VDTA and one rounded capacitor) with followin advantaeous features: (i) use of a rounded capacitor, (ii) availability of electronic control, (iii) no requireent of any external passive coponent atchin constraint (iv) full utiliation of VDTA and (v) low parasitic effects.. Proposed Grounded Inductor Siulator VDTA [35-36] is a versatile active eleent finds several applications in analo filter desinin [37-39], oscillators [4] and inductor siulators [4]. The scheatic sybol of the VDTA and CMOS ipleentation of VDTA are shown in Fi. and Fi. respectively, where P and N are input terinals and Z, X+ and Journal of Enineerin Science and Technoloy January 7, Vol. ()

4 6 M. Srivastava et al. Journal of Enineerin Science and Technoloy January 7, Vol. () X- are output terinals. All terinals of VDTA exhibit hih input ipedance values. The terinal characteristics of VDTA can be described by: Z V V X X Z V V V I I I N P () Fi.. The scheatic sybol of VDTA. Fi.. CMOS ipleentation of VDTA [36]. The proposed rounded inductance circuit is shown in Fi. 3. A routine analysis of this circuit yields the followin expression for its input ipedance: in sc Z () with Thus the circuit siulates a lossless rounded inductor with inductance value. eq C L (3) which is electronically tunable by.

5 New Electronically Tunable Grounded Inductor Siulator Eployin The condition can be easily achieved in practice by equatin the two bias currents of VDTA and does not require any external passive coponent atchin. Fi. 3. Proposed rounded inductance siulator confiuration. 3. Non-ideal analysis and effects of Parasitics In the non ideal case, the VDTA can be characteried by the followin equations I I I Z Z P N V V (4) X X V (5) Z X V (6) X Z where β Z, β X+ and β X- are voltae trackin errors. Under non ideal conditions the input ipedance of circuit proposed in fiure 3 is iven by Z in x sc (7) x Therefore, the circuit siulates a rounded series R - L circuit rather than a pure rounded inductor at low frequencies. where R and L x x x C (9) To evaluate the hih frequency perforance, the proposed rounded inductor is investiated under the influence of VDTA. X+ port parasitic ipedance consistin of a capacitor C x+ in parallel with resistance R x+, X- port parasitic (8) Journal of Enineerin Science and Technoloy January 7, Vol. ()

6 8 M. Srivastava et al. ipedance consistin of a capacitor C x- in parallel with resistance R x-, P port parasitic ipedance consistin of a capacitor C P in parallel with resistance R P, N port parasitic ipedance consistin of a capacitor C N in parallel with resistance R N and Z port parasitic ipedance consistin of a capacitor C Z in parallel with resistance R Z The expression of non ideal input ipedance of proposed confiuration is found to be; Z in where sc scz scn scx RZ RX sc scz scn scx RZ RX RX. sc P sc X () The non ideal equivalent circuit of proposed rounded inductor siulator shown in Fi. 3 is iven in Fi. 4. Fi. 4. Non ideal equivalent circuit of proposed rounded inductor siulator. where R L A A RZ R X () ( C () CZ CN ) C C C (3) A P X The rounded inductor siulator proposed in [3] as shown in Fi. 5, also eploys sinle VDTA and one rounded capacitor. Fi. 5. Grounded inductor siulator proposed in [3]. Journal of Enineerin Science and Technoloy January 7, Vol. ()

7 New Electronically Tunable Grounded Inductor Siulator Eployin The non non ideal equivalent circuit of rounded inductor siulator proposed in [3] is shown in Fi. 6. where L GI Fi. 6. Non ideal equivalent circuit of rounded inductor siulator proposed in [3]. ( C Cx) RxR (4) ( R R ) x x ( C C ) R R R R ( C C ) R C ' x x (5) x ( C C R C ) R C R ' x x (6) " R R (7) R R ) ( x x x D ( C C ) R R (8) On coparison of Fi. 4 with Fi. 6, it is clear that the effects of parasitics in the proposed circuit are lower as copared to the circuit iven in [3]. Hence, the proposed confiuration exhibits reduced parasitic effects. The proposed inductor can be seen as another version of inductor siulator proposed in [9] fro the viewpoint of two OTA realiation of VDTA. Grounded inductor siulator proposed in [9] eploys two OTAs alon with one rounded capacitor. The input neative terinals of first stae OTA is rounded so full utiliation of OTA is not achieved as an OTA is intended to produce output current for differential input voltae but here at input side only one voltae input is available. Moreover, in both the OTAs only one input is utilied so this work can be done with sinle input/sinle output transconductance eleents which need less nuber of MOS transistors for ipleentation in coparison to MOS transistors required to ipleent circuit iven in [9]. So, all the resources of [9] are not utilied which shows the wastae of resources. In our circuit both the input terinals of VDTA are utilied. The transconductance ains of VDTA are frequency dependent paraeter, which decide the bandwidth liitation of VDTA. The transconductances and of VDTA can be described by sinle pole odel as follows Journal of Enineerin Science and Technoloy January 7, Vol. ()

8 M. Srivastava et al. s (9) s s () s where and are the transconductance ains at ero frequency and and are pole frequencies. Here, τ and τ are delays correspondin to pole frequencies ω and ω respectively. The bandwidth of VDTA can be iproved by insertin a copensation resistor R A, one voltae buffer and MOS transistor pair M 9 and M in VDTA CMOS structure shown in Fi.. The odified CMOS structure is shown in Fi. 7. Transconductance ain for this odified VDTA can be iven as, () R A Fro Eq. () it is clear that of odified VDTA can be chaned by resistance R A. We know that bandwidth of VDTA depends on. Hence, bandwidth can also be controlled by R A. 4. Application exaple Fi. 7. Modified CMOS structure of VDTA. Journal of Enineerin Science and Technoloy January 7, Vol. ()

9 New Electronically Tunable Grounded Inductor Siulator Eployin.... To illustrate the application of proposed rounded inductor siulator it has been eployed in the realiation of a second order band pass filter as shown in Fi. 8. Fi. 8. Voltae ode second order band pass filter realied by proposed rounded inductor siulator. The voltae transfer function of filter shown in Fi. 8 is iven by: V out ( s) V ( s) in s( R C () s s( R C ) ) C C 5. Siulation Result The perforance of the proposed structure has been confired by SPICE siulations with TSMC CMOS.8μ process paraeters with ORCAD 6.3 PSPICE Siulator. The shape factors (W/L) of MOS transistors is iven in Table. Table. Shape factors (W/L) of MOS transistors. Transistor W/L(μ) M 3.6/.36 M 3.6/.36 M3 6.64/.36 M4 6.64/.36 M5 3.6/.36 M6 3.6/.36 M7 6.64/.36 M8 6.64/.36 For Siulations have been perfored usin CMOS VDTA [36] with coponent values: C =.nf, = = = μa/v and power supply ±.9V DC. The anitude response and the phase response of the proposed siulated inductor are shown in Fi. 9 and Fi.. Fro Fi. 9 it is clear that the siulated anitude response of proposed inductor is sae as the ideal anitude response in the Journal of Enineerin Science and Technoloy January 7, Vol. ()

10 Manitude M. Srivastava et al. frequency rane of 84 kh to 3.6 MH. siilarly Fiure indicates that the ideal and siulated phase responses are alost identical in frequency rane of 5. MH to 3.4 MH. the deviation of siulated responses fro ideal responses at low frequencies can be understood by Eq. (7), which shows that under the effects of nonidealities, the proposed circuit works as a rounded series R-L circuit. The lossy ter R is responsible for the deviation of siulated responses fro ideal responses. At hih frequencies the difference between ideal and siulated responses is ainly due to the parasitics of VDTA terinals. On coparin anitude and phase response of our circuit and responses of circuit iven in [3] with ideal response, it is clear that at low frequencies the responses of circuit iven in [3] are a bit better due to non availability of lossy ter in non ideal conditions which is because of leavin P and X- terinal unused in this circuit. The rounded P terinal results in wastae of recourses and the parasitics of floatin X- terinal are not balanced and will consue the power. So, iproved low frequency response of circuit proposed in [3] is at the cost of wastae of recourses and power. At hih frequencies the anitude and phase responses of circuit iven in [3] is hihly deviated fro ideal response due to presence of hih parasitic effects. Our proposed circuit ives better response at hih frequency due to low parasitic effects. So, it is verified that proposed circuit experience less parasitic effects in coparison to the circuit iven in [3]. In proposed rounded inductor siulator, the bias currents I b = I b = I b3 = I b4 = I b for satisfyin the condition =. The electronic control of proposed confiuration is deonstrated by chanin I b fro 5 μa to 8 μa. Fi. shows the anitude responses of input ipedance of proposed rounded inductor at different bias currents I b = 5 μa, 6 μa, 7 μa and 8 μa. To confir the workability of bandpass filter, the circuit was siulated usin the CMOS VDTA [36] with R =.58kΩ, C =.nf, C = 5pF, = = = μa /V with power supply ±.9V DC. The frequency response of this realied bandpass filter is shown in Fi., where central frequency of siulated filter is found to be 4. MH Siulated (Ref 3) Siulated (Proposed) Ideal Frequency(H) Fi. 9. Manitude response. Journal of Enineerin Science and Technoloy January 7, Vol. ()

11 Manitude Phase(de) New Electronically Tunable Grounded Inductor Siulator Eployin Siulated (Ref 3) Siulated (Proposed) Ideal Frequency(H) Fi.. Phase response Frequency (H) x 6 Fi.. Electronic tunability of anitude response of proposed rounded inductor siulator. Ib= 5 ua Ib= 6 ua Ib= 7 ua Ib= 8 ua Fi.. Frequency response of second order voltae ode bandpass filter. Journal of Enineerin Science and Technoloy January 7, Vol. ()

12 4 M. Srivastava et al. 6. Conclusion A new sinle VDTA based rounded inductor siulator circuit has been proposed which offers electronic controllability and reduced parasitic effects. The proposed confiuration requires a realiation condition which can be easily eet by equatin the two bias currents of VDTA. To verify the validity of the proposed rounded inductor, a second order bandpass filter has been realied. The SPICE siulation results confir the theoretical predictions. References. Ford, R.L.; and Girlin, F.E.J. (966). Active filters and oscillators usin siulated inductance. Electronics Letters, (), Prescott, A.J. (966). Loss copensated active yrator usin differential input operational aplifier. Electronics Letters, (7), Orchard, H.J.; and Willson, A.N. (974). New active yrator circuits. Electronics Letters, (3), Dutta Roy, S.C. (975). On operational aplifier siulation of rounded inductance. Archiv fuer Elektronik und Uebertraunstechnik, 9, Senani, R. (978). Active siulation of inductors usin current conveyors. Electronics Letters, 4(5), Nandi, R. (98). Novel insensitive lossless inductor siulation throuh inverse function eneration. Electronics Letters, 6(), Nandi, R. (98). Lossless inductor siulation: novel confiurations usin DVCCS. Electronics Letters, 6(7), Paul, A.N.; and Patranabis, D. (98) Active siulation of rounded inductors usin a sinle current conveyor. IEEE Transactions on Circuits and Systes, 8(), Fabre, A. (99). Gyrator ipleentation fro coercially available transipedance operational aplifiers. Electronics Letters, 8(3), Arslan, E.; Ca, U.; and Cicekolu, O. (3). Novel lossless rounded inductance siulators eployin only a sinle first eneration current conveyor. Frequen; Journal of RF Enineerin and Telecounications. 57(9-), Yuce, E.; Minaei, S.; and Cicekolu, O. (5). A novel rounded inductor realiation usin a iniu nuber of active and passive coponents. ETRI Journal, 7(4), Parveen, T.; and Ahed, M.T. (6). Siulation of ideal rounded tunable inductor and its application in hih quality ultifunctional filter. Microelectronics International Journal, 3(3), Yuce, E.; Minaei, S.; and Cicekolu, O. (6). Liitations of the siulated inductors based on a sinle current conveyor. IEEE Transactions on Circuits and Systes, 53(), Psychalinos, C.; and Spanidou, A. (6). Current aplifier based rounded and floatin inductance siulators. International Journal of Electronics and Counication (AEU), 6, Journal of Enineerin Science and Technoloy January 7, Vol. ()

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