DESIGN OF SECOND ORDER BUTTERWORTH HIGHPASS FILTER USING CMOS TECHNOLOGY

Transcription

1 ISSN (Print ) : ISSN (Online) : DESIGN OF SECOND ORDER BUTTERWORTH HIGHPASS FILTER USING CMOS TECHNOLOGY 11 Anraini Puspita Sari, Aun Darmawansyah, M. Julius St. Abstract The research Complementary Metal-Oxide Semiconductor (CMOS) Technoloy for Desin of second order butterworth hihpass filter IC. This is caused CMOS have excellence low power dissipation and small size. This research aims to know performance, quality and reliability second order butterworth hihpass filter circuit. The method used to problem solvin, analysis with the literature and the simulation use pspice proram for exam the specification of circuit. To make IC picture usin DSCH software and layout circuit usin Microwind proram. From examination result -2,99dB for ain voltae parameter, frequency -40dB and 88,25 phase shift second order hihpass filter. The result of this circuit have low power dissipation althouh applied to second order hihpass filter equal 2,28mW better than enerality IC second order hihpass filter (GH580). Wide of layout circuit is 1110µm x 385µm. Index Terms hihpass filter, butterworth filter, CMOS Technoloy. I I. INTRODUCTION N the recent years, semiconductor technoloy especially interated circuit is the best choice to minimize the dimensions of a device. Considerin the flexibility, low power requirements, and low cost, the incorporation of electronic components such as resistors, capacitors, transistors, diodes and other interated circuit components allows for the creation of flexible and resilient chip desins. The technoloy applied to minimize the size of interated circuit components is microelectronics technoloy. This technoloy is applied to realize the manufacture of small dimensional electronic circuits with consideration of increasin the capability of each component, weiht reduction, strenth of test power and the ability of stability to the environment.[1] [2][3] Durin this time, the evolution of CMOS technoloy more utilized in diital circuit but not so far for analo Araini Puspita Sari, Electrical Enineerin Department of Universitas Merdeka Malan, Malan, Indonesia ( ; anraini.puspita@unmer.ac.id) Aun Darmawansyah, Electrical Enineerin Department of Universitas Brawijaya, Malan, Indonesia ( aun.darmawansyah@ub.ac.id ) M. Julius St., Electrical Enineerin Department of Universitas Brawijaya, Malan, Indonesia ( ; m.julius.st@ub.ac.id ) circuit. So in this research could explore for CMOS technoloy in analo circuit.[4] In the field of analo electronics, filters are often used to reduce noise. One type of filter used is a hihpass filter. The hihpass filter passes all sinal frequencies above the cut-off frequency and weakens all sinals whose frequency is below the cut-off frequency. When desinin a circuit requires a fast desin technique and optimal layout to et the smallest possible size. In this research, we chose the layout of second order Butterworth filter IC usin CMOS technoloy because it has advantaes in low power dissipation and the size is very small. Power dissipation reatly affects workability, reliability, packain, cost and brevity [1]. The type of Butterworth filter is selected to produce a maximal flat response on the passband portion. II. REASERCH METODS In this research will be desined a hihpass filter with CMOS transistor. Fi. 1 shows the second order hihpass filter circuit. Fi. 1 The Second Order Hihpass Filter Circuit The operational amplifier (op-amp) used in this research is a second order op-amp CMOS with low power dissipation. Low power dissipation affects performance, reliability, packain, cost, portability. This op-amp circuit consists of nine CMOS transistors and capacitors. The op-amp used in this research is a second order opamp CMOS with low power dissipation. Low power dissipation affects performance, reliability, packain, cost, portability. This opamp circuit consists of nine CMOS transistors and a capacitor. The calculation of the values of each transistor is enerated from the current analysis. The flowchart of desin IC are shown Fi. 2

2 12 mi Cc = 3. C L m5 Cc = = 5 pf 3 III. Fi. 2 The Flowchart Of Desin IC CALCULATION RESULT OF HIGHPASS BUTTERWORTH FILTER IC Before determinin transistor comparison, the previously determined specifications CMOS operational amplifier second order is as follows: Gain Bandwidth (GB) = 2MHz, I 7= 25μA, V DD=5V, V SS= -5V, λ P = 0,02V -1, λ N= 0,01V -1, V TN= 0,8V, V TP= -0,8V, K N=10μA/V 2, K P= 4μA/V 2, C L= 5pF, V in (maks)= 3,5 V,V in (min)= -2,5V, R in= ~.[2] Fi. 3 shows a second order CMOS amplifier circuitada Fi. 3 Second Order CMOS Amplifier Circuit The desin procedure beins by calculatin the value of the compensation capacitor (Cc). To obtain the comparison of mi and m5 values based on the comparison of frequency amplification values of 3ω0 to obtain a ratio of 1/3. Then determined the minimum value of current I7 = 25 μa. Based on the specification of I7 and the compensation capacitor calculation results obtained slew rate (SR). I 7 = SR. Cc = SR SR = 5 V/ s In desin usin microwind with 0.8 μm CMOS Process. [2][3]Based on the calculations that have been done then the size of all transistors are: L1 = L2 = 0,8 µm W1 = W2 = 15,8.0,8 = 12,6µm L3 =L4 = 0,8 µm W3 = W4 = 2,78.0,8 = 2,2µm L5 = 0,8 µm W5 = 31,3..0,8 = 25µm L6 = 0,8 µm W6 = 18.0,8 = 14,4µm L7 = L8 = 0,8 µm W7 = W8 = 3.0,8 = 2,4µm W9 = 0,8 µm L9 = = 8µm 0.1 The value of power dissipation is: DP = (I 5 + I 7+I 8). (V DD-V SS) = ( ). ( 5 + 5) = 2 mw The calculation of low frequency ain is : 2. m2 m5 Ad 20lo ( ) I ( ) I P N lo , ,03.0,15.10 = 20 lo 6996,38 = 76,9 db The calculation of CMRR is: 2. m2 CMRR 20lo I P N m3 3 I 7 P N 7.1, , ,8.10.1, ,02.0,01.12, lo = 20 lo = 90,5 db In low frequencies, noise is caused by the bias currents and the asymmetry of components. In hih frequencies, the noise is amplified aain by the capacitance contained in the component, theoretically Ap = 1, then: Ad PSRR 20 lo AP = 20 lo 6996,38

3 13 = 76,9 db The value of the output voltae rane can be calculated are : V out(min) = V SS + (V GS6-V T6) = ,3 = -3,7V V out(max) = V DD-(V SG5-V T) = 5-1,5 = 3,5 V. IV. SIMULATION RESULT Second order hihpass IC circuit simulation of differential mode ain confiuration and common mode are shown in Fi. 4. = 79 db Fi. 6 shows a common mode ain raph 400mV 300mV 200mV 100mV Fi. 6 Common Mode Gain Graph Based on the analysis of common mode ain, the ratio between the output voltae at point 5 to the input voltae at point 6 is V so: Ac (db) = 20 lo Vin (A) = 20 lo 0,34403 = - 9,2 db The value of CMRR is: Ad CMRR = 20 lo Ac = Ad (db) Ac (db) = 79 (- 9,2) = 88,2dB The circuitsimulation of PSRR positive (PSRR + ) and PSRR neative (PSRR - ) are shown in Fi.7. Fi 4. Differential Mode Gain Confiuration (A) And Common Mode 10KV (A) 5KV Fi. 5 shows adifferential mode ain raph. The total power dissipation of the second order CMOS amplifier is 2.28 mw. Strenthenin the voltae, the ratio between the output voltae at point 5 to the input voltae at point 6 is V shown in Fi. 5, so: Ad (db) = 20 lo Vin Fi.7 The Circuit Simulation of PSRR + and PSRR - = 20 lo 8985,2

4 V 0.6V 0.4V Fi. 8 The Simulation Result of PSRR + Graph Fi. 8 shows a the result of comparison of the output voltae at point 5 to the V DP voltae at point 10 is V, then: V DP = 20 lo 0, = -5,8 db Ap + (db) = 20 lo So the value of PSRR + is: PSRR + + = Ad (db) A P (db) = 79 (- 5,8) = 84,8 db mV 5V (A) Fi. 10 The Circuit Simulation of SR + and SR mV mV -5V mV Fi. 9 The Simulation Result of PSRR - Graph Fi.9 shows a the result of comparison of the output voltae at point 5 to the V DP voltae at point 11 is mV, then: V DP = 20 lo 0, = -4,8 db Ap - (db) = 20 lo So, the value of PSRR - is: PSRR - = Ad (db) A P - (db) = 79 (-4,8) = 83,8 db The circuit simulation of slew rate positive (SR + ) and slew rate neative (SR - ) are shown in Fi s 5us 10us V(6) Time Fi.11 The Simulation Result of SR + Graph The Simulation Result of SR + Graph are shown Fi.11 andthe value of SR + is: 5V SR + = = Vmaks V min t 4,7493 ( 5) 3, = 3,35 V/μs -5V -1 0s 5us 10us V(7) Time Fi. 12 The Simulation Result of SR - Graph

5 15 Fi. 12 shows a The Simulation Result of SR - Graph and the value of SR - is: Vmaks V min SR - = t = 4,9676 4, , = -3,27 V/μs The second order hihpass filter circuit are shown in Fi d 93d 0d -93d 100Hz 1.0KHz 10KHz 100KHz P() Fi. 16The Graph of Second Order Hihpass Filter Phase At fo = 1kHz Fi.16shows the manitude of the ain (in db), which occurs at fo is db with a phase anle of Fi.17shows the results of hihpass filter IC use Microwind. The IC area is 1110μm x 385μm. 1.2 Fi.13 The Second Order Hihpass Filter Circuit Fi. 17 The Results of Hihpass Filter IC Use Microwind Table 1 shows a Calculation and Simulation Result to Second Order Op-amp CMOS and Table 2 shows a Result of Desin IC and IC GH mHz 1.0Hz 100Hz 10KHz 1.0MHz / V(11) Fi. 14 Graph of Response of Second Order Hihpass Filter at fo = 1kHz Fi. 14 shows a Graph of Response of Second Order Hihpass Filter when fo = 1kHz.Atfo = 1kHz, the voltae ain (A 0) is equal to V. Fi. 15shows athe raph of response frequency hihpass filter (in db) at fo = 1 khz. Pada saat fo = 1 khz penuatan teanan Ao sama denan -2,99dB. 50 Table1.Calculation and Simulation Result to Second Order Op-amp CMOS Calculation Simulation Parameter Results Results Ad 76,9 db 79dB SR 5 V/μs 3,35V/μs CMRR 90,5 db 88,2dB PSRR 76,9 db 84,8dB PD 2 mw 2,28mW V o -3,7 V s/d 3,5 V -5V s/d 4,7542V Table 2.Result of Desin IC and IC GH580 Parameter Desin IC Results GH580 Type Hihpass Hihpass Order Dua Dua Type Butterworth Butterworth PD 2,28mW 25mW PSRR 83,8dB 56dB mHz 1.0Hz 100Hz 10KHz 1.0MHz DB() Fi. 15The Graph of Response Hihpass Filter (in db) at fo = 1 khz

6 16 V. CONCLUTION The conclusion of this research are input sinal iven in hihpass filter circuit above cutoff frequency will be passed while below cutoff frequency will be damped, desin result for CMOS amplifier and second order hihpass filter can be fabricated due to shift of cutoff frequency and voltae ain close to expected that is for frequency cutoff = 1kHz and voltae ain (Ao) = 0.707V or -3dB, the desin excellence IC is havin a small power dissipation value of 2.28mW compared to the second order IC GH580, the results of desin second order hihpass IC use Microwind have IC area is 1110μm x 385μm. REFERENCES [1] Amm Y. Taur, CMOS desin near the limit of scalin, IBM J. Res. & Dev. Vol. 46, No. 2/3, pp , [2] Geier, Randall L., Allen, Phillip E., Strader, Noel R VLSI Desin Techniques For Analo and Diital Circuits. McGraw-Hill. Sinapore. [3] Rashid, Muh Microelectronic Circuits Analysis and Desin. PWS Publishin Company. Boston. [4] Bram Nauta and Anne-Johan Annema. Analo/RF circuit desin techniques for nanometerscale IC technoloies Proceedins of ESSCIRC, Grenoble, France /05.