Sigma-Delta A/D Modulator Design in a Pre-Diffused Digital Array Using the Principle of Trapezoidal Association of Transistors

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1 Sima-Delta A/D Modulator Desin in a Pre-Diffused Diital Array Usin the Principle of Trapezoidal Association of Transistors Jun Hyun Choi and Serio Bampi Federal University of Rio Grande do Sul - UFRGS Institute of Informatics - II Microelectronics Group- GME Av. Bento Gonçalves, Campus do Vale - Bloco IV P.O Porto Alere - RS - Brazil Phone / Fax: / <choi, bampi>@inf.ufrs.br Abstract This paper presents analo semi-custom desin and the advantaes of usin the Trapezoidal Association of Transistors (TAT) for mixed analo-diital system applications on pre-diffused diital arrays, such as the Sea- Of-Transistors (SOT). TAT emulates the behavior of a sinle full-custom transistor, which should have an arbitrary eometry, usin only a composition of reularly and linearly placed minimum-lenth transistors in an array like SOT style. TAT transistor achieves an analo performance that is equivalent to the sinle device. Basic analo buildin blocks were fabricated. Second-order sima-delta modulators for specific applications were also implemented usin TAT on SOT. Simulation and experimental results are for technoloies at 1.0µm and 0.5µm minimum transistor channel lenths. I. Introduction Lately, wireless communication and portable systems are drivin electronic industries to continuously improve their products, merin different portable devices with additional functions on a sinle device at very low cost. The up to date trend is to push research proressively towards VLSI/ULSI technoloies, since the power consumption becomes an essential desin taret because of short battery lifetime. Industries must put forward hiher quality and cheaper products, brinin them fast into competitive markets. In an attempt to prompt VLSI/ULSI interated circuits desin, the pre-diffused semi-custom arrays are larely employed, which are ood alternative to decrease the desin turnaround and prototypin time. The silicon area and speed are often larer than its equivalent full-custom version. The desiners achieve the desin at hih level of abstraction and the remainin steps are automated (positionin and routin), usin pre-defined cells and IP (Intellectual Property) blocks from the pre-defined libraries. The advantaes of diital sinal processin are also well known, however the world is analo and front-end are communication interfaces, between the real world and diital environment are still very much required. These interfaces frequently require basic buildin blocks known as analo cells or systems, which are the main component blocks for the Analo-to-Diital and Diital-to-Analo converters (ADC and DAC). However, available technoloies are not well appropriate for analo applications, and analo technoloies are still costly alternative and mixin analo-diital circuits can be prohibitive. There are a number of performance issues implementin an analo circuit in the environment traditionally dedicated for diital applications. The noise, DC and AC 1

2 performances of MOSFETs are poor compared to bipolar devices. The mixed-sinal analodiital placed side-by-side on same silicon chip causes cross-talks and increased noise levels. Even in the traditional methodoloies, analo desin is not straihtforward. The desin difficulty increases in the diital technoloy environment. It demands better device modelin and new desin techniques. For analo desin, improvements on CAD tools that reflect more accurately the linear and non-linear behavior of the devices, countin also RF behavior and effects are still needed. The mixed-sinal and analo desins in a diital environment are then difficult tasks, as the array is desined to stress the performance requirements of the lare diital blocks, that most likely comprise the overwhelmin majority of the transistors effectively used in the array in a mixed system-on-a-chip desin. It is possible to overcome or improve on these characteristics with a specific discipline for desinin the analo blocks on fixed-size transistors. One important discipline is the use of trapezoidal association of transistors. The unitary transistors on this SOT array were desined in such a way to facilitate miration to down-scaled technoloies takin into account solely the diital circuits demand for speed (usin L min transistors only) and adequate averae diital load drive for local routin. Equivalently, TAT transistor presented in this paper as a cascoded confiuration, that is, a self-cascode amplifier without any extra transistor and bias circuits. Comparisons between TAT and Sinle version are presented for common-source amplifier and folded-cascoded OTA as well as a 2 nd order Sima-Delta desined and fabricated in both methodoloies. II. The TAT Transistor Technique The principle of TAT transistor was demonstrated earlier at the device level by Riccó [3], showin that enlarin the channel width at the drain end of the channel (trapezoidal shape small source, lare drain), shown in Fi. 1a, results in a substantial improvement of the output conductance in saturation mode. Furthermore, Galup-Montoro [2] established that the seriesparallel association of discrete transistors emulates an equivalent sinle transistor. The TAT transistor is the combination of the previous techniques, i. e., a trapezoidal series-parallel association of transistors, shown in Fi. 1b, usin only diital-based pre-diffused transistors. The transistor variable sizes and eometry for electrically equivalent CMOS channel lenths and widths required for analo desin is achieved with appropriate association of the unitary transistors available in a SOT array. Details of this technique are better described in [1], [6]. Consider the series transistors, MD and MS at the drain and source ends, as shown in Fi. 1b, respectively. The equivalent conductance (in linear reion) is iven by an equivalent aspect ratio of the association as [2]: W Eq W = W D W S W D S where (W/L) D and (W/L) S are respectively the aspect ratios of the top parallel assciation MD and the bottom parallel association MS transistors. We can rewrite (2.1) as follows: 2

3 (a) Fiure 1: (a) trapezoidal eometry of a custom MOSFET transistor. (b) Series-parallel association of minimum transistors of the TAT transistor (Self-cascode confiuration). (b) Fiure 2: Simulated V x x V DS curve characteristic of TAT transistor: ND=17, NS=4, L min =0.5µm diital CMOS technoloy. W L Eq = m W m + 1 L S 2.2 with: m W W D =, > 1 S m 2.3 is the ratio between MD and MS transistor aspect ratios. Takin into account the limit of the function in (2.2), from m=1 to m, the TAT transistor aspect ratio will vary between a half of the MS aspect ratio and its physical individual value. Therefore, we must impose an aspect ratio to the MS transistor reater than the required aspect ratio and smaller or equal than twice this value in order to et a trapezoidal association. Reardin aain Fi. 1b, to achieve improvement (decrease) on the output conductance [8], it is indispensable that the channel width of transistor MD be larer than the width of the MS 3

4 transistor, as described in [2] and [3]. In fact, MD is obtained by havin N D unit transistors in parallel and similarly N S unit transistors in parallel for MS, where N S is smaller than N D, in order to keep the principle of trapezoidal eometry. The association of the type shown in Fi. 1 is the basic buildin block for analo desin in a diital SOT array. For eneral application, the upper transistor MD operates in the saturation reion and the intermediate node voltae V x, Fi. 2, is clamped at a fraction of the pinch-off voltae of the source end of the MD channel. This effectively limits de drain voltae of MS to be the channel saturation voltae for a iven V G, which keeps MS in the linear reion. Both transistors MD and MS have the same ate voltae. Hence, they also have the same channel pinch-off voltae [9], [10], therefore for both MD and MS in stron inversion, considerin MD is saturated, V x is iven by: 1 V x = 1. VP N D N S where V P is the pinch-off voltae of the TAT transistor. The expression 2.4 shows clearly the advantae of the TAT to be trapezoidal, i. e., V x approaches to V P. Since the transconductance of TAT is the transconductance of MS transistor (shown later) and MS is in linear reion (onset to saturation), the transconductance is directly proportional to the drain-to-source voltae of MS or V x. The MD and MS are the equivalent transistors obtained by several unit transistors physically laid out in parallel. Therefore, the equivalent threshold voltae is in fact an averain over many unit transistor threshold voltaes. This averain in fact compensates the hiher spread of V T for minimum lenths. Offset voltaes should improve by usin such composite TAT transistors in deep sub-micron circuits. The TAT is trapezoidal and channel lenths are the same for both MD and MS transistors (only the electrically equivalent L eq of TAT is variable). Then, transistor MD is always made wider than transistor MS and its width is not the minimum and the threshold voltae of MS will not be larer than that of MD, iven the body effect present. Additionally the TAT association can be used in several analo low voltae applications because it works as an intrinsic self-cascode circuit, a loosely controlled cascode. Normally, a second ate bias for MD is required for a traditional cascode operation. Improvement, i.e. reduction, on the effective output conductance is effectively achieved for a TAT on SOT array, because a TAT transistor is similar to the traditional cascaded transistors. Then the output conductance is iven by traditional expression: o ds MS ds r ( ) MD o rds r MS ds MD ms 2.5 MD ms MD From 2.5, the output conductance of MD dsmd is represented by a lare value, typical of the worst-case minimum channel lenth transistor, which is effectively reduced by the transconductance of MD. The effective transconductance of TAT transistor is iven by: 4

5 (a) (b) Fiure 3: Experimental output conductance at V G =1V, V G =3V and 5V for TAT and 1.0µm Diital CMOS technoloy: (a) L=5µm, W=30µm, W/L=6 (ND=12, NS=3, unitary W/L=2.5/1.0). (b) L=5µm, W=170µm, W/L=34 (ND=17, NS=4, unitary W/L=10.5/1.0). mtat = dsms msmd mgms ( + ) dsmd msmd + mdms SMD + mdms mg MD MS ( + ) msmd md SMD mg 2.6 MS Accordin to 2.6, the transconductance of TAT is determined mainly by the transconductance of MS transistor. Hence, to improve overall TAT characteristics one needs to increase the MS transconductance and improvement on the effective output conductance one has to increase mainly the output impedance or MD transconductance. Thus, the transistor MD mainly determines the output conductance and transistor MS determines de transconductance of the TAT transistor. In Fi. 3 is plotted the experimental output conductance for TAT transistors with channel lenth L=5µm and two different widths W=170µm and W=30µm compared to the equivalent full-custom sinle transistors. It shows clearly that at stron inversion and saturation reion the output conductance of the TAT is smaller. At hiher ate drive (5V) it is remarkable that the minimum-l TAT transistor achieves a lower ds in saturation reion as the lon channel (L=5µm drawn) lenth devices. At lower ate drive (1V) the short channel effects of V T reduction and Drain Induced Barrier Lowerin (DIBL) combine to ive a larer ds both in conduction and saturation reions. In the saturation reion, the output conductance is about the same with respect to its lon channel equivalent at hiher ate drive. The total equivalent noise power at the input present in the TAT transistor is iven by: V 2 ND ( mg ) MD u 2 [ NS ( )] 2 + V n + fk NS mg MS u ND 2 NS 2 + ( I n u ) ( I n u ) 2 + th MD th [ NS ( )] [ ( )] MS mg MS u NS mg MS u 2 1 n in = TAT u where ND and NS are the number of unitary transistors that set up the MD and MS transistors, respectively, and V 2 u and I 2 u are the flicker noise and thermal noise of each unitary n fk n th 5

6 transistor. Comparin above expression to the equivalent sinle transistor, TAT transistor is noisier. Electrical simulation and experimental results (for the OTAs) have demonstrated that thermal noise is similar, however flicker noise is larer for TAT, which can be minimized increasin the transconductance of MS (or TAT). The same noise analysis can be extended to the circuits and it is shown in next section. III. Basic Analo Circuits Usin TATs Fiure 4: Small sinal model of TAT transistor with body effect. Full-Custom SOT V dd 3V 3V C L 10pF 10pF f max 70MHz 40MHz V os 10mV 18mV P diss I tail 84µA 93µA Table 1: Comparator simulated performance desined in 0.5µm diital CMOS technoloy. The main parasitic capacitances in TAT transistor are the ate-source capacitance from MD transistor (in saturation) and from MS transistor (in conduction) is the ate-source and ate-drain capacitance, shown in Fi. 4. The combination of parasitic capacitances is larer for the TAT than in its equivalent sinle transistor. The presence of one more node in the TAT (poles) increases the total parasitic capacitance seen at the input. Nevertheless, due to the cascode effect the ain bandwidth is similar to the sinle transistor one. Indeed, the product ain-bandwidth is increased by the cascode effect of the TAT. The electrical simulations in Fi. 5 show clearly that for the common-source amplifiers with PMOS current source. The channel lenths, widths and W/L ratios are exactly same values for both TAT and Sinle transistor for better comparison purposes, as indicated in the fiure caption. Fi. 6a shows the total equivalent noise power source at the input of common source amplifiers. It is clearly noted that the flicker noise is almost 5 times larer with TAT transistors. A track-and-latch comparator, shown in Fi. 7a, was desined due to its hiher speed operation. In order to hold and increase output fan-out, the sinal compared and memorized durin samplin time, the comparator must be followed by a latch type D at the output. In Tables 1, the simulated performance reached by the comparator is summarized. The 6

7 technoloy parameters are for HP 0.5µm 3 metal diital CMOS technoloy and were used Smartspice and Hspice electrical simulators with Level 49, which includes noise parameters (1/f and thermal noises). Full-custom SOT A V (db) C L (pf) pF V os (mv) SR C L (pf) PM ( o ) V o max (V) +1.1/ /-0.9 Table 2: OTAs measured performance desined in 1.0µm diital CMOS technoloy. Fiure 5: Gain and Phase marin. HSpice simulation of a common-source amplifier usin TAT (solid) and Sinle (dotted) transistors (W/L) eq =106/1.9 for 0.5µm diital CMOS technoloy. Fiure 6: Total equivalent noise power: (a) HSpice simulation of a common-source amplifier usin TAT (solid) and Sinle (dotted) transistors (W/L) eq =106/1.9 for 0.5µm diital CMOS technoloy. (b) Experimental results from folded-cascode OTA desined in both SOT and full-custom methodoloies for 1.0µm CMOS technoloy. 7

8 (a) (b) Fiure 7: (a) Track-Latch Comparator. (b) Folded-Cascode OTA. (a) Fiure 8: Die photo: OTA on SOT array (left) and same OTA in full-custom (riht). A sinle-ended folded-cascode OTA - Fi. 7b - in both SOT (usin TAT transistors) and full-custom methodoloy [6], [7] were also desined to allow better performance comparisons. In Fi. 8 the die photos of the folded-cascode are shown. In Table 2 the results for electrical simulations and experimental measurements are summarized for both SOT array and full-custom OTAs. The load capacitances were estimated from electrical simulation of expected output current and measured slew-rate. It is worth notin that the SOT with TAT transistors version of OTA has similar (or 1.9X times hiher) ain-bandwidth. It is expected because the TAT transistor is an intrinsic cascode (self-cascode pointed out previously). The offset voltae in the SOT version of OTA is smaller than the full-custom version of OTA due to its better intrinsic layout confiuration, that is, naturally the TAT transistors are very similar to the interdiitated layout technique that is widely used in full-custom layouts. The total noise power spectral densities measured in both OTAs are shown in Fi. 6b. The flicker noise in both are lare due to its dependence on the OTA input differential pair [4], [5]. In this desin, these differential pair eometries are smaller than usual. The thermal noise in the SOT version of OTA is almost similar (slihtly hiher) to its equivalent version in fullcustom, as already predicted previously. An ADC system was fabricated, in 0.5µm diital CMOS technoloy, usin the buildin blocks implemented previously. A fully differential OTA (not shown here) was implemented in order to be compatible to the 2 nd order fully differential Sima-Delta A/D converter (shown in Fi. 9) for a specific applications, i. e., for a multi-standard wireless communications. This converter was fabricated in both full-custom and SOT methodoloies. Testin procedures are under investiations. Pictures of the interated circuits containin A/D system are shown in Fi. 10. (b) 8

9 Fiure 9: Fully differential 2 nd -Order Sima-Delta Modulator architecture. (a) (b) Fiure 10: A 2 nd order Sima-Delta A/D converter fabricated in 0.5µm diital CMOS technoloy: (a) Fullcustom. (b) SOT methodoloy. IV. Conclusion This paper demonstrated that the TAT technique could be used in analo circuit applications without major penalties. One has to deal with the demonstrated noise fiures; it is noisier than the sinle transistor counterpart. However, usin a lare number N D of minimumsize transistors in the TAT, the worse characteristics with respect to noise can be compensated, while keepin the same equivalent W/L. The TAT transistors, as shown herein, are not restricted only for semi-custom arrays. It can be used advantaeously even in fullcustom analo interated circuits, as shown by the sub-circuits and sima-delta converter implemented in SOT usin TAT. Even thouh the total noise is larer and some natural limitations exist, the TAT transistors in SOT methodoloy present ood performance. It is a ood trade-off, for a iven application, between performance and cost and desin time turn around. 9

10 Acknowledements: The support of CAPES and CNPq Brazilian R&D Aencies and of the Analo VLSI Laboratory at OSU is ratefully acknowleded. V. Reference [1] Aita, A.L.; Bampi, S. Desin of Mixed Diital-Analo Circuits on a Diital Sea-of- Transistors, Intl. Symposium on Circuits and Systems, Hon Kon. Proceedins, ISCAS97, 1997, p [2] Galup-Montoro, C.; Schneider, M.C.; Loss, I.J.B. Series-Parallel Association of FET's for Hih Gain and Hih Frequency Applications, IEEE Journal of Solid-State Circuits, v.29, n.9, Sept. 1994, p [3] Riccó, B. Effects of Channel Geometries on FET Output Conductance in Saturation, IEEE Electron Device Letters, vol. EDL-5, Sept. 1984, p [4] Mikoshiba, H. 1/f Noise in n-channel Silicon-Gate MOS transistors, IEEE Transaction Electron Devices, Vol. ED-29, June 1982, p [5] Bertails, J. C. Low-Frequency Noise Considerations for MOS Amplifiers Desin, IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 4, Au. 1979, p [6] Choi, J. H.; Bampi S. Desin of CMOS OTA Amplifiers and Oscillators in a Diital Seaof-Transistors Array. In: 5 th IEEE International Conference on Electronics, Circuits and Systems, ICECS 98. Lisboa, Portual, 9-10/Sept/1998, p [7] Choi, J. H.; Bampi, S. "Trapezoidal Association of Transistors for Mixed Analo-Diital Circuits Desin on a SOT Array". In: IEEE International Workshop on Desin of Mixed- Mode Circuits and Systems, III (Proceedins). Puerto Vallarta, July 1999, p [8] Choi, J. H.; Bampi, S. "Conductances and Noise in Trapezoidal Association of Transistors for Analo Applications Usin a SOT Methodoloy". In: Symposium on Interated Circuits and Systems Desin, XII - SBCCI'99 (Proceedins). Natal, Brazil, Sept. 1999, p [9] ENZ, C. Hih Precision Micropower Desin, Ph.D. thesis, 1989, 198p. [10] ENZ, C. The EKV Model: a MOST Model Dedicated to Low-Current and Low-Voltae Analoue Circuit Desin and Simulation, Low-power HF microelectronics: a unified approach, 1996, p