CMOS Fully Differential Feedforward-Regulated Folded Cascode Amplifier

Transcription

1 MOS Fully Differential Feedforward-Reulated Folded ascode Amplifier Edinei Santin, Michael Fiueiredo, João Goes and Luís B. Oliveira Departamento de Enenharia Electrotécnica / TS UNINOVA Faculdade de iências e Tecnoloia (FT) / Universidade Nova de Lisboa (UNL) aparica Portual {e.santin, l.oliveira}@fct.unl.pt, {mf, j}@uninova.pt Abstract. A fully differential self-biased inverter-based folded cascode amplifier which uses the feedforward-reulated cascode principle is presented. A detailed small-sinal analysis coverin both the differential-mode and the common-mode paths of the amplifier is provided. Based on these theoretical results a desin is iven and transistor level simulations validate the theoretical study and also demonstrate the efficiency and usefulness of the proposed amplifier. Keywords: fully differential amplifiers, feedforward-reulated cascode technique, self-biasin, inverter-based, MOS analo interated circuits. 1 Introduction Amplifiers are essential buildin blocks used frequently to build feedback networks able to perform a variety of accurate functions, e.. multiplication, addition, interation, inversion, etc. The accuracy of these operations is directly dependent on the amplifier s ain-bandwidth product (GBW) performance [1]. Dictated by the down scalin of the diital circuits, the MOS technoloy evolved posin several obstacles to the analo circuits desin in eneral and in particular to the amplifiers desin. Some of these obstacles are low intrinsic ain ( m / ds ) of transistors, reduced supply voltaes, hih variability of devices, etc., which inevitably deteriorate the performance of the well-known amplifier topoloies. To cope with this problem some existin amplifier topoloies have been enhanced and novel topoloies have been proposed, some recent examples are []- [4]. In this paper we propose a fully differential self-biased inverter-based folded cascode amplifier which uses the feedforward-reulated cascode principle firstly presented in [4]. First, the small-sinal behavior of the topoloy is analyzed in detail. After, a desin is outlined and transistor level simulations are presented to demonstrate the efficiency of the proposed new topoloy. Finally, the main conclusions are drawn.

2 558 E. Santin et al. ontribution to Sustainability A new self-biased inverter-based transconductance amplifier topoloy usin feedforwad-reulated cascode devices is presented. The combination of these features allows the topoloy to achieve an attractive fiure of merit (FoM = GBW L /Power), which is comparable or better to those of the best amplifiers up to date. This enhanced bandwidth to power dissipation efficiency is interestin for hih speed and low power applications to be realized in deep-submicron MOS technoloy nodes ( 0.13-µm). 3 Amplifier Description and Analysis 3.1 ircuit Description The circuit of the proposed amplifier without common-mode (M) feedback (MFB) circuitry is shown in Fi. 1. The input stae is composed of transistors M 1, M 4, M a-b, and M 3a-b, where M a-b and M 3a-b are responsible for convertin input voltae variations in incremental drain currents which are then folded to the output cascode devices. These currents are converted to incremental voltaes in nodes v Da-b and v D3a-b, and these voltaes are used to drive cascode transistors M 6a-b and M 7a-b in a feedforward fashion as proposed in [4]. For this reason the topoloy is named feedforward-reulated folded cascode. An interestin advantae of the feedforward-reulated cascode topoloy over the well-known feedback-reulated cascode one is the faster cascode reulation, which leads to a hiher operation speed [4]. The inverter-based inputs of the amplifier effectively double the input m compared to sinle-transistor inputs, which can be used favorably in attainin hih GBW. Fi. 1. Electrical schematic of the proposed amplifier (MFB circuitry not shown). The extra (self) biasin voltaes v MFBN and v MFBP, which are also used to adjust the output M voltae, are obtained from the circuit depicted in Fi.. This circuit performs two functions: 1) it averaes the output voltae obtainin v MFB = (v OP + v ON )/ v MO ; ) in the sequence, it level-shifts this voltae down, resultin in v MFBN, and up, resultin in v MFBP. These voltae level-shifts are needed to bias transistors M 1, M 4, M 5a-b and M 8a-b in the saturation reion without sacrificin considerably the output voltae swin. For example, assumin V DD = 1. V, V SS = 0

3 MOS Fully Differential Feedforward-Reulated Folded ascode Amplifier 559 V, and V MO = 0.6 V, the V DS (drain-source voltae) of the aforesaid transistors should be reater than 0.3 V to saturate these transistors in a technoloy with a V TH 0.3 V (threshold voltae). As a result, 50 % of the rail-to-rail voltae is consumed, which is not desirable. Reardin the averain circuit, the value of the resistors should be sufficiently lare in order not to lower the output impedance, and hence the ain. Unfortunately, lare resistor values mean lare silicon area, and, if this is prohibitive, other MFB circuitry, dependin on the application, can be used (e.., switched-capacitor MFB, differential difference amplifier MFB, etc.). It is important to remark that besides the rail voltaes (V DD and V SS ) no additional biasin voltaes are required, i.e., the amplifier is completely self-biased. This feature precludes the use of an explicit biasin circuit, savin power consumption and silicon area. 3. ircuit Analysis Fi.. Electrical schematic of the MFB circuitry. The small-sinal differential-mode (DM) analysis is carried out with the equivalent half-circuit shown in Fi. 3 (a). Here L represents an output capacitive load. The small-sinal model used for all MOS transistors is illustrated in Fi. 3 (b). M 8 vd M 7 M 3 d d v od v id L M s s mv s mbv bs db ds b sb M 6 vd3 (b) M 5 (a) Fi. 3. Small-sinal DM half-circuit of the amplifier (a) and MOS transistor model (b). By considerin a perfect symmetry, that is, the small-sinal parameters of transistors M, M 5, and M 6 identical to those of M 3, M 8, and M 7, respectively, the followin input-output transfer function results: V V od id ( sd m )( s d 6 ) = (1) s + [ ( ) ( + )] s ( ) d 6 ds

4 560 E. Santin et al. where = m6 mb6, = L + d6 + db6, and eq = d + db + d5 + db5 + s6 + sb6. It is important to mention that, besides the two poles and two zeros present in (1), a pole-zero doublet occurs between the dominant and nondominant poles. With the symmetry assumption, this doublet is perfectly canceled out. If we consider the dominant pole anular frequency ω d much lower than that of the nondominant pole ω nd, expressions for these poles can be derived from (1) as follows [5]: and ( ) ( ds ) ω d = () ( ) ( + ) ( ) ( ds ) ( eq + d 6 ) ω nd =. (3) The low-frequency (D) ain is iven by: d 6 m6 mb6 m A = 1+ + dc. (4) It is important to note that bulk-source transconductances mb of transistors M 6a-b and M 7a-b increase the ain. Therefore, it is recommended not to eliminate the bodyeffect of these transistors, even thouh this is possible in most modern MOS technoloies. Also from (1) we see the transfer function has two riht-half plane zeros. In practice, these zeros are at relatively hih frequencies and can be nelected. The maximum GBW for this amplifier, considerin a phase marin of about 65 o, i.e. the nondominant pole located at a frequency twice the GBW [1], is ω nd /(*π) hertz. We now analyze the small-sinal common-mode behavior. For this purpose, we consider the equivalent circuit shown in Fi. 4, where it is assumed ideal averain circuit as well ideal level shifters. One important requisite for the M path is to have sufficient bandwidth (enerally equal or reater than that of the DM path [6]) and ood phase marin to not deteriorate the DM performance. It is also desirable a moderate D ain to stabilize the output M voltae with some accuracy. By visual inspection, we see that the overall transfer function (V cmo /V cmfb ) of the circuit in Fi. 4 is of fifth order, since it has five sinal nodes, excludin the input. It is now clear why, for simplicity, we made ideal both the averain circuit and the level shifters (otherwise the transfer function would be of seventh order and hardly manaeable). Also, if desirable, the influence of these circuits can be included a posteriori. onsiderin symmetrical devices, i.e., transistors M 1, M, M 5, and M 6 identical to M 4, M 3, M 8, and M 7, respectively, two perfectly matched doublets arise and the system reduces to third order. In this case the transfer function is iven by: V V cmo cmfb ( d 6 m5( ds 1) m1 }, 3 (5) s + [( ) + ( ) ] s + ( s ){ d 5 )( eq 3 s + [( ) d1 + s + 8 d5 ) [ ( + ( d5 ) m5 ] )] s

5 MOS Fully Differential Feedforward-Reulated Folded ascode Amplifier 561 where = ( m mb ), eq = ( mb6 ), = L + 4 db6, eq = ( d + db + d5 + db5 + d6 + sb6 ), and = d1 + db1 + ( s + sb ). This transfer function is approximated because the sum of products terms multiplyin the complex frequency s powers in the denominator are somewhat simplified; however, each term has a simplification error no reater than 1 % for typical parameter values. Fi. 4. Small-sinal M equivalent circuit considerin ideal averain circuit and level shifters. onsiderin a dominant-pole behavior, i.e. the frequency of the first pole much lower than the remainin ones, the dominant pole can be derived from (5) as: 8 = [ ( ) ] ω d, cm. (6) ( eq )( ds 1) ( eq ) Since the nondominant (second) pole is not far away from the third pole, it can not be derived usin an approach similar to that used for the dominant one. Therefore, a different approach [7] is used to approximate this pole (with an error lower than 10 %) resultin in: 8 ω = nd, cm ( 0.045[( 1.6( ds ds 5 ) ) )( eq 3 + ( + ( ) ds 1) ) ]. (7) Similar to the DM path, this nondominant pole will dictate the maximum M GBW for a iven stability (phase marin). Hence, expressions (3) and (7) play a crucial role in the analysis and desin of the proposed amplifier. The M D ain is straihtforward derived from (5) and is iven by: A dc, cm [ ( ) ] m5 m1 =. (8) 4 [ ( ) ] The M transfer function (equation (5)) also has three zeros; however, these zeros are at relatively hih frequencies and can be inored in practice.

6 56 E. Santin et al. 4 Amplifier Desin The accuracy of the feedback networks (settlin error, ain accuracy, bandwidth, etc.) where amplifiers are usually used is directly related with the amplifier s loop ain, which in turn at a particular frequency is a function of the GBW; therefore, the reater the GBW can be desined, the better system performances can be obtained [1]. As a result, in a basic view the desin (sizin) problem of an amplifier is to achieve the maximum GBW possible with the minimum averae power dissipation. In practice, however, other requirements (e.., output swin, input-referred noise, distortion, etc.) have to be considered simultaneously resultin in a very challenin problem. To deal with this complexity and be able to obtain the most efficient solution (sizin), it is a common procedure to use a circuit optimizer. Alternatively to the automated/optimized sizin, a manual and interactive equation-based approach can be followed. In order to come up with a tractable desin problem, only the most important requirements are considered by the desiner and the remainin ones are achieved with some desin rules of thumb, which enerally mean over-sizin the circuit. Althouh this approach enerally precludes the optimum solution, we follow it here to ain more insiht into the amplifier operation and also to validate the usefulness of the relatively simple expressions derived in the analysis section. Throuhout the previous section we conveniently considered symmetrical devices. Unfortunately, the PMOS and NMOS transistors are not symmetrical. At a simplified view, they differ mostly in the effective mobility (in the technoloy used in this work the mobility ratio of the NMOS/PMOS transistors (α np ) is rouhly four times). To compensate this lower PMOS performance, the aspect ratio (W/L) of the PMOS transistors is usually α np times reater than that of the NMOS counterparts. With this constraint, both device types have the same m (for a iven drain current I D ), and this is also ood to improve the noise performance of the amplifier [1]. However, the price to pay for wider PMOS transistors is reater parasitic capacitances. Another important constraint is to use channel lenths two or more times reater than the minimum channel lenth (L min ) allowed by the technoloy. Doin so short-channel phenomena are hihly attenuated, but also the devices are slowed down. Table 1. Active devices sizin and biasin (V OV V GS V TH ). Devices W/L I D V OV V DS/V DSsat m mb ds s d sb db [µm/µm] [µa] [mv] [V/V] [ms] [µs] [µs] [ff] [ff] [ff] [ff] M 1 3/ M a-b 4/ M 3a-b 96/ M 4 18/ M 5a-b 4/ M 6a-b 16/ M 7a-b 64/ M 8a-b 96/ M / M 10 4/ M / M 1 67/

7 MOS Fully Differential Feedforward-Reulated Folded ascode Amplifier 563 Followin the previous constraints and the set of equations derived in the analysis section, the amplifier is sized taretin the hihest GBW while providin a moderate DM D ain (> 55 db) and an averae current consumption of about 1 ma. The sizin result is summarized in Table 1 (the passive elements sizin is: L = 4 pf, a- b = 0.5 pf, and R a-b = 500 kω). It is worth to note that only transistors M 10 and M 1 are not saturated in stron or moderate inversion, and, except for the parasitic capacitances, the transistors small-sinal parameters are approximately symmetrical. 5 Simulation Results In this section some electrical simulations are presented for the amplifier sizin shown in Table 1, which is done in a standard 0.13-µm hih-speed 1. V MOS technoloy (L min = 0.1 µm) from a pure foundry player. Only standard-v TH devices are used. For all simulations a load capacitance of 4 pf is employed. The DM frequency response is depicted in Fi. 5. The amplifier achieves a GBW of 197 MHz with a phase marin of about 83 o, and a D ain of about 55 db while dissipatin 1.1 mw from a 1. V supply. This results in a FoM of 704 MHz pf/mw, which compares favorably with other up to date amplifiers [8]. Fi. 5. Differential-mode frequency response. Fi Vp-p,diff step response (top) and output M voltae settlin (bottom). The step response of the amplifier in unity-ain feedback confiuration for a step of 0. V p-p,diff is shown in Fi. 6 (top), where the settlin final values are clearly

8 564 E. Santin et al. indicated. Also in this fiure is shown the output M voltae settlin, which indicates a ood M behavior. The amplifier settles to within the 0.01 % error band about the final values in less than 7.1 ns (exactly 6.96 ns for the positive step and 7.06 ns for the neative one). 6 onclusions In this work we proposed a fully differential self-biased inverter-based folded cascode amplifier which uses the feedforward-reulated cascode technique. The amplifier achieves a DM GBW of 197 MHz with a capacitive load of 4 pf while dissipatin an averae power of only 1.1 mw from a 1. V supply. onfiured as a unity-ain follower, and with the same load, the amplifier settles to within an error of 0.01 % in less than 7.1 ns for 0. V p-p,diff positive and neative steps. These results show the suitability of the proposed amplifier for hih speed and low power applications desined in standard deep-submicron MOS technoloies. Acknowledments. This work has been supported by the Portuuese Foundation for Science and Technoloy throuh projects SPEED (PTD/EEA-EL/66857/006), LEADER (PTD/EEA-EL/69791/006), IMPAT(PTD/EEA- EL/10141/008) and TARDE (PTD/EEA-EL/65710/006), and Ph.D. rants BD/6568/009 and BD/4154/007. The authors also would like to thank Flávio Gil for his initial contributions and Prof. Adolfo Steier Garção for the many technical discussions which help to deepen the understandin of the proposed amplifier. References 1. Steyaert, M., Sansen, W.: Opamp Desin towards Maximum Gain-Bandwidth. In: Huijsin, J., van der Plassche, R., Sansen, W. (eds.) Analo ircuit Desin: Operational Amplifiers, Analo to Diital onvertors, Analo omputer Aided Desin. The Netherlands: Kluwer Academic Publishers, 1993, pp Assaad, R.S., Silva-Martinez, J.: The Recyclin Folded ascode: A General Enhancement of the Folded ascode Amplifier. IEEE J. Solid-State ircuits, v. 44, pp , Sept Fiueiredo, M., Santin, E., Goes, J., Tavares, R., Evans, G.: Two-Stae Fully-Differential Inverter-based Self-Biased MOS Amplifier with Hih Efficiency. In: Proc. IEEE Int. Symp. ircuits Syst. (ISAS), May 010, pp Zhen, Y., Saavedra,.E.: Feedforward-Reulated ascode OTA for Giahertz Applications. IEEE Trans. ircuits Syst. I, Re. Papers, vol. 55, pp , Dec Razavi, B: Desin of Analo MOS Interated ircuits. New York: McGraw-Hill, 001, pp Sansen, W.: Analo Desin Essentials. The Netherlands: Spriner, 006, pp Palumbo, G., Pennisi, S.: Feedback Amplifiers: Theory and Desin. Dordrecht: Kluwer Academic Publishers, 00, pp Perez, A.P., Nithin Kumar, Y.B., Bonizzoni, E., Maloberti, F.: Slew-Rate and Gain Enhancement in Two Stae Operational Amplifiers. In: Proc. IEEE Int. Symp. ircuits Syst. (ISAS), May 009, pp