A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION. Cui, Ji; Tani, Sadahiro; Ohara, Kenji; Hirai, Yusaku; Matsuoka, Toshimasa

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1 Title Author(s) Citation A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION Cui, Ji; Tani, Sadahiro; Ohara, Kenji; Hirai, Yusaku; Matsuoka, Toshimasa Far East Journal of Electronics and Communications. 14(2) P.105-P.115 Issue Date Text Version publisher URL DOI rihts 2015 Pushpa Publishin House

2 Far East Journal of Electronics and Communications 2015 Pushpa Publishin House, Allahabad, India Published Online: June Volume 14, Number 2, 2015, Paes ISSN: A DYNAMIC LATCHED COMPARATOR WITH BUILT-IN OFFSET CALIBRATION Ji Cui, Sadahiro Tani, Kenji Ohara, Yusaku Hirai and Toshimasa Matsuoka Graduate School of Enineerin Osaka University 2-1 Yamada-oka, Suita-shi Osaka , Japan matsuoka@eei.en.osaka-u.ac.jp Abstract This paper presents a novel dynamic latched comparator that uses a built-in offset-cancellation technique. The proposed offset-cancellation scheme does not require any extra amplifiers or diital-assistant cancellation. Combinin a conventional dynamic latched comparator with a one-stae amplifier benefits from not only an enhancement in comparator ain but also a reduction in power consumption. The Monte-Carlo simulation results, which were derived by usin a 130-nm CMOS process, show that the comparator achieved a 3.8 mv equivalent input-referred offset voltae at a 10 MHz clock rate while dissipatin 2.7 μw from a 1.2V supply. 1. Introduction Comparators are the basic elements used for analo-to-diital converters, memory circuits, and so forth. They can have a sinificant impact on the Received: December 30, 2014; Accepted: February 13, 2015 Keywords and phrases: dynamic latched comparator, offset voltae cancellation. Correspondin author

3 106 J. Cui, S. Tani, K. Ohara, Y. Hirai and T. Matsuoka performance of their taret applications in terms of accuracy, speed, and power consumption. In order to amplify a small input voltae to a fully loic voltae, comparators require very hih ain. For dynamic latched comparators, a hih voltae ain can be more easily achieved by adoptin a positive feedback load. These comparators consume no static power. Therefore, such a comparator is widely utilized. However, dynamic latched comparators suffer from lare input-offset voltaes, which cannot be self eliminated. In conventional processes, a scheme that utilizes pre-amplifiers is used to reduce the offset voltae at the cost of an increase in power dissipation and delay [1]. Moreover, the continuin trend of technoloy scalin leads to a larer mismatch in MOS transistors and a lower voltae supply. As a result, it is difficult to desin a hih-performance pre-amplifier without increasin the power consumption. On the other hand, instead of usin a pre-amplifier, a calibration technique based on a diital-assistant circuit becomes more attractive since it is likely to benefit from technoloy scalin [2, 3]. This technique enerally reduces the offset voltae by feedin back an error sinal durin the output of the comparator. This method is an efficient approach, but increases in complexity and power consumption are inevitable. In this paper, a dynamic latched comparator that utilizes a built-in offsetcancellation technique is proposed. The proposed topoloy of the comparator combines a conventional dynamic latched comparator with a one-stae amplifier, which is embedded in the same current path. Therefore, the comparator does not require any pre-amplifiers or diital-assistant circuits and also benefits from low power consumption. In Section 2, a detailed analysis is carried out to verify the proposed technique for the offset voltae cancellation. The simulations of this analysis are described in Section 3. The conclusions of this study are iven in Section 4.

4 A Dynamic Latched Comparator with Built-in Offset Calibration 107 (a) Circuit confiuration (b) Timin diaram (c) Equivalent circuit in equalization and calibration modes (d) Equivalent circuit in reeneration mode Fiure 1. Proposed dynamic latched comparator. 2. Proposed Dynamic Latched Comparator The circuit confiuration of the proposed comparator is shown in Fiure 1(a), and is mainly comprised of two modified latch staes and capacitors that are used for storin input-offset voltae. The stored offset voltae can be subtracted from the input sinal to determine the offset-cancellation by usin auto-zeroin techniques [4]. The proposed comparator is operated at equalization, calibration, and reeneration modes that are switched by usin

5 108 J. Cui, S. Tani, K. Ohara, Y. Hirai and T. Matsuoka a clock, as shown in Fiure 1(b). The operation of the comparator is described as follows. When the clock sinals φ 1 and φ 2 increase, the comparator operates in the equalization mode illustrated in Fiure 1(c), in which the switch is closed. The objective is to make the voltaes of C1 and C2 equal so that the error resultin from the unbalance of the initial voltae can be compressed as much as possible. When the clock sinal φ 1 decreases and φ 2 remains hih, the comparator operates in the calibration mode illustrated in Fiure 1(c), in which the switch is open. In this mode, the offset voltae resultin from M1-M8 is stored in the capacitors C1 and C2. Additionally, M3-M6 perform as a unity-ain amplifier. Thus, the proposed offset-cancellation technique can be considered to be based on the inputoffset storae [1]. However, when φ 3 increases, the circuit is switched to the reeneration mode shown in Fiure 1(d). The offset voltae enerated by M1-M8 is the same as that caused durin the calibration mode, and they consequently are mutually canceled by the subtraction of the offset voltae from the input sinal. In Fiure 1(d), the M3-M6 transistors serve as a one-stae pre-amplifier as well as a part of the latch stae and are constructed in the current-reused confiuration. Thus, its power consumption is sinificantly lower than the conventional dynamic latched comparator, which utilizes the pre-amplifiers and latch staes separately. The principle operation of the modified latch stae is described as follows. The up arrows and down arrows represent the voltae rises and drops, respectively. Assumin that the initial state of the output is V o + > V o, V o+ tends to increase and V o tends to decrease at the start of operation. This mechanism apparently results from positive feedback. In the latch circuit, the ain of the latch stae can be enerally defined as one-half the loop ain in decibels. For the modified latch stae, the ain of latch A latch is iven by ( ) 3 // 5 = 1 + m A m latch m m + +, (1) o3 o3 o5 o5

6 A Dynamic Latched Comparator with Built-in Offset Calibration 109 where mi and oi are the transconductance and small-sinal drain conductance of Mi, respectively. The above ain expression contains the term m1, which indicates the ain of M1 that operates as a commonsource amplifier, and the term m3 o3 that is attributed to M3, which can be viewed as a common-ate amplifier. Consequently, the ain of the modified latch is sinificantly reinforced compared with a common-source amplifier. The enhancement of ain is expected to improve the voltae transition. Next, the operation of the offset voltae cancellation is explained in detail with a small-sinal analytical expression. It is worth notin that M9 is operated as a current source and it is not taken into account because of its limited effect on the performance of the entire circuit. (a) Calibration mode (b) Reeneration mode Fiure 2. Half small-sinal equivalent circuit of proposed dynamic latched comparator.

7 110 J. Cui, S. Tani, K. Ohara, Y. Hirai and T. Matsuoka In the calibration mode, most of the supply voltae is occupied by M3- M6, since they are operated in a saturation reion. Therefore, the voltaes between the drains and sources of M1-M2 and M7-M8 decrease to smaller values compared to their overdrive voltaes determined by usin the ate voltae V CM. For this reason, M1-M2 and M7-M8 are operated in a linear reion. For simplicity, the drain conductances of M3-M4 and M5-M6 that are operated in the saturation reion are nelected. In this case, the offset voltae oriinates from the mismatch of the threshold voltae V TH and transconductance parameter β (dependin on carrier mobility, ate oxide thickness, and ate width/lenth) of the MOS transistor [5]. To evaluate this, a half equivalent circuit (M2, M4, M6, and M8) that focuses on the deviations from the other half of the circuit (M1, M3, M5, and M7) in the comparator is utilized as illustrated in Fiure 2(a). The deviations of the drain conductance and currents oriinatin from the threshold voltae and transconductance parameter β of the MOS transistors in Fiure 2(a) are calculated as follows: Δβ2 Δβ Δ, 8 o2 = β1δvth, 2 Δo8 = + β7δvth, 8 β, (2) 1 β7 Δβ4 Δβ i, 6 dev, 4 = ID3 m3δvth, 4 idev, 6 = ID5 + m5δvth, 6, (3) β3 β5 where Δβi = βi βi 1, ΔV TH, i = VTH, i VTH, i 1, and I Di are the drain bias current of Mi. By solvin the half circuit shown in Fiure 2(a), the deviation of the output voltae in the calibration mode is iven by ( m4, eff m3) idev, 4 ( m6, eff m5) idev, 6 Δ vo =, (4) + m4, eff m6, eff 3( 1 + Δ 2 ) 3 1 3Δ 2 4, = m o o m o + m o m eff + + Δ + ( + ), (5) m3 o2 m3 1 m3 5( 7 + Δ 8) 5 7 5Δ 8 6, = m o o m o + m o m eff + + Δ + ( + ). (6) m5 o8 m5 1 m5

8 A Dynamic Latched Comparator with Built-in Offset Calibration 111 The input-referred offset voltae corresponds to Δ v o, and is primarily dominated by the mismatches of the channel resistances of M1-M2, M7-M8, and the threshold voltaes of M3-M4 and M5-M6. In the reeneration mode, the comparator amplifies the small input voltae to a detectable loic level. The equivalent input-referred offset voltae Δ vo can be stored with the Gaussian-distributed values located on the ate node of each differential pair in series [6]. To evaluate the outputreferred offset voltae, the differential input voltae is set to zero. It should be noted that the initial output voltaes of the reeneration mode are assumed to be nearly equal to V CM, which is defined as one-half the supply voltae. To evaluate the output-referred offset voltae Δ v o in the reeneration mode, a similar half equivalent circuit (M2, M4, M6 and M8) that focuses on the deviations from the other half circuit (M1, M3, M5 and M7) in the comparator is utilized as illustrated in Fiure 2(b). Owin to the existence of the positive feedback paths, the deviations of the drain currents i dev, 4 and i dev, 6 differ slihtly from those in the calibration mode ( i dev, 4 and i dev, 6 ). By solvin the half circuit shown in Fiure 2(b), the deviation of the output voltae in the reeneration mode is iven as 1 m4, eff ( Δvo + idev, 4 m3) + m6, eff ( Δvo idev, 6 m5) Δ vo = A ( + Δ ) + ( + Δ ). (7) latch m4, eff m1 o2 m6, eff m7 Substitutin Equation (4) into Equation (7) ives the followin: 1 Δ v o = A latch ( m4, eff m3)( idev, 4 idev, 4 ) ( m6, eff m5)( idev, 6 idev, 6 ). (8) ( + Δ ) + ( + Δ ) m4, eff m1 o2 m6, eff If the values of idev, 4 idev, 4 and idev, 6 idev, 6 are small and the value of A latch is lare, Δ v o ets very small. This shows that the offset voltae caused durin the calibration mode can be canceled durin the reeneration mode. m7 o8 o8

9 112 J. Cui, S. Tani, K. Ohara, Y. Hirai and T. Matsuoka 3. Simulation Results The proposed dynamic latched comparator was desined and simulated by usin a 130-nm CMOS process. The ate width and lenth of M1-M4 are 24μm and 0.3μm, and those of M5-M8 are 60μm and 0.3μm. To maintain the current consumption, the ate width and lenth of M9 are 0.16μm and 1μm. All of the switches are CMOS transmission ate with a small size (PMOS ate width: 4μm, NMOS ate width: 1.6μm, ate lenth: 0.12μm) so as to reduce the effect of chare injection. Each of all MOS devices has connection between its source and body with triple-well process to avoid body effect. The capacitors C1 and C2 are 88 ff. In order to verify the usefulness of the proposed offset-cancellation method, a proposed comparator without any input storae capacitors was introduced for comparison. Except for the offset-cancellation function, the performance of the comparator was expected to be identical to the proposed latched comparator. The equivalent input-referred offset voltae was observed by applyin a ramp sinal to the comparator input. Both comparators were operated with a 10MHz clock frequency and 1.2V supply. The results were obtained by carryin out 100 Monte-Carlo transient simulations. Distributions of the equivalent input-referred offset voltae of the comparator without and with calibration are illustrated as historams in Fiures 3(a) and 3(b). For the comparator without the offset-cancellation function, the maximum equivalent input-referred offset extension is up to 134mV at ± 3σ. In contrast, the maximum offset voltae of the proposed comparator is reduced to 3.8mV. It should be noted that larer capacitors C1 and C2 can be beneficial to the offset-cancellation at the cost of a decrease in operatin speed.

10 A Dynamic Latched Comparator with Built-in Offset Calibration 113 (a) (b) Fiure 3. Monte-Carlo simulation results of the equivalent input-referred offset voltae distribution (a) without and (b) with the offset-cancellation function (100 trials). The proposed comparator consumes less than 2.7μW of dynamic power with a clock frequency of 10MHz and a 1.2V supply. In this study, the ratio of period between φ 1, φ2 and φ 3 is set as 1:2:2 approximately. Current dissipation can be scaled down by decreasin the pulse width of φ 2 durin the calibration mode. Furthermore, Table 1 compares the performances of our desin to that of other studies. In practical case, there are some timin variations of φ 1, φ2 and φ 3 throuh clock buffers. Even considerin the clock buffer delay variation for each of CMOS switches, the simulation result shows that the maximum offset voltae of the proposed comparator is only 4.1mV.

11 114 J. Cui, S. Tani, K. Ohara, Y. Hirai and T. Matsuoka Table 1. Performance summary and comparisons 4. Conclusions A low-offset dynamic latched comparator with a built-in offset calibration that does not require extra amplifiers or diital cancellation was proposed. This structure contributes to the compact size of the comparator circuit and lower power consumption. The proposed comparator was verified by usin analytical method and simulation. The simulation results show that the equivalent input-referred offset voltae can be reduced to 3.8mV at ±3 σ when usin a 10MHz clock frequency and 1.2V supply. Acknowledements This work is supported by the VLSI Desin and Education Center (VDEC), University of Tokyo, in collaboration with Cadence Corporation and Mentor Graphics, Inc. In addition, this study is also partially supported by the Japan Society for the Promotion of Science (JSPS) throuh Grants-in- Aid for Scientific Research (B) (# ). References [1] B. Razavi and B. A. Wooley, Desin techniques for hih-speed, hih-resolution comparators, IEEE J. Solid-State Circuits 27(12) (1992), [2] M. Miyahara, Y. Asada, D. Paik and A. Matsuzawa, A low-noise self-calibratin dynamic comparator for hih-speed ADCs, IEEE Asian Solid-State Circuits Conference, Nov. 2008, pp

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