A New Architecture for Rail-to-Rail Input Constant-g m CMOS Operational Transconductance Amplifiers

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1 A New Architecture for Rail-to-Rail Input Constant- m CMOS Operational Transconductance Amplifiers Mohammad M. Ahmadi Electrical Enineerin Dept. Sharif University of Technoloy. Azadi Ave., Tehran, Iran mmahmadi@mehr.sharif.edu Reza otfi Elect. & Comp. En. Dept. University of Tehran North Karar Ave., Tehran, Iran lotfir@ut.ac.ir Mehrdad Sharif-Bakhtiar Electrical Enineerin Dept. Sharif University of Technoloy. Azadi Ave., Tehran, Iran msharif@sharif.edu ABSTRACT A new architecture for constant- m rail-to-rail(r-r) input staes is presented that has less than 5% deviation in m over the entire rane of the input common-mode voltae. Furthermore, a new structure for folded cascode amplifier based on the use of a floatin current source is presented. Employin these techniques a low-power operational transconductance amplifier(ota) with 100MHz unity-ain bandwidth, 106dB ain, 60 phase marin, 2.65V swin, and 6.4nV/ Hz input-referred noise with R-R input common-mode rane is realized in a 0.8µm CMOS technoloy. This amplifier dissipates 10m from a 3V power supply. V MP1 I MP2 Current Summation V Cateories and Subject Descriptors Interated circuits General Terms Desin MN1 MN2 I Keywords Rail-to-rail, transconductance, current summation, floatin current source, input stae, operational transconductance amplifier. 1. INTRODUCTION Operational amplifier is one of the most widely used functional blocks for hih-level analo and mixed-sinal interated circuit desin. One desin issue of many circuits or systems is that their overall achievable performance directly depends on the used op amps. Hih-speed operational transconductance amplifiers with R-R input common-mode rane have a wide rane of applications in hih-speed continuous-time filters and equalizers where the OTA-C architecture is sometimes the only candidate. At lare supply voltaes, there is a trade off amon speed, ain and power of an operational amplifier. Sinal swin becomes yet another performance metric to be considered when desinin operational amplifiers at low supply voltaes [1]. Permission to make diital or hard copies of all or part of this work for personal or classroom use is ranted without fee provided that copies are not made or distributed for profit or commercial advantae and that copies bear this notice and the full citation on the first pae. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ISPED 03, Auust 25 27, 2003, Seoul, Korea. Copyriht 2003 ACM X/03/ $5.00. Fiure 1. A simple rail-to-rail input stae For desinin hih swin op amps in low supply voltaes, output swin is not usually a problem because a class-a or class-ab output stae or even a folded cascode architecture can drive loads close to power supply voltae. However, opamps with hih-swin input staes are still challenin to desin. To have a R-R input common-mode rane, two complementary differential pairs are required to form the input stae (Fiure 1) [2]. However, this circuit suffers from some drawbacks. The total input transconductance, mt, is iven by the sum of the transconductances of the NMOS and PMOS differential pairs. At the extreme input voltae ranes, only one input pair is active, so the effective transconductance is halved. Therefore, the deviations in mt as a function of input common mode voltae, V CM, can be as much as 100%. This is not desirable because it complicates the frequency compensation and also results in harmonic distortion [3]. Furthermore, at lare sinal reime, the lare sinal output current is also halved at the extreme input ranes. This means that the slew rate of a conventional sinle-stae or two-stae amplifier with this input stae will be a function of V CM. imitations of Fiure 1 were incentive for analo desiners to innovate input stae topoloies that have constant input transconductance over the whole rane of V CM [3-7]. Additionally, because of some other limitations, usin these input staes in sinle stae amplifiers does not result in ood performance with respect to power dissipation. Indeed, almost all of the R-R constant- m operational amplifiers have been realized in two or three stae con- 353

2 fiurations, which this limits the bandwidth and speed of amplifier. In this paper, in Section 2, we present a new R-R constant- m input stae that has superior performance compared to the other confiurations. Besides, a new architecture for current summation circuit based on the use of a floatin current source is presented in Section 3. By the use of these new architectures, a low-power sinle-stae operational transconductance amplifier with R-R input common-mode rane and almost constant- m capability is proposed. In Section 4, simulation results are presented to illustrate the effectiveness of the approaches, and Section 5 is the conclusion. I P1 =I Current Summation I P2 =I MP5 I P3 = I + I MP6 MP1 MP2 MP3 MP4 2. INPUT STAGE ARCHITECTURE A popular approach for desinin constant- m R-R input staes is to sense that one of the input pairs has lost needed ate bias for proper operation, takes away the unused tail current of that pair throuh a bypass transistor, amplify it by a factor of 3 with a current mirror and add it to the tail current of the active pair [5]. In spite of the simplicity of this approach, it has several shortcomins. The main drawback of this method becomes important in submicron processes in which square law equation in an MOS transistor is no loner valid. Amplification of tail current by 3 and addition of this to the tail current of active pair is not ood enouh to realize R-R input staes, as in submicron CMOS processes, short channel effects mean that the factor 3 should be 5 or 6, depends on the technoloy. As a result, at the extreme input voltae ranes, the power consumption becomes considerably hih. Furthermore, this makes the desin of current summation (folded cascode) circuit difficult. There are some structures [6-7] which their operation are not based on MOS squre law equation, however, their input transconductance are subject to lare variations. The operation of the novel architecture presented here is not also based on the MOS square law equation. Besides, it maintains a nearly constant m in the whole rane of V CM and shows superior performance copared with other structures. The principle of this new technique is to activate another pair similar to the active pair when one pair has lost required ate bias for proper operation. As a result, at extreme supply voltae ranes that one of input pairs turns off, two similar pairs of other polarity enerate sinal current in parallel, and so the input transconductance doubles. To implement this approach, as it is shown in Fiure 2, three differential pairs of each polarity are used. All the PMOS differential pairs have equal / and all the NMOS differential pair transistors are also identical. hen V CM is at the midway of supply voltaes, amonst the NMOS transistors, MN1 and MN2 enerate sinal current, and amon the PMOS transistors, the pair MP1-MP2 does this work. In this reion of operation, the current of the source I N3 flows throuh transistors MN5 and MN6 and sinks all the tail current of the pair MP3-MP4, and switches off this pair. On the other side, the current of the source I P3 flows throuh transistors MP5 and MP6 and supplies all the tail current of the pair MN3-MP4, and also this pair switches off. Hence, only four devices MN1, MN2, MN1 MN2 MN3 MN4 I N1 =I I N2 =I MN5 MN6 I N3 = I + I Fiure 2. New constant- m rail to rail input stae MP1, and MP2 are eneratin sinal current and mt is equal to the sum of input NMOS transistor transconductance, mn, and input PMOS transistor transconductance, mp. If the sizes of the PMOS and NMOS transistors are chosen such that mn = mp = m, then mt is equal to 2 m. There is also a total current of 2I available for the current summer when the circuit is in slew-limited reime. hen V CM is near, none of the PMOS transistors have sufficient V GS to remain active. Since there are no other path for tail current sources I P1 and I P3, these current sources are deactivated. Therefore, the tail current source I N2 is not supplied from anywhere and flows throuh the pair MN3-MN4. So this pair turns on and works in parallel with the main pair MN1-MN2. As a result, mt is equal to 2 mn which is equal to 2 m. There is also a total current of 2I available in the limitin situation. At the other extreme point of V CM, similarly, I N3 is pushed to be off and I P2 flows throuh MP3 and MP4. So the equivalent transconductance is 2 mp. There is also a total current of 2I available in the slew-limited reime. If because of transistor mismatches, the current value of I N2 and I P2 becomes slihtly hiher than I, or the current value of current sources, I N3 and I P3, becomes slihtly lower than I, the pairs MN3- MN4 and MP3-MP4 will turn on when V CM is in the midway of supply voltaes. This undesired activation of pairs MN3-MN4 and MP3-MP4 increases mt and enhances the mt deviations of input stae. By adjustin the current of current sources I P3 and I N3 slihtly hiher than I, i.e. I+ I, above problem will be eliminated. In this new circuit, by handlin the / and V GS of the transistors of the tail current sources, the mt deviation can be more reduced. The principle of decreasin the mt deviation is shown in Fiure 3. The solid and the dotted lines are the mt and its components before and after the improvement, respectively. The overhans in the mt curve are because of the lare slope in the m of differential pairs in turnin on and off intervals. As it is shown in 354

3 the Fiure 3, if the slopes of the curves are decreased, the mt curve becomes smoother. For example when the pair MN3-MN4 is turnin on, the other pair, MP1-MP2, is turnin off. If the slopes of m when these pairs are turnin on and off are constant and equal, by addin the two curves the mt will be constant, but the curve of m in the zone that the pairs are turnin on or off is similar to a parabola. As it is shown in Fiure 3, by decreasin the slope of the curves, the deviation in mt will be reduced more. To decrease this slope, i.e. the slope of the m -V CM curve of a differential pair when turnin on, the effective voltae, V DS,sat, of the tail current source transistor should be increased. That is, the effective voltaes of the transistors which realize the current sources I N1 and I P1 should be increased. This can be done simply by reducin their / and increasin their V GS. By cascodin the tail current sources I N2, I N3, I P2, and I P3, the deviations in mt reduce more. ith this topoloy, the mt deviations could be less than 5%. The simulated result of the m of the new input stae is shown in Fiure CURRENT SUMMATION CIRCUIT Another important block in an OTA with R-R input commonmode rane is the current summin circuit. The conventional approach for realizin this circuit is shown in Fiure 5. However, when this circuit is used in sinle-stae amplifiers, some problems are caused in frequency compensation of the amplifier. These problems can be addressed as follows: Reardin the Fiure 5, The bias current of and, I B, must be able to supply the current of NMOS input device, I N, and bias current of -,. The current of the input NMOS stae, can vary from zero for minimum values of V CM to more than 2I n for values close to the positive rail; where I n is the current of the NMOS input stae for mid-rane values of V CM. As a result, the bias current of transistors and must be able to supply these increments in the quiescent current of the NMOS input and also the minimum quiescent current for the transistors of the current summation circuit. mt before improvement Fiure 4. mt and its components versus V CM, (a) mt, (b) mn1,2, (c) mp1,2, (d) mn3,4, (e) mp3,4. Note that, when V CM is in the midway of supply voltaes or close to the neative supply rail, the additional bias current of and flows throuh transistors -, and considerably chanes their quiescent current and therefore their transconductance and output resistance. These variations lead to lare variations in pole-zero locations and also the low-frequency ain of the amplifier. These lare variations in pole-zero locations complicate the frequency compensation and prevent the optimum usae of power in order to enhance the bandwidth. Here we can have a lance on the on the pole-zero location and ain of this amplifier. The poles and zeros of this opamp with reference to Fiure 5 are located at: 1 m4 m6 P1 = P2 = P3 = C out R out CX CY m5 4 m7 CY P4,5 = 1 ± 1 2C Y m5c M m4 m6 ( mn + mp ) m5 8 m7cy Z1 = Z 2,3 = 1 ± 1 mn m4cy + mp m6c X 2CY m5cm Input Transconductance, mt mp3,4 mn1,2 Vtn mt after improvement Input Common Mode Voltae,V CM mn3,4 mp1,2 Vdd- Vtp Fiure 3. The principle of reducin the mt deviations in new R-R input stae. where C X, C Y, C M and C OUT denote the total parasitic capacitances at nodes X, Y, M and OUT respectively. mi, mn and mp denote the transconductances of transistor Mi, the NMOS input stae and the PMOS input stae, respectively, and R out is the output resistance of the amplifier obtained from: R OUT = ( m ro 4( ro 2 ron )) ( m6ro 6( ro 8 r 4 OP where r oi is the output resistance of transistor Mi. As it is obvious in above equations, any variations in the bias current of transistors considerably chane the low-frequency ain as well as the frequency response of the amplifier. These variations in the bias current of the current summation transistors are not very important in two- or multi-stae amplifiers that use R-R input stae. This is mainly due to the fact that in twoor multi-stae amplifiers the voltae swin in the output node of the first stae is not restrictive. Consequently, the aspect ratio of the output transistors of the first stae should not be hih and the )) 355

4 I B V bias1 I B I N I N X NMOS Input V bias2 NMOS Input V bias2 V OUT V OUT PMOS Input M V bias3 IP Y PMOS Input V bias3 I P I M I M Fiure 5. Conventional method for biasin current summation circuit. parasitic capacitances in nodes X, Y, and M are neliible. So the poles due to these nodes are located at hih enouh frequencies to nelect the effects of their variations. Indeed, in these amplifiers the bandwidth of the amplifier is restricted to the poles of the second or other staes, which inherently are in lower frequencies. However, when desinin hih swin sinle stae amplifiers, the voltae swin in the output node of the current summation circuit which is the output node of the amplifier should be hih enouh. Hence, the aspect ratio of the devices - and therefore the parasitic capacitances at nodes X and Y are increased and the small-sinal parameters of these devices affect the frequency response of the amplifier considerably. For optimizin NMOS Input PMOS Input 2 I n1 2 I n2 I 1 I 2 V V V OUT Fiure 6. A simple approach for biasin current summation circuit. Fiure 7. Usin a floatin current source for biasin the current summation circuit. the power consumption of the opamp, the variations in the polezero locations due to the variations in the bias current, should be minimized to the possible extent. By a detail analysis, it is clear that the location of poles, P 2, P 3, P 4,5 and zeros, Z 1, Z 2,3 is directly related to the transconductance of transistors -. In fact, the transconductance and output resistance of these transistors have the most important role in the ain and pole-zero locations of the amplifier. Therefore, stabilizin the quiescent current of these transistors helps so much in optimizin the frequency compensation and reducin the harmonic distortion of the amplifier. For this reason, both NMOS and PMOS cascoded transistors are used as current mirrors. Note that the current value of the current mirror chanes automatically by the chanes in the input differential pair currents. The remainin problem is biasin the current summation circuit. The first approach is the use of two independent current sources as depicted in Fiure 6. A drawback of this approach is that the bias current sources of the current mirrors contribute to the noise of the amplifier because the current ain between the current sources and the drain currents of the input transistors is equal to one. Besides, Any mismatches in the bias current sources will also increase the offset of amplifier [5]. By usin a floatin current source between the drain of transistors and, as shown in Fiure 7, the mentioned problems are alleviated considerably. Besides, the bias current of transistors - becomes nearly constant. The circuit realization of floatin current source with complete diaram of the entire amplifier is shown in Fiure 8. The value of this floatin current source is determined by the MOS translinear loops, M9, 2, 1 and, 0, 3, 4. The use of floatin current source has been used for the desin of class AB amplifiers previously [5-6], however, in this paper, it has been employed to bias the current summation circuit. 356

5 Gain boostin has been also employed to ensure enouh ain for the amplifier. Indeed, by two auxiliary folded cascode amplifiers, the output resistance of the amplifier increases extremely without deradation of frequency response [8]. However, in desinin those auxiliary amplifiers, some precautions should be met to prevent slowin down the transient response. The main parameter in desinin the auxiliary amplifiers is their unity-ain bandwidth that should be about half of the frequency of the foldin poles. That is, the unity-ain bandwidth of the auxiliary amplifiers X and Y should be chosen about half of the frequency of the poles P 2 and P 3, respectively [9]. 4. AMPIFIER SPECIFICATIONS The proposed sinle-stae amplifier with constant- m R-R input stae has been implemented in a 0.8 µm double-poly, doublemetal CMOS technoloy It occupies a die area of 500*400(µm) 2 and consumes a total power of 10m from a 3-V supply. The m of the input stae as shown in Fiure 4 has a deviation of less than 5% over the entire R-R rane of the input common-mode voltae. Fiure 9 shows the simulated frequency response of the operational amplifier with a 5pF capacitive load. It shows that the unity-ain frequency is about 100 MHz. The variations of the unity ain bandwidth and phase marin versus V CM are shown in Fiures 10 and 11, respectively. Fiure 12 shows the step response of the amplifier in unity ain feedback confiuration. The 0.1% and 0.01% settlin times of the amplifier are 15ns and 30ns, respectively. Besides, the slew rate of the amplifier is 150 V/µS, the output swin is 2.65V and input referred noise is 6.4nV/ Hz. The amplifier characteristics are summarized in Table 1. Table 1. Amplifier characteristics(post-layout simulation) with a 3-V Supply voltae and 5pF capacitive load. PARAMETER VAUE Gain (db) 102 GB (MHz) 100 Phase Marin(de) 60 Settlin Time 0.1(nS) 15 Settlin Time 0.01(nS) 30 Slew Rate (V/µS) 150 Swin (V) KHz (db) 121 Input noise voltae (nv/ Hz) 6.4 m variation(%) 5 Power dissipation (m) 10 Fi. 10. ayout of the amplifier. MSP2 MSP3 8 4 MX9 MX10 MSP1 MSP4 MSP5 7 3 X MX5 MX4 MP1 MP2 MP3 MP4 MP5 MP6 X OUT- X MX7 MX1 MXB MXS2 MX2 X X OUT+ MX6 MX9 MXS1 MX8 M9 0 OUT MY7 MYS1 MY8 MN1 MN2 MN3 MN4 MN5 MN6 MSN1 MSN4 MSN4 1 5 Y MY5 MYS2 MY6 Y OUT- MY1 MYB MY2 Y Y Y OUT+ MY4 MY3 MSN2 Msn3 2 6 MY9 MY10 Fiure 8. Complete schematic of the amplifier: the floatin current source is realized by transistors M9 to 8. There are two ainboostin amps, X and Y. The circuit realizations of the amplifiers X and Y are shown in riht hand of the fiure

6 Fiure 9. Frequency response of the desined amp. Fiure 11. Phase marin deviations with respect to V CM Fiure 10. Unity-ain bandwidth deviations with respect to V CM 5. CONCUSION In this paper, a new architecture for R-R constant- m input staes is presented, which not only its operation is not based on the MOS square law equation, but also has superior performance compared with other ones. Additionally, based on the use of a floatin current source, a new architecture is presented for desinin sinle-stae operational transconductance amplifiers. This floatin current source biases the output transistors of the amplifier with minimum chanes in the polezero location of the amplifier. Employin these new architectures, a low power, hih swin, hih speed, and hih ain sinle-stae operational transconductance amplifier is desined and implemented in a 0.8µm double poly double metal CMOS process which consumes less than 10m from a 3-V supply 6. REFERENCES [1]. K. Gulati and H.-S. ee, A Hih-Swin CMOS Telescopic Operational Amplifier, IEEE J. of Solid-State Circuits, Vol. 33, NO. 12, Dec. 1998, PP: [2]. Huijsin, J.H.; Hoervorst, R.; de anen, K. -J. owpower low-voltae VSI operational amplifier cells IEEE Trans. Circuits Syst. II, Vol. 42, NO. 11, PP: , [3]. S. Sakurai and M. Ismail, Robust Desin of Rail-to-Rail CMOS Operational Amplifiers for a ow Power Supply Fiure 12. Small sinal step response of the desined amp Voltae, IEEE J. of Solid-State Circuits, Vol. 31, NO. 2, Feb. 1996, PP: [4]. Marc Ryat, Rail to rail operational transconductance amplifier, U.S. Patent , May [5]. R. Hoervorst et. al., A Compact Power-Efficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VSI Cell ibraries, IEEE J. of Solid-State Circuits, Vol. 29, NO. 12, Dec. 1994, PP: [6]. R. Hoervorst, S.M. Safai, J.P. Tero, and J.H. Huijsin, a prorammable 3-V CMOS rail-to-opamp with ain boostin for drivin heavy resistive loads, ISCAS 95, Vol. 2, 1995, PP: [7]. illiam Redman-hite, A Hih Bandwidth Constant m and Slew-Rate Rail-to-Rail CMOS Input Circuit and its Application to Analo Cells for ow Voltae VSI Systems, IEEE J. of Solid-State Circuits, Vol. 32, NO. 5, MAY 1997, PP: [8]. K. Bult and G. J. G. M. Geelen, A Fast-Settlin CMOS Op Amp for SC Circuits with 90-dB DC Gain, IEEE J. of Solid-State Circuits, Vol. 25, NO. 6, Dec. 1990, PP: [9]. Mohammad M. Ahmadi, Desin and Fabrication of a Hih Performance Operational Amplifer, Master Thesis, Sharif University of Technoloy, September