Low Power Amplifier Design Using CMOS Active Inductor

Transcription

1 Proceedins of the 5th WSEAS International Conference on Sinal Processin, Istanbul, Turkey, May 7-9, 006 (pp ) Low Power Amplifier Desin Usin CMOS Active Inductor MING-JEUI WU, PEI-JEN YEN, CHING-CHUAN CHOU, JENN-TZER YANG Department of Electronics Enineerin Min Hsin University of Science and Technoloy 1. Hsin-Hsin Rd., Hsin-Fon, Hsin-Chu 04 Taiwan Abstract: - In this paper, a CMOS low power amplifier based on a hih-quality active inductor and implemented by usin 0.5-µm 1P5M CMOS standard technoloy is presented. The amplifier achieves power ain (S1) of 18dB within the -db cutoff frequency, bandwidth of 1.GHz, and power consumption of 18mW under.5v power supply in µm silicon area. The input third-order intercept point (IIP) and the noise fiure (NF) are -1dBm and 10dB, respectively. Key-Words: - Amplifier, Bandwidth, S-parameter, Noise Fiure, and Power Consumption. 1 Introduction There are many applications usin hiher frequency circuits for the past two decades. These applications include TV cable modem, multi-band mobile communication, wireless communication systems, instrumentation, and optical communication. The traditional hih frequency circuits were implemented usin hih speed GaAs MESFETs and MMIC technoloies [1]-[4]. However, the producin costs of such devices are hiher than that of the CMOS devices available today. Moreover, the comin advancement in state-of-the-art electronic systems and future system-on-chip solutions will comprise the diital, the analo and the hih frequency circuits with a hue demand for low-cost, hih-speed, and mixed-sinal interated systems. It is essential that hih frequency circuits can be implemented in low-cost CMOS technoloy. Recently, there are considerable efforts workin on the miration of the hih frequency elementary circuit blocks from GaAs to CMOS process [5-8]. Unfortunately, such circuit miration has not been able to achieve directly. One major obstacle of the miration is that it is difficult to implement hih frequency circuits in CMOS because of the deleterious substrate couplin effects. The hihly doped substrate causes substantial losses especially when on-chip passive spiral inductors operate above GHz frequency durin CMOS manufacturin process. Most of the previous reports in CMOS hih frequency circuits were implemented by usin on-chip passive spiral inductors to achieve better matchin, hiher wide bandwidth, hiher power ain, and lower power consumption [9-14]. However, the low quality-factors of an on-chip passive spiral inductor cause the deradin of the ain/bandwidth performance and larer power consumption. Furthermore, obtainin a hih quality factor of spiral inductor often requires additional processin steps to compensate the quality factor and these additional processin steps also require extra cost [15-16]; moreover the inductance value is dependent on the size of the inductor [17]. The die area of an interated passive inductor is usually larer than other components. An alternative method called active inductor is to use the CMOS active devices as an inductor, where the equivalent inductive impedance can be implemented. The above difficulties can be overcome by usin an active inductor. The active inductor is an alternative technique, which is implemented by usin circuit confiurations, called yrator. The quality-factor and the inductance value obtained by this active technique are hih enouh to overcome the value exhibited by conventional spiral inductors. Dependin on the chosen topoloy, the loss of an active inductor caused by the active devices can be reatly reduced and the area of an active inductor is totally independent of the desired inductance values [18-1]. Most of the active inductor circuits were applied in low noise amplifiers, band-pass filters, and voltae control oscillator and they produced impressive results [-6]. Althouh, the active inductor approach has not been applied on the low power amplifiers with wider bandwidth and the smaller die area, it is possible that we can apply the characteristics of

2 Proceedins of the 5th WSEAS International Conference on Sinal Processin, Istanbul, Turkey, May 7-9, 006 (pp ) hih-quality factor, amplifier confiuration, and neative feedback topoloy of a hih-quality active inductor on the amplifier desin of lower power consumption, wider bandwidth, and smaller die area. A simple rounded active inductor confiuration is a very popular inductor, where two transconductors are connected in back-to-back confiuration [7]. However, the non-desirable characteristics of active devices amon drain, source of MOSFET and DC bias circuits will limit the performance of the active inductor circuits such as the Q-value and the operatin frequency [8]. These limitations derade the performance of application circuits usin active inductors. In this paper, a CMOS amplifier circuit based on a hih-quality active inductor is presented in section. In section, the measurin characteristics of the implemented amplifier usin 0.5-µm CMOS technoloy is introduced. Finally, the conclusion is summarized in section 4. Output buffer stae is desined as common-drain stae, which comprises transistors M B and R B. This common-drain confiuration minimizes the loadin effect and provides a simple output impedance matchin. Therefore, the overall ain of the amplifier can be expressed as Eq. (). Circuit Desin The prototype of the inductor-less low power amplifier circuit based on the proposed hih-quality active inductor is shown in Fi. 1. This circuit consists of three different staes, includin common ate confiuration, hih-quality active inductive load and buffer stae. Transistors M S1 and M S comprise the input common ate amplifier stae. This common-ate confiuration provides low input impedance, expressed in Eq. (1), and achieves a simple input matchin, and hiher linearity without source deeneration inductor. This common-ate approach also helps to increase the effective reverse isolation. Z in // // (1) ms dss1 dss ms A hih-quality active inductor is constructed by transistors M 1 ~M, M P, resistance R G, and capacitance C N. The hih-quality active inductor is employed to fulfill the load of the common-ate amplifier. Hih-quality active inductive load is applied mainly for three reasons. Firstly, the hih quality-factor active inductive load consumes less die area than on-chip passive spiral inductor does; secondly, the amplifier can obtain hiher power ain, and requires less dc bias current. Thus, the power consumption of the amplifier can be saved. Finally, the architecture of the active inductor has the topoloy of the neative feedback; hence it can improve the frequency response of the amplifier. Fi. 1 Proposed amplifier circuit m1 m m A voverall, A vcg,.. [( + mp + ds1 ) + sc s1 + ( sc s + ds1 ds ) scs( scd1+ m ) 1 mm 1 / + m + sc N 1 C N mm 1 mm 1 m ) ] ( ) ( 1 ) A, sc C sc 1 s sc d m v bufer m + + () N d d s+ C d1 ds1 where A v,c.g and G m,c.g. are the voltae ain and the transconductance of the common-ate amplifier, respectively. Z load, active_inductor is the equivalent input impedance of the hih-quality active inductor. A v,buffer is the ain of the buffer stae. In Eq. (), the quality-factor improvement of the active inductive load will improve the performance of the amplifier such as die area, power consumption, and bandwidth. Furthermore, this characteristic of the amplifier is sensitive to the parasitic components and the followin stae loadin. Tunin the external biases of V S1, V S, V G and V P can modify these effects of the overall circuit response. Therefore, it is easy to tune the variation because of the process or other factors. Capacitors C B1 and C B are used as a DC blockin capacitor of the input and output to isolate DC voltae of the previous stae and the followin stae. Measurement Results All transistors in this amplifier have the same

3 Proceedins of the 5th WSEAS International Conference on Sinal Processin, Istanbul, Turkey, May 7-9, 006 (pp ) dimensions. The minimum lenth and width are 0.4um and 40um. Resistance R G, and R B are 750Ω and 10Ω respectively and capacitance C N is 0.7PF. The biasin values are V S1 =V S =1V, V G =1.7V, V P =1.4V and the normal supply voltae is.5v. Fi. shows the die photo with a die area of µm and the bondin pads are not included. The die area is much less than the one usin the on-chip passive spiral inductor. Note that the dc power supplies separatin the RF input and output pad is for reducin mutual couplin. In order to measure the circuit, a PCB board is built. All dc bias pads are bonded with PCB board. The RF input/output pads are measured directly throuh probe station. by the external DC blockin capacitor and the effects between the probe and the connector of network analyzer are calibrated into the network analyzer in which it only considers the internal characteristics of the amplifier. Fi. shows the power ain (S1) of this CMOS amplifier. The amplifier demonstrates the flat power ain of 18dB and 0 to 1. GHz bandwidth in the db cutoff frequency. The total dc power consumption is only 18 mw under.5v dc power supply. Unlike the passive inductor where the dampin resistor is the main noise producer, the noise in active inductor oriinates from the thermal noise and the flick noise of MOS transistor channel while the dampin resistor is a fictitious one without any noise contribution. In this amplifier s desin shown in Fi. 1, the first stae is a common-ate confiuration, and the load of the common-ate amplifier is a hih-quality active inductor. The final stae is a common-drain confiuration. To have a fully understand of noise characteristic of amplifier, the noise analysis of active inductors is therefore important. Eq. () derived the noise factor of the hih-quality active inductor and is show in Fi. 1. R NF () G m 1 ( ) CN m m 1 m 1 Generally, the noise effects in a common-ate topoloy include the thermal noise and the flick noise. Thus, the noise factor of the common-ate amplifier can be expressed as Eq. (4). Fi. Microraph of the proposed amplifier K NF [ + ] + [ ] (4) C f WL WL N ms1 ms m ms1 ms m ox ms ( ) s ( ) m ms where K N, Cox, and f are a process-dependent constant on the order of 10-5 V F, a ate capacitance, and the operatin frequency of MOSFET, respectively. The final stae is a common-drain confiuration. The noise factor of this stae is derived in Eq. (5). NF 1 1 ( + ) (5) R mb mb B Fi. Measured and simulated of power ain (S1) of proposed amplifier A network analyzer carries out the measurement of the S-parameters. Capacitors C B1 and C B are used Thus, the total noise factor of the proposed amplifier is the effect of Eq. ()-(5). Assumin all transistors dimension is identical and 1 1 m1 = m = m = mp = mb = m = ms1 =, ms so the noise factor cab be rewritten as Eq. (6). 1 5KN R G ds NF ( ) + + ( + ) + (1 + )(6) f C WL R C ox m m m B N m

4 Proceedins of the 5th WSEAS International Conference on Sinal Processin, Istanbul, Turkey, May 7-9, 006 (pp ) From Eq. (6), the first term in Eq. (6) indicates the noise is sinificantly affected by flick noise at low frequency. As the frequency is increased, the noise factor can be affected mainly by the thermal noise. Furthermore, a hiher m can minimize the noise factor of the amplifier. However, in an amplifier desin, the used transistor size is the tradeoff between noise factor and total power consumption. The measured noise fiure of this amplifier is shown in Fi. 4, and the frequency rane is from 0Hz to GHz. It indicates that the noise fiure is around 10dB in the frequency rane of 100MHz and GHz, and this noise factor is reasonable in some applications. Fi. 5 shows the two-tone testin results to evaluate the linearity of the amplifier. The injected sinals are 0.9GHz and 1.1GHz respectively. The input third-order intercept point (IIP) is -1dBm. The comparison of this desin and other desins is shown in TABLE I and the proposed amplifier has better performance usin the proposed hih-quality active inductor. A. Worapishet 15 W. Sansen 8 C. K. Wan 14 Y. C. Chen 7 This Work Gain (db) Power Consumption (mw) Bandwidth (GHz) Processin (µm) Conclusion In this study, based on the hih-quality active inductor, a low power amplifier can achieve 18dB hih power ain, 1.GHz wide bandwidth, µm small die area, and 18 mw low power consumption under.5v dc power supply. Acknowledments The authors would like to thank National Chip Implementation Center (CIC) for chip fabrication. This work is sponsored by NSC of Taiwan under rant NSC E Fi. 4 Measured and simulated of noise fiure (NF) of proposed amplifier Fi. 5 Measured and simulated of input third-order intercept point (IIP) of proposed amplifier TABLE I COMPARISON WITH OTHER AMPLIFIER DESIGNS References: [1] G. D. Vendelin, A. M. Pavio, and U. L. Rohde, Microwave circuit desin usin linear and nonlinear techniques, (John Wily & Sons, New York, 1990) [] T. T. Y. Won, Fundamentals of Distributed Amplification, Norwood, MA: Artech, 199 [] E. W. Strid and K. R. Gleason, A DC-1-GHz monolithic GaAs FET distributed amplifier, IEEE Trans. Microwave Theory Tech., vol. 0, pp , July 198 [4] Y. Ayasli, R. L. Mozzi, J. L. Vorhaus, L. D. Reynolds, and R. A. Pucel, A monolithic GaAs 1-1-GHz travelin-wave amplifier, IEEE Trans. Microwave Theory Tech., vol. 0, pp , July 198 [5] P. J. Sullivan, B. A. Xavier, and W. H. Ku, An interated CMOS distributed amplifier utilizin packain inductance, IEEE Trans. Microwave Theory Tech., vol. 45, pp , Oct [6] F. Bruccoleri, E. A. M. Klumperink, and B. Nauta, Wide-Band CMOS Low-Noise Amplifier Exploitin Thermal Noise cancelin, IEEE Journal of Solid-State Circuits, Vol. 9, No., pp. 75-8, Feb. 004 [7] Y. C. Chen and S. S. Lu, Analysis and Desin of CMOS Broadband Amplifier with Dual Feedback Loops, IEEE ASIC Proceedins Conference, pp , 00

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