Design of a Wide Tuning-Range, High Swing Fully Differential CMOS VCO with a Differential Tunable Active Inductor

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1 Desin of a Wide Tunin-ane, Hih Swin Fully Differential CMOS VCO with a Differential Tunable Active Inductor Zahra Dorost Ghol, Noushin Ghaderi 2, Majid Ebnali-Heidari - Department of Enineerin, Shahrekord University, Shahrekord, Iran z.dorosthol@mail.com (Correspondin author) 2- Department of Enineerin, Shahrekord University, Shahrekord, Iran haderi.nooshin@en.sku.ac.ir 3- Department of Enineerin, Shahrekord University, Shahrekord, Iran ma.ebnali@mail.com eceived: Dec. 204 evised: March 205 Accepted: May 205 ABSTACT: In this paper, an inductor-less, hih frequency tunin rane and low power CMOS voltae controlled oscillator (VCO) is presented. The VCO can be implemented in 0.8 µm CMOS, with.8 V supply voltae. By usin a novel structure, a hih frequency tunin rane, low phase noise and low power consumption VCO, is obtained. In order to increase the frequency tunin rane, an active inductor is used. In addition, deep triode reion transistors are employed to enhance the swin of the output voltae. By usin the results of simulation with HSPISE software, the tunin rane, phase noise and power consumption are GHz, - 46 dbc/hz and 5.99 mw, respectively. KEYWODS: CMOS rin oscillator, voltae controlled oscillator, tunin rane, active inductor.. INTODUCTION Adjustable oscillators, which their output frequency is controlled by a voltae, are needed in many applications such as active adio Frequency Identification (FID) transponders, OC-48 application, frequency synthesizer module and PLL []. In addition, the oscillator with hih frequency tunin rane is desirable in modern communication systems. Generally, the CMOS oscillators are implemented at two types of rin oscillator and LC oscillator. In fact, the LC oscillators have low phase noise, better frequency stability and low power consumption compared to the rin oscillators. However, the LC oscillators will occupy a lot of places in circuit. In addition, frequency tunin rane of LC oscillators is limited [2]. In hih symbol rate of Gbps serial links, the slope of the risin and fallin edes of the clock should be maximized to achieve the minimum timin jitter. The timin jitter of VCOs is obtained by Eq. [3]-[4]. 2 n 2 dv 2 ( ) dt () Where the timin jitter, the threshold-crossins noise injected, and the threshold-crossins slew rate of the sinal, are Δτ 2, υ 2 n and dv respectively. As shown in dt Equation, the enhancement in the threshold-crossins slew-rate will decrease the timin jitter. The delay is developed by C time constant at the fundamental nodes. This limitation is a conventional drawback of VCO structures [5]. In order to considerably improve the slew rate of the output voltae, the spiral inductors are employed at fundamental nodes. However, several limitations exist in utilizin spiral inductors as a load, includin a lare component size, lare area and a small inductance. The active inductor in replace of spiral inductor is used to remove these limitations. Therefore by usin a differential active inductor, a very wide frequency tunin rane is obtained [6]. The rin oscillators with differential delay stae show the reater immunity to the common mode noise. Also, low phase noise and low power dissipation must be considered to the interation of oscillators [7]. In this paper, the desin and calculations of a new active inductor VCO are provided. In section (2), the circuit desin is described. In section (3), simulation results and discussions are presented. Conclusions are expressed in section (4). 2. DESIGN OF POPOSED ING VOLTAGE OSCILLATO A rin oscillator is formed by a number of ain staes in a loop. Generally, its oscillation frequency chanes 6

2 by usin a controllable voltae. In fact, the output frequency of an ideal VCO has a linear relation with its control voltae. The oscillation frequency of an N-stae rin oscillator is 2NT - d, where T d refer to the delay of each stae []. By considerin the resistance load of the differential delay stae at the output node as eq, the time constant will be equal to eq C L at the output node. Where, C L is the capacitance of the differential delay stae at the output node [2]. Therefore, the oscillation frequency is equal to : Fosc 2NeqCL (2) The oscillation frequency, power, area and noise performance are the key roles of the rin VCO desin [2]. Indeed, superior frequency tunin rane, low power, low area and low noise performance are desirable. In this paper, a two-stae rin oscillator VCO is proposed. Its structure is shown in Fiure. The circuit of each delay stae is illustrated in Fiure 2 [8]. Each delay stae circuit (Fiure 2) has two poles and one zero. The value of zero, neutralizes the small pole. Therefore the second pole that located at hiher frequencies, remains and causes to increase the bandwidth. The active inductor is employed in this circuit to avoid a lare chip area. In this circuit, M and M 2, are used as input pair. In addition, an active inductor as is shown in Fiure 3, is provided to increase the frequency rane [9]. Vctrl a X b X2 Vctrl c Fi.. Architecture of the two-stae rin oscillator Fi. 2. delay stae for rin oscillator [8] d The equivalent resistance of the active inductor circuit is obtained as follows [9]-[0]; Z o S 2 C Fi. 3. Active inductor load [9]-[0] d S( C d C s) C s m. C s S( C d. m ) m C S (3) By usin the spiral inductor as a load, as it is shown in Fiure 3(a), the transfer function of the delay stae is obtained by Equations 4 and 5 : A ( jw ) [ ( jwl )] (4) A v m o ml jwc v ( jwl) ( w LC ) jw ( C ) m o 2 o ml o ml m s (5) Where, C is the parasitic capacitance at the output node. Accordin to Barkhausen s criteria, at oscillation frequency of a rin oscillator, the total phase shift of a delay stae chain most be 80 in feedback system. Therefore, in a two stae rin oscillator, the phase shift of the transfer function will be equaled to 90. It means that, the oscillation frequency will be obtained as follows : F osc o ( o ml ) (6) 2 L. ml Therefore, if L is decreased, F osc will be increased. Accordin to Equation 3, o is equaled to / m3,4. The size of M L,2L and M 3,4 is chosen to have the value of o ml,2l lower than one. As can be seen in Fiure 2, the loads of delay stae are consisted of controllable transistors M 7 and M 8. By usin a variable load throuh varyin the ate voltae of M 7 and M 8, the oscillation frequency can be tuned. If M 7 and M 8 transistors are biased in deep triode reion, the resistance values of M 7 and M 8, are obtained as follows : M 7,8 (7) W pcox ( ) 7,8( V DD V ctrl Vthp ) L 62

3 Accordin to the above equation, by decreasin V ctrl, M7,8 will be decreased. It means that, the inductance will be decreased accordin to the followin relation : M 7,8Cs 3,4 L (8) m 3,4 Therefore, accordin to Equation 6, the oscillation frequency will be increased. By usin crossover transistor pair, M L and M 2L, 90 delay will be obtained by each delay cell. It means that, the Barkhausen s criteria will be satisfied by this oscillator. In addition, these transistors are used to chare and dischare of output node capacitor faster. The action of the delay stae can be characterized as follows :. If the input node of din becomes lower than another input node of din2, then M 2 will be on, while M will be off. Consequently, M 2L will be on and M L will be off. It means that, the output node (B) capacitor will be dischared throuh M 2L transistor. 2. If the input node of din becomes larer than another input node of din2, then M will be on, while M 2 will be off. Consequently, M L will be on and M 2L will be off. Therefore, the capacitance at the output node (B) doesn't dischare throuh M 2L transistor. This capacitor will be chared throuh M 4 and controllable M 7,8 transistor (near V DD ). In both actions of the full circuit, controllable PMOS transistors of M 7 and M 8, adjust the entire charin and discharin of capacitors at the output node of delay stae. One of the most important problems of this circuit (Fiure 2) is its limited frequency tunin rane. Another problem of the circuit is its limited output voltae swin, which is caused by usin the active inductor. Triode reion transistors M 5, M 6, M 77 and M 88 are added to solve the above problems, which are shown in Fiure 4. Fi. 4. Frequency rane of the proposed rin oscillator The dc equivalent resistance at the output node is iven by Equation 9. It shows that eq has a small value, which cause to improve the oscillation frequency and frequency tunin rane. eq ( L ) (9) m3,4 m L,2L m3,4 m L,2L The value of L in Equation 9 is obtained as follow; (0) L M 5,6 M 77,88 M5,6 are biased in deep triode reion. Therefore they have a small output resistance. As mentioned before, if the value of V ctrl becomes low, M5,6 and therefore L will be decreased, while the values of m3,4 and ml,2l are constant. Accordin to Eq. 9, if L is decreased, eq will be decreased. It means that, the oscillation frequency will be increased. Indeed, accordin to the Equation 2, conclusion can be obtained as follows : Vctrl L eq Fosc () 3. SIMULATION ESULTS The proposed voltae controlled rin oscillator circuit is simulated based on TSMS 0.8µm CMOS process model usin HSPICE. The tunin rane of Fiure 2 and proposed VCO are shown in Fiure 5 and Fiure 6, respectively, where V crtl and V ctrl2 are connected toether and considered as a sinle V ctrl in the proposed VCO. As can be seen, the frequency tunin rane is hiher in the proposed VCO. Furthermore, the performance of its linearity is much better. In the proposed VCO circuit, the control voltae value is varied between 0 to.3v, which cause in a frequency rane of 9.6 GHz to 5.49 GHz (Fiure 6). Otherwise, if V ctrl is chaned between 0 to.3v and V ctrl2 is fixed at 0V, the frequency tunin rane will be chaned between 9.6 GHz to 8.43 GHz, as is shown in Fiure 7. Also, if V ctrl2 is chaned between 0 to.3v and V ctrl is fixed at 0V, the frequency tunin rane will be chaned between 9.6 to 7.36 GHz (Fiure 8). As can be seen, by interatin the Fiures 7 and 8 toether, Fiure 6 will be obtained, which is a more linear function of V ctrl. The differential waveforms of the VCO at a frequency of 7.64 GHz are illustrated in Fiure 9. The output spectrum which is simulated at 7.64 GHz is shown in Fiure 0. The simulation result illustrates a maximum peak at 7.64 GHz of oscillation frequency, with the spectrum of complementary skirtin spurs. Eye diaram and jitter historam at 7.64 GHz workin frequency are illustrated in Fiures and 2. These fiures exhibit about 2.58ps and 3.3 ps MS and peakto-peak jitters, respectively. By usin Equation 2, the phase noise is obtained as follows [3] : f 0 t 2 ( vco S rms ) (2) 2 T f 0 L 63

4 Where, f 0 is center frequency, f is certain frequency offset, Δt vco-rms is rms jitter, and T 0 is period of sinal. The phase noise of the VCO at the workin frequency in different frequency offset is presented in Fiure 3. The output phase noise is - 46 dbc/hz at a MHz frequency offset. The value of merit of the proposed VCO accordin to Equatin 3 [], is dbc/hz. f { } 20lo{ 0 P FOM L f } 0lo{ diss } (3) f mw Where, L{Δf}, Δf, f 0 and P diss are phase noise, certain frequency offset, center frequency and power dissipation, respectively. A comparison between proposed work with previous rin oscillators is performed in Table. The proposed oscillator obtained a FOM of dbc/hz. In the proposed rin oscillator the frequency tunin rane is increased and the value of phase noise is almost improved while the power consumption of the rin oscillator is minimum. Fi. 7. Frequency rane of the proposed rin oscillator for Vctrl variations and constant Vctrl2 Fi. 5. Frequency rane of the Fi. 2 Fi. 8. Frequency rane of the proposed rin oscillator for Vctrl2 variations and constant Vctrl Fi. 9. Transient response of VCO at 7.64 GHz Fi. 6. Frequency rane of the proposed rin oscillator 64

5 Fi. 2. Output jitter historam at 7.64 GHz Fi. 0. Output spectrum of the VCO at center frequency Fi.. Output jitter eye diaram at 7.64 GHz Fi. 3. Simulated phase noise at 7.64 GHz for different frequency offsets 4. CONCLUSIONS In this paper, a two-stae differential rin oscillator is presented. By usin an active inductor in each delay stae, a wide tunin rane is obtained. In addition, the deep triode reion transistors are used to increase the swin of the output voltae. The results show that maximum tunin rane, phase noise and power consumption are GHz, - 46 dbc/hz and 5.99 mw, respectively. This circuit illustrates a hih FOM performance compared to the previous works. Thus this VCO can be expressed as one of the hih tunin rane VCO, which is suitable for PLL applications. in Oscillator CenterF req (GHz) Table. The performance comparisons of rin oscillators Tunin ane (GHz) Phase Noise (dbc/hz) SupplyV oltae (V) FOM (dbc/hz) Power (mw) Technoloy (µm) Proposed @MHz [2] @0MHz [7] @MHz [2] @0MHz [5] _ @0MHz.8 _ [6] @0MHz [7] _ @0.6MHz.8 _ [8] @MHz No. of staes 65

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