A Novel Low Power UWB Cascode SiGe BiCMOS LNA with Current Reuse and Zero-Pole Cancellation

Transcription

1 A Novel Low Power UWB Cascode SiGe BiCMOS LNA with Current Reuse and Zero-Pole Cancellation Chunbao Ding, Wanrong Zhang, Dongyue Jin, Hongyun Xie, Pei Shen, Liang Chen, School of Electronic Inforation and Control Engineering, Beijing University of Technology, Beijing 004, China Abstract A low power cascode SiGe BiCMOS low noise aplifier (LNA) with current reuse and zero-pole cancellation is presented for ultra-wideband (UWB) application. The LNA is coposed of cascode input stage and coon eitter (CE) output stage with dual loop feedbacks. The novel cascode-ce current reuse topology replaces the traditional two stages topology so as to obtain low power consuption. The eitter degenerative inductor in input stage is adopted to achieve good input ipedance atching and noise perforance. The two poles are introduced by the eitter inductor, which will degrade the gain perforance, are cancelled by the dual loop feedbacks of the resistance-inductor (RL) shunt-shunt feedback and resistance-capacitor (RC) series-series feedback in the output stage. Meanwhile, output ipedance atching is also achieved. Based on TSMC 0.35μ SiGe BiCMOS process, the topology and chip layout of the proposed LNA are designed and post-siulated. The LNA achieves the noise figure of.3~4.db, gain of 8.9~0.dB, gain flatness of ±0.65dB, input third order intercept point (IIP 3 ) of -7dB at 6GHz, exhibits less than 6ps of group delay variation, good input and output ipedances atching, and unconditionally stable over the whole band. The power consuing is only 8W. Index Ters Current reuse, Ultra-wideband, Low noise aplifier, low power I. INTRODUCTION The standard of Ultra-Wideband (UWB) was set up and approved 7.5 GHz band (3.-0.6GHz) for UWB applications by Federal Counications Coission (FCC) in 00. UWB receivers have soe advantages such as strong anti-interference, high transission rate, wide frequency bandwidth, and low cost[].. As the first stage of UWB receivers, low noise aplifier (LNA) perforance has an iportant influence on the whole receiver syste. UWB LNA should have low noise figure and high gain to elevate receiver signal to noise ratio (SNR), low power consuption to preserve battery powered life of portable devices, good ipedance atching to reduce return loss, and absolute stability in the whole band. To obtain high gain, distributed and ultistage LNAs usually cascade several stages [,3]. For ultistage topologies, ultiple dc bias paths are needed, which largely increase the total power consuption. To realize low power, coon gate (CG)-coon source (CS) and CS-CS current-reuse structures[4][5][6] are generally adopted, eanwhile, high gain also can be achieved. Therefore in this paper, the current reuse topology is used, but in a novel cascode-coon eitter (CE) topology style. In the topology, the cascode structure is used as the input stage to iprove the reverse isolation of the LNA. The good input ipedance atching and noise perforance are achieved by eitter inductive degeneration technique. In order to cancel two poles arising fro the eitter inductor, and hence to flat the gain perforance, the dual feedback topology of RL shunt-shunt feedback and RC series-series feedback in the output stage is proposed, eanwhile, the output ipedance atching is also achieved. Finally, based on SiGe HBT technology, the UWB LNA is designed and realized. Corresponding author. Tel.: E-ail address: wrzhang@bjut.edu.cn

2 II. Topology and Analysis of the Proposed LNA A The Proposed Current-Reuse Cascode LNA Figure Scheatic of traditional two stages LNA Figure Scheatic of the proposed current reuse LNA Fig. is a traditional two stage LNA topology. The cascode structure is used as the input stage due to its high reverse isolation and good frequency characteristic[7], coon eitter transistor Q 3 is the output stage for aplifying the input signal again to achieve high gain. Input and output stages are connected as a cascaded structure by capacitor coupling path. Note that two bias currents provide for cascode and Q 3, large power consuption is inevitable. In order to realize low power consuption, a current reuse topology with L and C is proposed, as shown in Fig.. It has only one current biasing strea for Q, Q and Q 3 in DC path, reduces current consuption by the reuse of bias current. It is noted that in the AC path, the signal is aplified by the input stage, the series inductor L provides a high ipedance path to block the signal, and the capacitor C decouple the AC interaction between the first and second stage, therefore the signal can be again aplified by the second stage, high gain can be achieved the sae as two stages cascade topology. The bypass-capacitor C 3 avoids the signal interference coupling back to cascode. To show that the current reuse LNA can realize low power consuption, eanwhile achieve high gain, the analysis is given as follows. Copared Fig. with Fig., the power consuption of traditional aplifier and current reuse aplifier are: P V ( I I ) cascade cc P V I currentreuse cc c When V cc =V cc, the input ipedances of traditional aplifier and current reuse aplifier are all atched well in the sae sizes of Q, Q and Q 3, I is approxiately equal to I c. Consequently, power consuption of the current-reuse aplifier is saller than the traditional aplifier. Since the current gain of coon base transistor Q is nearly unity, the effective transconductance of the cascode aplifier is equal to the transconductance of Q [7]. So the effective transconductances of traditional aplifier and current reuse aplifier are sae, and obtained as G G g g () cascade currentreuse, Q, Q3 () Therefore, when I I I C, the current reuse aplifier reduces the power consuption without affecting the power gain. B. Input Ipedance and Noise Analysis

3 Figure 3 Input stage with eitter degenerative inductive Figure 4 Sall signal equivalent circuit Since the LNA is the first odule of the receiver, the input ipedance ust be atched to the source ipedance (50 Ω) so as to reduce the distortion caused by signal reflection. The eitter degenerative inductive technique is adopted to achieve wideband input ipedance atching, as shown in Fig. 3. Fig. 4 shows its sall signal equivalent circuit, input ipedance Z IN is derived as follows: Lg in b (3) jwc C Z r jwl The input ipedance atching can be achieved by adjusting the inductor value and the bias current of the circuit. The noise characteristic is also very iportant for the LNA. After the ipedance atching is achieved, we now turn to noise characteristic analysis. According to the Friis noise figure (NF) equation of cascade aplifier [8], when the gain of the first stage in the LNA is high enough, the total NF of the LNA is ainly doinated by the first stage. Therefore, it is assued that the overall noise figure ainly arises fro the first stage in the following analysis. Although the coon base stage in the cascode aplifier adds soe noise to the LNA, the noise fro it is very sall at the output copared with the noise fro the coon-eitter stage. Thus, for siplification of calculation, the effect of coon base part is oitted. In order to calculate the noise perforance, the sall signal noise odel and equivalent input referred noise odel for cascode stage with eitter degenerative inductive technique (CAEDI) are shown in Fig. 5 and Fig. 6, respectively. Figure 5 sall signal Noise odel of CAEDI Figure 6 Equivalent input referred noise odel of CAEDI The ean square value of equivalent noise voltage v iedi is increased due to the eitter inductor feedback [7], can be derived as: qi f w v ktrf qi f jwl qi jwl f (4) C iedi 4 b B C g wt The ean square value of equivalent noise current i iedi can be expressed as w i qi f qi f (5) iedi B wt where, r b is the base series resistance, k is Boltzann s constant, q is the electron charge, T is absolute teperature in degrees Kelvin, Δf is frequency bandwidth of interest. v iedi and i iedi is correlated each other. The noise paraeters (equivalent noise resistance R n, the optiu noise ipedance Z OPT, and the iniu noise figure NF in ) are derived as follows: C

4 The NF is calculated as: g w w R R g w L wl n b ( ) e e wt g wt g w g w Z ( ) R j( wl ) OPT b e g w g wt wtg w g ( ) wt wt NF g w g in wt ( ) g w g ( ) wt NF NFin ZOPT Z R S S (6) (7) where g =qi C /kt, β is the current gain, w T =g /(C π +C bc ), Z S is the source ipedance (50 Ω). According to the Eq (6) and Eq. (7), NF can be optiized by adjusting the structure of transistors, bias current and inductor L. Therefore, in order to achieve good ipedance atching and noise perforance, the coon eitter transistor in cascode stage is equipped with A E = (0.3 0) μ, and the value of inductor L is 0.8 nh. Furtherore, the poles will be introduced by the eitter inductor, the gain perforance is degraded. In the following we analyze that and try to copensate the gain degradation. C. Zero-Pole Cancellation The transfer function of cascode input stage with eitter inductive degeneration is derived as: i out v Lg s ( R ) g sl S rb sc s LC C The ter s LC π + in (8) can be ignored over the band of interest since the input atching network is a low-q circuit and the center frequency f o = 6.5 GHz. Therefore, the pole P 0 and P contributed by the eitter inductor are expressed as: P 0 0 P g L g (8) (9) Figure 7 The proposed current reuse LNA with dual feedback output stage The poles P 0 and P degrade the gain perforance of the LNA. Therefore, in order to flat the gain perforance, the additional zeros should be introduced to copensate the degradation. So the resistance-inductor shunt feedback and resistance-capacitor series feedback are adopted in the output stage Q 3 of the LNA, as shown in Fig. 7. The transfer function of the output stage is derived as: v v g ( R sc ) z ( ) out3 out3 3 4 f f 4 L in3 iin3 vin3 ( RsC4) g3r Rf slf ( RL sl4) ( Rf slf ) RL sl4 4 3 f f 4 ( R sl ) sl R ( RsC 4 g3r)( Rf sl3)[( RL sl4) ( Rf sl3) RLsL4] [( RsC g R) sc ( R sl )( RsC)] [( R sl )( R sl ) R sl ] g R sl ( R sl )( R sc ) L 4 f f L 4 3 L 4 f f 4 where, v out3, v in3, i in3 and z in3 are the output voltage, input voltage, input current and input ipedance of (0)

5 the output stage, respectively. According to the Eq. (0), three new zeros and one pole are introduced and expressed as g R g R R Z 0 Z Z 3 3 f f 0 g3lf ( g3rf ) R Lf RR f L( g3r) P R ( g R ) L C ( R R R R R ) R R g L L 3 f 4 L f L f f L 3 4 () The pole P 0 fro Eq. (8) can be cancelled with zero Z 0 fro Eq. () introduced by the load inductor L 4, eanwhile pole P introduced by the R f -L f feedback is also cancelled with the zero Z by adjusting the resistance R f and inductor L f. The additional pole P introduced by the dual feedback network will be cancelled with the zero Z by adjusting the resistance R and capacitance C 4. Therefore, the gain perforance can be iproved by the resistance-inductor shunt and resistance-capacitor series feedback by pole-zero cancellation. D. Circuit Topology and Chip Layout The coplete topology of the proposed UWB LNA with current reuse is shown in Fig. 8. The input ipedance atching is achieved by eitter inductor L. Output ipedance atching is achieved by R f -L 3 shunt feedback and R -C 4 series feedback, eanwhile the bandwidth is also extended by the pole-zero cancellation. Resistance R f and R are used for self-biasing Q 3 and Q. The irror current source Bias provides stable bias current for transistors Q. Inductor L and capacitor C are used for the current reuse structure. Based on TSMC 0.35μ SiGe BiCMOS process, the chip layout of the UWB LNA has been designed, as shown in Fig. 9, the area is Figure 8 Topology of proposed UWB LNA Figure 9 Chip layout of proposed UWB LNA III Verification and Result Analysis The proposed UWB LNA is post-siulated with Spectre of Cadence, s EDA using TSMC 0.35 μ SiGe BiCMOS process design kit(pdk), the following figures show the post-siulation results. Figure 0 NF and S and Stability Factor K of proposed LNA Figure S, S, S of proposed LNA

6 Fig. 0 depicts the S and NF of the proposed UWB LNA with current reuse together with S of the traditional two stages LNA. The peak S is 0. at 8.6GHz with the power consuption of 8W. The gain flatness is ±0.65 db fro 3. to 0.6 GHz. The results deonstrate that the LNA with current reuse can indeed achieve the siilar S characteristics and the gain flatness is iproved copared with cascade LNA. Nevertheless, the power consuption is approxiately half of the traditional two stages LNA. The validity of the proposed current reuse and zero-pole cancellation approach is verified. In addition, the proposed UWB LNA has good noise perforance, the noise figure is.3~4. db. The input return loss S, output return loss S and reverse isolation S versus frequency are plotted in Fig.. As shown, the S and S are all lower than -0 db while S is lower than -4 db. The stable factor K in Fig. 9 is larger than.6 and Δ = S S -S S <0.3. All the results indicate this LNA has good ipedance atching, reverse isolation and is absolute stability fro 3. to 0.6 GHz. As the derivation of the phase of transfer function, Group delay is usually used to evaluate phase nonlinearity. As shown in Fig., the group delay variation of LNA is ±6 ps, achieving good phase linearity. Fig. 3 shows the input 3 rd order intercept point (IIP 3 ) of UWB LNA, which is -7 db at 6 GHz when a two tone test is perfored with 0 MHz spacing for the entire UWB band. Therefore the LNA have good linearity, and eets the requireent of UWB receivers. Figure Group delay of proposed LNA Figure3 IIP 3 of proposed LNA at 6 GHz Table I shows the suary of the proposed LNA and coparison with the recently reported SiGe and CMOS UWB LNAs. The proposed LNA has lower power consuption and better phase linearity with high gain and low noise copared with the previously published UWB LNAs [0,,3,5]. Although the two LNAs [, 4] have uch lower power consuption, the proposed LNA exhibits better gain and group delay. In addition, the proposed LNA achieves good gain flatness. TABLE I SUMMARY OF THE PROPOSED SiGe UWB LNA, AND COMPARISON WITH THE RECENTLY REPORTED SiGe AND CMOS UWB LNA Process Frequency (GHz) Peak S (db) Gain flatness(db) Miniu NF(dB) Group delay variation(ps) IIP 3 (db) Power consuption(w) This work 0.35μ SiGe ± ±6-7@6GHz 8 [0] 0.8μ SiGe ± NA -.7@3GHz 4.5 [] 0.5μ SiGe ±.5.8 NA -8@3GHz 9.7 [] 0.5μ SiGe ± ±30 NA 3.5 [3] 0.8μ CMOS ± ±48 NA 33. [4] 0.8μ CMOS NA 4 ±40-6.7@6GHz 9 [5] 0.8μ SiGe ±.05.8 NA.@6GHz 6

7 IV CONCLUSION A new topology of UWB (3.~0.6 GHz) SiGe LNA is proposed to realize low power consuption and high gain. The LNA is coposed of cascode input stage and coon eitter output stage. Cascode input stage together with eitter degenerative inductive ake LNA a good input ipedance atching and noise perforance. At output stage, the dual loop feedbacks of resistance-inductor shunt feedback and resistance-capacitor series feedback are eployed to flat gain perforance by the pole-zero cancellation. The proposed SiGe UWB LNA exhibits peak gain of 0. db with the power consuption 8 W, eanwhile achieves good gain flatness, low NF, better phase linearity, good input and output ipedances atching over the UWB. REFERENCES [] D. Porcino and W. Hirt. Ultra-wideband radio technology: Potential and challenges ahead, IEEE Counication Magazine 003, 4(7): [] R.C. Liu, C.-S. Lin, K.-L. Deng, and H. Wang. A GHz 0.6 db CMOS cascode distributed aplifier. VLSI Circuits Syp. Tech. Dig., Jun [3] Y. Shi, C.W. Ki, J. Lee, and S.-G. Lee. Design of full band UWB coon-gate LNA. IEEE Microw. Wireless Copon. Lett., 007, 7(0), [4] H. K. Cha, M. K. Raja, X. Y. Yuan, et al. A CMOS MedRadio Receiver RF Front-End With a Copleentary Current-Reuse LNA, IEEE Transactions on Microwave Theory and Techniques, JULY 0, 59(7), [5] R. M. Weng, C. Y. Liu, P. C. Lin. A Low-Power Full-Band Low-Noise Aplifier for Ultra- Wideband Receivers. IEEE Transactions on Microwave Theory and Techniques, 00, 58, [6] S. MK, Solian AM. Low-voltage low-power CMOS RF low noise aplifier. AEU International Journal of Electronics and Counications 009; 63(6): [7] P. R. Gray and R. G. Meyer. Analysis and Design of Analog Integrated circuit. Fourth Edition. Beijing: Higher Education press, 005 [8] H. T. Friis. Noise figure of radio receivers, Proc. IRE 944; 3(7): [9] Sasilatha T, Raja J. A V,.4 GHz low power CMOS coon source LNA for WSN applications. AEU International Journal of Electronics and Counications 00, 64: [0] J. Lee and J. D. Cressler, Analysis and design of an ultra-wideband low-noise aplifier using resistive feedback in SiGe HBT technology, Microwave Theory and Techniques. 006; 54(3): [] D. Barras, F. Ellinger, H. Jackel, and W. Hirt. A low supply voltage SiGe LNA for ultra-wideband frontends, IEEE Microw. Wireless Copon. Lett. 004; 4(0): [] B. Shi and M. Y. W. Chia. A SiGe Low-Noise aplifier for GHz ultra-wideband wireless receivers, in IEEE Radio Freq. Integrated Circuits Syp [3] Y. Lu, K. S. Yeo. A. Cabuk, J. Ma, M. A. Do, and Z. Lu, A novel CMOS low-noise aplifier design for 3.-to-0.6-GHz ultra-wideband wireless receiver, IEEE Trans. Circuits Syst. I, Reg. Papers 006; 53(8): [4] A. Bevilacqua and A. M. Niknejad. An ultra wideband CMOS low noise aplifier for GHz wireless receivers, IEEE J. Solid-State Circuit 004: 39(): [5] Y. Lu, R. Krithivasan, W. M. L. Kuo, and J. D. Cressler. A.8 3. db noise figure (3 0 GHz) SiGe HBT LNA for UWB applications, in IEEE Radio Freq. Integrated Circuits Syp