Differential Difference Current Conveyor Based Cascadable Voltage Mode First Order All Pass Filters

Transcription

1 Differential Difference Current Conveyor Based Cascadable ltage Mode First Order All Pass Filters P..S. MURALI KRISHNA, NAEEN KUMAR, AIRENI SRINIASULU, R.K.LAL Department of Electronics & Communication Engineering ignan University, Guntur Birla Institute of Technology, Mesra INDIA Abstract: - This paper proposes two first-order all-pass filters using DDCCs as active elements, one resistor and one capacitor. Both proposed filters have two DDCCs, one grounded resistor and one grounded capacitor. Thus the two topologies are having minimum number of components and there is no need for matching constraints on passive components. The performance of the proposed circuits is examined using PSPICE simulations with the model parameters of a.5 µm CMOS process. Obtained results demonstrate excellent agreement with theoretical values. Keywords: - Current conveyor, CCII, DDA, DDCC, all-pass filter, SPICE Introduction Second generation current conveyor (CCII), introduced in 97 [], has been a popular building block in voltage-mode and current-mode analog applications likes oscillators, various types of filters and amplifiers, due to its high and versatile performance, low power consumption, high bandwidth and high output voltage swing. Many CCII applications were available in the literature [2-3]. But CCII has a drawback. It has only one voltage input terminal. Thus it is not suitable for applications that use differential inputs or floating inputs. So, such applications require two or more CCIIs. Differential difference current conveyor (DDCC) is more suitable in such applications. CMOS based DDCC was introduced in 996. DDCC encompasses the good features of Differential difference amplifier (DDA) like high input impedance, low output impedance, less number of components and capability of performing arithmetic operations, and advantages of CCII such as high gain, accuracy and bandwidth. DDCC applications such as realizing squarer, square rooter and multiplier circuits, differential integrators, and voltage mode and current mode low-pass filters and high-pass filters were also demonstrated [4]. Later, many applications using DDCC were presented [5-2]. All-pass filters of first-order are widely used in analog signal processing applications for changing the phase shift, where amplitude remain unchanged. They are also used to construct quadrature and multiphase oscillators. Recently many voltage-mode and currentmode all-pass filters were presented using CCII or DDCC. Grounded passive components provide tuning facility that is required in analog ICs after manufacture, because of the problem of high tolerances. The frequency of oscillation can be adjusted by a grounded resistor without disturbing the oscillation condition. Grounded capacitors are easier for fabrication and have less parasitics compared with floating capacitors [5-8], [-3], [8-27]. Here two new first order all-pass filters are proposed using DDCCs as active elements. The remaining sections of the paper are organized as follows. The DDCC fundamentals and proposed design are presented in section 2 and 3. Non-ideal analysis is included in section 4. Finally, simulation results and conclusions are given in section 5 and 6 respectively. 2 DDCC Fundamentals The symbol of five-port DDCC is shown in Fig.. The internal structure of this device is shown in Fig. 2 and it can be characterized by the following matrixrelations between various voltage and current variables [2, 28]. I I I I Y β -β 2 β 3 α I In the DDCC,,, and are three voltage input terminals with high input impedance. Terminal is a low impedance current input terminal. There is a high impedance current output terminal. The hybrid matrix can be represented by the following equations: I I I, β β + β, Y and I Y Y 2 3 () α I (2) ISBN:

2 Here α represents the current tracking error from to terminal. β, β 2 and β 3 represent the voltage tracking errors from,, to terminal. Ideally β β 2 β 3 α. Actually these tracking errors arise due to parasitic capacitance and resistance of the DDCC. It provides to 8 phase shift. Its phase response is 2 tan ( ωcr) (6) Y Y2 Y3 I Y I Y2 I Y3 DDCC I i DDCC C R DDCC 2 I Fig. Symbol for DDCC Fig. 3 Proposed all-pass filter dd M 7 M 8 M 9 M i DDCC C DDCC 2 M M 2 M 4 M 5 R b ss M 3 M 6 M M 2 Fig. 2 Device level presentation of DDCC 3 Proposed Design The first proposed filter is shown in Fig. 3. In this topology, DDCC outport is fed to the input port of DDCC 2 with a grounded capacitor C. And also, DDCC terminal is fed to the input port of DDCC 2 with a grounded resistor R. The voltage transfer function is scr (3) i scr + It provides 8 to phase shift. And the phase response is 8 2 tan ( ωcr) (4) The second proposed filter is shown in Fig. 4. In this topology, DDCC outport is fed to the input port of DDCC 2 with a grounded capacitor C. And also, DDCC terminal is fed to the input port of DDCC 2 with a grounded resistor R. The voltage transfer function is scr + scr i (5) Fig. 4 Proposed all-pass filter 2 4 Non-Ideal Analysis So far, ideal characteristics for the DDCC are being considered in the analysis. However, in this section of investigation, the analysis could change if the parameters of non-idealities are taken for granted. From Fig. 3, we can write voltage transfer function as β ( β 2sCR αβ 22 ) (7) i scr+ and phase response as β 2ωCR ωcr 8 tan tan (8) αβ 22 From Fig. 4, we can write voltage transfer function as β ( αβ 2 β 22sCR) (9) i + scr and the phase response as β 22ωCR ωcr tan tan () α β α β 2 Effects of non-ideality on pole frequency: Ideally, from Eqs. (3) and (5), we can observe that the pole/zero frequency will be ω RC and its p / z P / sensitivity due to passive element is C. From 2 S ω R, ISBN:

3 Eqs. (7) and (9) we can observe that the pole frequency is different from the zero frequency and it is the following characteristic equations. For Fig. 3, ω α β RC, ω α β RC and P 2 22 β 2 αβ 2 β 22 For Fig. 4, ω P α β2 RC, ω RC After completion of analysis we found that the sensitivity of pole or zero frequency due to DDCC is not more than unity. The sensitivities for Fig. 3 are P S ω α, β2 () z S ω α β2β22 (2) and for Fig. 4, they are denoted by S ω β P α 2 (3) z S ω α β 2β 22 (4) In comparison with the published all pass filter, this filter can have additional transfer function, scr 2 i + scr (5) i.e., this filter is also capable of producing amplified output by connecting the terminal to. 5 Simulation Results The proposed all-pass filters were simulated using PSPICE with.5 µm MITECH parameters. The parameters are given in table I and the aspect ratios of transistors are given in table II. The supply voltages of proposed all-pass filter circuits are +2.5 and the biasing voltage B is -.7. The simulation results of all-pass network shown in Fig. 3 are given in Fig. 5 and Fig. 6 and those of all-pass network shown in Fig. 4 are given in Fig. 7 and Fig. 8. The passive component values selected are R kω, C pf and the pole frequency f 59 KHz. TABLE I.5 µm MIETEC CMOS PROCESS MODEL PARAMETERS; LEEL-3 MODEL NT NMOS LEEL3 +UO46.5 TO.E-8 TPG TO.62 JS.8E- 6+J.5E-6 RS47 RSH2.73 LD. ETA+MA3E3 NSUB.7E7 PB.76 PHI.95+THETA.29 GAMMA.69 KAPPA. AF+WD.E-6 CJ76.4E-5 MJ.357CJSW5.68E-+MJSW.32 CGSO.38E- CGDO.38E-+CGBO3.45E- KF3.7E-29 DELTA.42+NFS.2E MODEL PT PMOS LEEL3 +UO TO.E-8 TPG TO-.58 JS3.8E- 6+J.E-6 RS886 RSH.8 LD.3EETA+MA5E3 NSUB2.8E7 PB.9PHI.95+THETA.2 GAMMA.76 KAPPA2 AF+WD.4E-6 CJ85E-5 MJ.429 CJSW4.67E- +MJSW.63 CGSO.38E- CGDO.38E-+CGBO3.45E- KF.8E-29 DELTA.8 +NFS.52E TABLE II. TRANSISTORS ASPECT RATIOS TRANSISTOR W (µm) L (µm) M, M 2, M 4, M M 3, M M 7, M M 9, M..5 M, M Conclusion In this paper, two new voltage-mode first-order allpass networks employing two DDCCs, one grounded resistor, another grounded capacitor are presented. Both use optimum and canonical number of passive components. So there is no need for passive component matching. No capacitors are connected at terminal. We found that Total Harmonic Distortion (THD) of both circuits is less than 4%. However its value is decreasing for first proposed circuit with increasing frequency and it is less than 2%. Both the circuits have grounded resistor and grounded capacitor, which provide the tunable property. The circuits are verified using SPICE simulation and the simulated results agreed with theoretical ones. These are alternative better circuits than the ones present in [5], and have added advantages of parasitic resistances and capacitances that can be minimal. The circuit presented in [8], provides only low output impedance. And circuits presented in [5-7] uses the floating passive element and have element matching restrictions. References [] A. S. Sedra and K. C. Smith, A second generation current conveyor and its application, IEEE Trans. ISBN:

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5 Fig. 5 Phase and magnitude plots of the proposed circuit of Fig. 3 Fig. 6 Dependence of output voltage harmonic distortion on input voltage frequency for.2 PP of Fig. 3 Fig. 7 Phase and magnitude plots of the proposed circuit of Fig. 4 Fig. 8 Dependence of output voltage harmonic distortion on input voltage frequency for.2 PP of Fig. 4 ISBN: